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1 79 jguarin200
-- Author : Julian Andres Guarin Reyes.
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-- Project : JART, Just Another Ray Tracer.
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- The following code is licensed under GNU Public License
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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 -- This file is part of JART (Just Another Ray Tracer).
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    -- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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    -- it under the terms of the GNU General Public License as published by
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    -- the Free Software Foundation, either version 3 of the License, or
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    -- (at your option) any later version.
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    -- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    -- GNU General Public License for more details.
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    -- You should have received a copy of the GNU General Public License
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    -- along with JART (Just Another Ray Tracer).  If not, see <http://www.gnu.org/licenses/>.library ieee;
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-- Unitary Ray Set generator. 
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-- This file is the description of    
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_signed.all;
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use work.powerGrid.all;
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entity urs is
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        generic (
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                GRIDS   : integer := 2;         -- The number of grids.
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                TOP             : integer := 1024;      -- Range.
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                SCREENH : integer := 200;       -- Screen Height Resolution.
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                SCREENW : integer := 320        -- Screen Width Resolution.
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        );
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        port (
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                clk,rst,ena                     : in std_logic;                                         -- The usual control signals
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                y                                       : out integer range TOP/2 to TOP-1;
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                xn, xp, zp, zn,yp       : out std_logic_vector (mylog2(TOP-1,"signed")*GRIDS-1 downto 0); -- Signed
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                urs                                     : out std_logic
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        );
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end entity;
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architecture rtl of urs is
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        constant localwidth0 : integer := mylog2(TOP-1,"signed"); -- 0 to 9 value. 10 sign.
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        signal szpos,szneg,sxpos,sxneg          : integer range -TOP to TOP-1;
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        signal sypos                                            : integer range 0 to TOP-1;
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        signal slockd,slockq                            : std_logic;
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        signal grid_enable                                      : std_logic_vector (GRIDS-1 downto 0);
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        -- slockd : marks whenever a screen line has been finished.
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        -- slockq : indicates if ycompo has already started.
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begin
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        xcompo : zu
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        generic map (
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                VALSTART => 34  -- Value required for X component.
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        )
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        port map (
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                clk             => clk,
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                rst     => rst,
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                ena     => ena and slockq,
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                clr             => slockd,
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                zpos    => sxpos,
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                zneg    => sxneg
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        );
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        zcompo : zu
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        port map (
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                clk             => clk,
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                rst             => rst,
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                ena             => slockd,
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                clr             => slockd and not(slockq),
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                zpos    => szpos,
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                zneg    => szneg
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        );
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        ycompo : yu
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        generic map (
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                TOP     => TOP,
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                SCREENW => SCREENW
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        )
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        port map(
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                clk             => clk,
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                rst             => rst,
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                ena             => ena,
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                lineDone=> slockd,
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                ypos    => sypos
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        );
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        process (clk,rst,ena)
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                variable colcounter             : integer range 0 to (SCREENW/2)-1;
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                variable linecounter    : integer range 0 to (SCREENH/2)-1;
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                variable gridindex              : integer range 0 to GRIDS-1;
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        begin
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                if rst ='0' then
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                        slockq          <='0';
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                        urs                     <='0';
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                        linecounter := 0;
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                        gridindex       := 1;
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                elsif rising_edge(clk) and ena='1' then
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                        y <= sypos;
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                        -- Calculate the locked 
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                        if slockq = '1' then -- If we already load the initial ypos value, then we must be unlocked!
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                                for i in 0 to GRIDS-1 loop
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                                        if gridindex=i then
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                                                grid_enable(i)<='1';
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                                        else
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                                                grid_enable(i)<='0';
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                                        end if;
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                                end loop;
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                                gridindex:=gridindex+1;
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                                if slockd = '1' then -- This is the end....  of the line....... my friend... This is the end...... 
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                                        if linecounter = (SCREENW/2)-1 then
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                                                urs <= '1'; -- Finished the URS.
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                                        else
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                                                linecounter:=linecounter+1;
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                                        end if;
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                                end if;
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                        else
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                                slockq <= slockd or slockq;
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                        end if;
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                end if;
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        end process;
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        rowExits : for i in 0 to GRIDS-1 generate
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                process (clk,rst,grid_enable(i))
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                begin
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                        if rst = '0'  then
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                                xp(localwidth0*(i+1)-1 downto (i*localwidth0))<= (others=>'0');
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                                xn(localwidth0*(i+1)-1 downto (i*localwidth0))<= (others=>'0');
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                                zp(localwidth0*(i+1)-1 downto (i*localwidth0))<= (others=>'0');
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                                zn(localwidth0*(i+1)-1 downto (i*localwidth0))<= (others=>'0');
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                                yp(localwidth0*(i+1)-1 downto (i*localwidth0))<= (others=>'0');
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                        elsif rising_edge (clk) and grid_enable(i) = '1' then
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                                xp(localwidth0*(i+1)-1 downto (i*localwidth0)) <= CONV_STD_LOGIC_VECTOR (sxpos,localwidth0);
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                                zp(localwidth0*(i+1)-1 downto (i*localwidth0)) <= CONV_STD_LOGIC_VECTOR (szpos,localwidth0);
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                                xn(localwidth0*(i+1)-1 downto (i*localwidth0)) <= CONV_STD_LOGIC_VECTOR (sxneg,localwidth0);
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                                zn(localwidth0*(i+1)-1 downto (i*localwidth0)) <= CONV_STD_LOGIC_VECTOR (szneg,localwidth0);
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                                yp(localwidth0*(i+1)-1 downto (i*localwidth0)) <= CONV_STD_LOGIC_VECTOR (sypos,localwidth0);
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                        end if;
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                end process;
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        end generate rowExits;
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        -- Result Intercalation.
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end rtl;
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