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[/] [jart/] [branches/] [ver0branch/] [zu.vhd] - Blame information for rev 80

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1 72 jguarin200
-- Author : Julian Andres Guarin Reyes.
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-- Project : JART, Just Another Ray Tracer.
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- The following code is licensed under GNU Public License
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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 -- This file is part of JART (Just Another Ray Tracer).
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    -- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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    -- it under the terms of the GNU General Public License as published by
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    -- the Free Software Foundation, either version 3 of the License, or
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    -- (at your option) any later version.
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    -- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    -- GNU General Public License for more details.
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    -- You should have received a copy of the GNU General Public License
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    -- along with JART (Just Another Ray Tracer).  If not, see <http://www.gnu.org/licenses/>.library ieee;
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-- Zu synthesises the z and x components of the unitary vectors along an image vertical and/or horizontal line respectively. 
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-- For the jart project Zu must be used with the following values:
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-- When synthesising X , VALSTART must be 34, when synthesising Z, VALSTART must be 9.  
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_signed.all;
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entity zu is
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        generic
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        (
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                VALSTART                : integer := 4;
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                TOP                             : integer := 1024
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        );
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        port (
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                clk, rst, ena   : in std_logic; -- The usual control signals
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                clr                             : in std_logic;
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                zpos                    : out integer range -TOP to TOP-1;
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                zneg                    : out integer range -TOP to TOP-1
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        );
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end entity;
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architecture rtl of zu is
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        signal pivot : std_logic;
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begin
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        process (clk,rst,ena,clr)
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                variable z      : integer range  -TOP to TOP-1;
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        begin
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                if rst='0' then
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                        zpos<=VALSTART;
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                        zneg<=-VALSTART;
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                        z:=VALSTART;
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                        pivot<='0';
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                elsif rising_edge(clk) and ena='1' then
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                        if clr='1' then
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                                z:=VALSTART;
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                                pivot<='0';
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                        elsif pivot = '0' then
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                                z:=z+3;
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                                pivot <= '1';
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                        else
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                                z:=z+2;
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                                pivot <= '0';
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                        end if;
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                        zpos <= z;
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                        zneg <=-z;
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                end if;
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        end process;
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end rtl;
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