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[/] [jart/] [trunk/] [BLRT/] [accum0.vhd] - Blame information for rev 42

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1 42 jguarin200
-- Author : Julian Andres Guarin Reyes.
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-- Project : JART, Just Another Ray Tracer, CopyRight (C) Julian Andres Guarin Reyes, 2009.
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- The following code is licensed under GNU Public License
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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 -- This file is part of JART (Just Another Ray Tracer).
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    -- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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    -- it under the terms of the GNU General Public License as published by
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    -- the Free Software Foundation, either version 3 of the License, or
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    -- (at your option) any later version.
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    -- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    -- GNU General Public License for more details.
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    -- You should have received a copy of the GNU General Public License
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    -- along with JART (Just Another Ray Tracer).  If not, see <http://www.gnu.org/licenses/>.
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-- Selectable operator adder.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity accum0 is
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        generic (WIDTH : integer range 1 to 32);
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        port (
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                clk             : in std_logic;
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                rst     : in std_logic;
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                inAccum : in std_logic_vector (WIDTH-1 downto 0);
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                inSum0  : in std_logic_vector (WIDTH-1 downto 0);
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                inSum1  : in std_logic_vector (WIDTH-1 downto 0);
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                ldAccum : in std_logic;
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                ldSum0  : in std_logic;
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                ldSum1  : in std_logic;
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                enable  : in std_logic;
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                sel             : in std_logic;
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                outAccum        : out std_logic_vector (WIDTH-1 downto 0)
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        );
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end accum0;
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entity rtl of accum0 is
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        signal sAccum : std_logic_vector (WIDTH-1 downto 0);
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        signal sS0 : std_logic_vector (WIDTH-1 downto 0);
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        signal sS1 : std_logic_vector (WIDTH-1 downto 0);
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begin
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        -- Conectar la salida del flip flop afuera
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        outAccum <= sAccum;
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        process (clk, rst)
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        begin
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                if rst='0' then
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                        sAccum  <= (others => '0');
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                        sS0             <= (others => '0');
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                        sS1             <= (others => '0');
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                elsif rising_edge(clk) then
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                        -- Acumulator.
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                        if ldAccum <='1' then
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                                sAccum <= inAccum;
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                        elsif enable <='1' then
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                                sAccum <= sS1 + sAccum;
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                        else
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                                sAccum <= sS0 + sAccum;
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                        end if;
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                        -- Cargar el operador 0
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                        if ldSum0 <= '1' then
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                                sS0 <= inSum0;
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                        end if;
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                        -- Cargar el operador 1
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                        if ldSum1 <= '1' then
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                                sS1 <= inSum1;
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                        end if;
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                end if;
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        end process;
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end rtl;

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