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[/] [jart/] [trunk/] [BLRT/] [floor1Row.vhd] - Blame information for rev 32

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1 30 jguarin200
-- Author : Julian Andres Guarin Reyes.
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-- Project : JART, Just Another Ray Tracer.
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- The following code is licensed under GNU Public License
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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 -- This file is part of JART (Just Another Ray Tracer).
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    -- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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    -- it under the terms of the GNU General Public License as published by
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    -- the Free Software Foundation, either version 3 of the License, or
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    -- (at your option) any later version.
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    -- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    -- GNU General Public License for more details.
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    -- You should have received a copy of the GNU General Public License
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    -- along with JART (Just Another Ray Tracer).  If not, see <http://www.gnu.org/licenses/>.
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-- This file is an instantiation of a k comparison cells row. The number of dot cells used is parameterizable.
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library ieee;
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use ieee.std_logic_1164.all;
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use work.powerGrid.all;
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entity floor1Row is
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        generic (
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                        viw : integer := 32;    -- Vector input Width
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                        col     : integer := 4;         -- Number of Colums
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        );
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        port (
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                        -- Input Control Signals, pipe on is one when raysr going on. 
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                        clk, rst        : in std_logic;
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                        pipeOn          : in std_logic;
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                        -- Clk, Rst, the usual control signals.
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                        nxtSphere       : in std_logic_vector (col-1 downto 0);
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                        -- VD Input / Output.
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                        vdInput : in std_logic_vector (viw*col-1 downto 0);
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                        vdOutput: out std_logic_vector (viw*col-1 downto 0);
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                        -- K Input / Output.
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                        kInput  : in std_logic_vector (viw*col - 1 downto 0); -- The dot product emerging from each dot prod cell. 
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                        kOutput : out std_logic_vector (viw*col - 1 downto 0) -- The dot product emerging from each dot prod cell. 
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        );
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end entity;
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architecture rtl of floor1Row is
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begin
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        theCells : for i in 0 to col-1 generate
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                kComparisonCellx : kComparisonCell port map (
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                        clk                     => clk,
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                        rst                     => rst,
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                        nxtSphere       => nxtSphere,
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                        pipeOn          => pipeOn,
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                        kinput          => kInput       ((i+1)*viw-1 downto i*viw),
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                        koutput         => kOutput      ((i+1)*viw-1 downto i*viw),
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                        vdinput         => vdInput      ((i+1)*viw-1 downto i*viw),
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                        vdoutput        => vdOutput     ((i+1)*viw-1 downto i*viw)
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                        );
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        end generate;
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end rtl;
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