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[/] [jart/] [trunk/] [BLRT/] [scanFF.vhd] - Blame information for rev 35

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1 12 jguarin200
-- Author : Julian Andres Guarin Reyes.
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-- Project : JART, Just Another Ray Tracer.
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- The following code is licensed under GNU Public License
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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 -- This file is part of JART (Just Another Ray Tracer).
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    -- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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    -- it under the terms of the GNU General Public License as published by
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    -- the Free Software Foundation, either version 3 of the License, or
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    -- (at your option) any later version.
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    -- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    -- GNU General Public License for more details.
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    -- You should have received a copy of the GNU General Public License
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    -- along with JART (Just Another Ray Tracer).  If not, see <http://www.gnu.org/licenses/>.
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-- A scan flipflop hdl code. Note the logic function q <= (s0 and s ) or (s1 and ~s) its a mux with s as selector and s0 and s1 as selectable inputs.
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library ieee;
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use ieee.std_logic_1164.all;
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entity scanFF is
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        generic (       W       : integer := 8);
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        port    (
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                                clk,rst,ena,sel         : std_logic; -- The usual  control signals
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                                d0,d1                           : std_logic_vector (W-1 downto 0);       -- The two operands.
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                                q                                       : std_logic_vector (W-1 downto 0)        -- The selected data.
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        );
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end entity;
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architecture rtl of scanFF is
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begin
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        dff_ena_sel : process (clk,rst,ena)
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        begin
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                if rst = '0' then
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                        q <= '0' & (others => '1');
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                elsif rising_edge (clk) and ena = '1' then
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                        if sel='1' then
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                                q <= d1;
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                        else
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                                q <= d0;
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                        end if;
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                end if;
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        end process;
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end rtl;
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        end process;
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end rtl;
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