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1 2 davidklun 
/////////////////////////////////////////////////////////////////////
2 
////                                                             ////
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////  JPEG Encoder Core - Verilog                                ////
4 
////                                                             ////
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////  Author: David Lundgren                                     ////
6 
////          davidklun@gmail.com                                ////
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////                                                             ////
8 
/////////////////////////////////////////////////////////////////////
9 
////                                                             ////
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//// Copyright (C) 2009 David Lundgren                           ////
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////                  davidklun@gmail.com                        ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
33 
 
34 
/* This module is the Huffman encoder.  It takes in the quantized outputs
35 
from the quantizer, and creates the Huffman codes from these value.  The
36 
output from this module is the jpeg code of the actual pixel data.  The jpeg
37 
file headers will need to be generated separately.  The Huffman codes are constant,
38 
and they can be changed by changing the parameters in this module. */
39 
 
40 
`timescale 1ns / 100ps
41 
 
42 
module cr_huff(clk, rst, enable,
43 
Cr11, Cr12, Cr13, Cr14, Cr15, Cr16, Cr17, Cr18, Cr21, Cr22, Cr23, Cr24, Cr25, Cr26, Cr27, Cr28,
44 
Cr31, Cr32, Cr33, Cr34, Cr35, Cr36, Cr37, Cr38, Cr41, Cr42, Cr43, Cr44, Cr45, Cr46, Cr47, Cr48,
45 
Cr51, Cr52, Cr53, Cr54, Cr55, Cr56, Cr57, Cr58, Cr61, Cr62, Cr63, Cr64, Cr65, Cr66, Cr67, Cr68,
46 
Cr71, Cr72, Cr73, Cr74, Cr75, Cr76, Cr77, Cr78, Cr81, Cr82, Cr83, Cr84, Cr85, Cr86, Cr87, Cr88,
47 
JPEG_bitstream, data_ready, output_reg_count, end_of_block_empty);
48 
input           clk;
49 
input           rst;
50 
input           enable;
51 
input  [10:0]  Cr11, Cr12, Cr13, Cr14, Cr15, Cr16, Cr17, Cr18, Cr21, Cr22, Cr23, Cr24;
52 
input  [10:0]  Cr25, Cr26, Cr27, Cr28, Cr31, Cr32, Cr33, Cr34, Cr35, Cr36, Cr37, Cr38;
53 
input  [10:0]  Cr41, Cr42, Cr43, Cr44, Cr45, Cr46, Cr47, Cr48, Cr51, Cr52, Cr53, Cr54;
54 
input  [10:0]  Cr55, Cr56, Cr57, Cr58, Cr61, Cr62, Cr63, Cr64, Cr65, Cr66, Cr67, Cr68;
55 
input  [10:0]  Cr71, Cr72, Cr73, Cr74, Cr75, Cr76, Cr77, Cr78, Cr81, Cr82, Cr83, Cr84;
56 
input  [10:0]  Cr85, Cr86, Cr87, Cr88;
57 
output  [31:0]   JPEG_bitstream;
58 
output  data_ready;
59 
output  output_reg_count;
60 
output  end_of_block_empty;
61 
 
62 
 
63 
reg             [7:0] block_counter;
64 
reg             [11:0]  Cr11_amp, Cr11_1_pos, Cr11_1_neg, Cr11_diff;
65 
reg             [11:0]  Cr11_previous, Cr11_1;
66 
reg             [10:0]  Cr12_amp, Cr12_pos, Cr12_neg;
67 
reg             [10:0]  Cr21_pos, Cr21_neg, Cr31_pos, Cr31_neg, Cr22_pos, Cr22_neg;
68 
reg             [10:0]  Cr13_pos, Cr13_neg, Cr14_pos, Cr14_neg, Cr15_pos, Cr15_neg;
69 
reg             [10:0]  Cr16_pos, Cr16_neg, Cr17_pos, Cr17_neg, Cr18_pos, Cr18_neg;
70 
reg             [10:0]  Cr23_pos, Cr23_neg, Cr24_pos, Cr24_neg, Cr25_pos, Cr25_neg;
71 
reg             [10:0]  Cr26_pos, Cr26_neg, Cr27_pos, Cr27_neg, Cr28_pos, Cr28_neg;
72 
reg             [10:0]  Cr32_pos, Cr32_neg;
73 
reg             [10:0]  Cr33_pos, Cr33_neg, Cr34_pos, Cr34_neg, Cr35_pos, Cr35_neg;
74 
reg             [10:0]  Cr36_pos, Cr36_neg, Cr37_pos, Cr37_neg, Cr38_pos, Cr38_neg;
75 
reg             [10:0]  Cr41_pos, Cr41_neg, Cr42_pos, Cr42_neg;
76 
reg             [10:0]  Cr43_pos, Cr43_neg, Cr44_pos, Cr44_neg, Cr45_pos, Cr45_neg;
77 
reg             [10:0]  Cr46_pos, Cr46_neg, Cr47_pos, Cr47_neg, Cr48_pos, Cr48_neg;
78 
reg             [10:0]  Cr51_pos, Cr51_neg, Cr52_pos, Cr52_neg;
79 
reg             [10:0]  Cr53_pos, Cr53_neg, Cr54_pos, Cr54_neg, Cr55_pos, Cr55_neg;
80 
reg             [10:0]  Cr56_pos, Cr56_neg, Cr57_pos, Cr57_neg, Cr58_pos, Cr58_neg;
81 
reg             [10:0]  Cr61_pos, Cr61_neg, Cr62_pos, Cr62_neg;
82 
reg             [10:0]  Cr63_pos, Cr63_neg, Cr64_pos, Cr64_neg, Cr65_pos, Cr65_neg;
83 
reg             [10:0]  Cr66_pos, Cr66_neg, Cr67_pos, Cr67_neg, Cr68_pos, Cr68_neg;
84 
reg             [10:0]  Cr71_pos, Cr71_neg, Cr72_pos, Cr72_neg;
85 
reg             [10:0]  Cr73_pos, Cr73_neg, Cr74_pos, Cr74_neg, Cr75_pos, Cr75_neg;
86 
reg             [10:0]  Cr76_pos, Cr76_neg, Cr77_pos, Cr77_neg, Cr78_pos, Cr78_neg;
87 
reg             [10:0]  Cr81_pos, Cr81_neg, Cr82_pos, Cr82_neg;
88 
reg             [10:0]  Cr83_pos, Cr83_neg, Cr84_pos, Cr84_neg, Cr85_pos, Cr85_neg;
89 
reg             [10:0]  Cr86_pos, Cr86_neg, Cr87_pos, Cr87_neg, Cr88_pos, Cr88_neg;
90 
reg             [3:0]    Cr11_bits_pos, Cr11_bits_neg, Cr11_bits, Cr11_bits_1;
91 
reg             [3:0]    Cr12_bits_pos, Cr12_bits_neg, Cr12_bits, Cr12_bits_1;
92 
reg             [3:0]    Cr12_bits_2, Cr12_bits_3;
93 
reg             Cr11_msb, Cr12_msb, Cr12_msb_1, data_ready;
94 
reg             enable_1, enable_2, enable_3, enable_4, enable_5, enable_6;
95 
reg             enable_7, enable_8, enable_9, enable_10, enable_11, enable_12;
96 
reg             enable_13, enable_module, enable_latch_7, enable_latch_8;
97 
reg             Cr12_et_zero, rollover, rollover_1, rollover_2, rollover_3;
98 
reg             rollover_4, rollover_5, rollover_6, rollover_7;
99 
reg             Cr21_et_zero, Cr21_msb, Cr31_et_zero, Cr31_msb;
100 
reg             Cr22_et_zero, Cr22_msb, Cr13_et_zero, Cr13_msb;
101 
reg             Cr14_et_zero, Cr14_msb, Cr15_et_zero, Cr15_msb;
102 
reg             Cr16_et_zero, Cr16_msb, Cr17_et_zero, Cr17_msb;
103 
reg             Cr18_et_zero, Cr18_msb;
104 
reg             Cr23_et_zero, Cr23_msb, Cr24_et_zero, Cr24_msb;
105 
reg             Cr25_et_zero, Cr25_msb, Cr26_et_zero, Cr26_msb;
106 
reg             Cr27_et_zero, Cr27_msb, Cr28_et_zero, Cr28_msb;
107 
reg             Cr32_et_zero, Cr32_msb, Cr33_et_zero, Cr33_msb;
108 
reg             Cr34_et_zero, Cr34_msb, Cr35_et_zero, Cr35_msb;
109 
reg             Cr36_et_zero, Cr36_msb, Cr37_et_zero, Cr37_msb;
110 
reg             Cr38_et_zero, Cr38_msb;
111 
reg             Cr41_et_zero, Cr41_msb, Cr42_et_zero, Cr42_msb;
112 
reg             Cr43_et_zero, Cr43_msb, Cr44_et_zero, Cr44_msb;
113 
reg             Cr45_et_zero, Cr45_msb, Cr46_et_zero, Cr46_msb;
114 
reg             Cr47_et_zero, Cr47_msb, Cr48_et_zero, Cr48_msb;
115 
reg             Cr51_et_zero, Cr51_msb, Cr52_et_zero, Cr52_msb;
116 
reg             Cr53_et_zero, Cr53_msb, Cr54_et_zero, Cr54_msb;
117 
reg             Cr55_et_zero, Cr55_msb, Cr56_et_zero, Cr56_msb;
118 
reg             Cr57_et_zero, Cr57_msb, Cr58_et_zero, Cr58_msb;
119 
reg             Cr61_et_zero, Cr61_msb, Cr62_et_zero, Cr62_msb;
120 
reg             Cr63_et_zero, Cr63_msb, Cr64_et_zero, Cr64_msb;
121 
reg             Cr65_et_zero, Cr65_msb, Cr66_et_zero, Cr66_msb;
122 
reg             Cr67_et_zero, Cr67_msb, Cr68_et_zero, Cr68_msb;
123 
reg             Cr71_et_zero, Cr71_msb, Cr72_et_zero, Cr72_msb;
124 
reg             Cr73_et_zero, Cr73_msb, Cr74_et_zero, Cr74_msb;
125 
reg             Cr75_et_zero, Cr75_msb, Cr76_et_zero, Cr76_msb;
126 
reg             Cr77_et_zero, Cr77_msb, Cr78_et_zero, Cr78_msb;
127 
reg             Cr81_et_zero, Cr81_msb, Cr82_et_zero, Cr82_msb;
128 
reg             Cr83_et_zero, Cr83_msb, Cr84_et_zero, Cr84_msb;
129 
reg             Cr85_et_zero, Cr85_msb, Cr86_et_zero, Cr86_msb;
130 
reg             Cr87_et_zero, Cr87_msb, Cr88_et_zero, Cr88_msb;
131 
reg     Cr12_et_zero_1, Cr12_et_zero_2, Cr12_et_zero_3, Cr12_et_zero_4, Cr12_et_zero_5;
132 
reg             [10:0] Cr_DC [11:0];
133 
reg     [3:0] Cr_DC_code_length [11:0];
134 
reg             [15:0] Cr_AC [161:0];
135 
reg     [4:0] Cr_AC_code_length [161:0];
136 
reg     [7:0] Cr_AC_run_code [250:0];
137 
reg             [10:0] Cr11_Huff, Cr11_Huff_1, Cr11_Huff_2;
138 
reg             [15:0] Cr12_Huff, Cr12_Huff_1, Cr12_Huff_2;
139 
reg             [3:0] Cr11_Huff_count, Cr11_Huff_shift, Cr11_Huff_shift_1, Cr11_amp_shift, Cr12_amp_shift;
140 
reg             [3:0] Cr12_Huff_shift, Cr12_Huff_shift_1, zero_run_length, zrl_1, zrl_2, zrl_3;
141 
reg             [4:0] Cr12_Huff_count, Cr12_Huff_count_1;
142 
reg             [4:0] output_reg_count, Cr11_output_count, old_orc_1, old_orc_2;
143 
reg             [4:0] old_orc_3, old_orc_4, old_orc_5, old_orc_6, Cr12_oc_1;
144 
reg             [4:0] orc_3, orc_4, orc_5, orc_6, orc_7, orc_8;
145 
reg             [4:0] Cr12_output_count;
146 
reg     [4:0] Cr12_edge, Cr12_edge_1, Cr12_edge_2, Cr12_edge_3, Cr12_edge_4;
147 
reg             [31:0]   JPEG_bitstream, JPEG_bs, JPEG_bs_1, JPEG_bs_2, JPEG_bs_3, JPEG_bs_4, JPEG_bs_5;
148 
reg             [31:0]   JPEG_Cr12_bs, JPEG_Cr12_bs_1, JPEG_Cr12_bs_2, JPEG_Cr12_bs_3, JPEG_Cr12_bs_4;
149 
reg             [31:0]   JPEG_ro_bs, JPEG_ro_bs_1, JPEG_ro_bs_2, JPEG_ro_bs_3, JPEG_ro_bs_4;
150 
reg             [21:0]   Cr11_JPEG_LSBs_3;
151 
reg             [10:0]   Cr11_JPEG_LSBs, Cr11_JPEG_LSBs_1, Cr11_JPEG_LSBs_2;
152 
reg             [9:0]    Cr12_JPEG_LSBs, Cr12_JPEG_LSBs_1, Cr12_JPEG_LSBs_2, Cr12_JPEG_LSBs_3;
153 
reg             [25:0]   Cr11_JPEG_bits, Cr11_JPEG_bits_1, Cr12_JPEG_bits, Cr12_JPEG_LSBs_4;
154 
reg             [7:0]    Cr12_code_entry;
155 
reg             third_8_all_0s, fourth_8_all_0s, fifth_8_all_0s, sixth_8_all_0s, seventh_8_all_0s;
156 
reg             eighth_8_all_0s, end_of_block, code_15_0, zrl_et_15, end_of_block_output;
157 
reg             end_of_block_empty;
158 
 
159 
wire    [7:0]    code_index = { zrl_2, Cr12_bits };
160 
 
161 
 
162 
 
163 
always @(posedge clk)
164 
begin
165 
        if (rst) begin
166 
                third_8_all_0s <= 0; fourth_8_all_0s <= 0;
167 
                fifth_8_all_0s <= 0; sixth_8_all_0s <= 0; seventh_8_all_0s <= 0;
168 
                eighth_8_all_0s <= 0;
169 
                end
170 
        else if (enable_1) begin
171 
                third_8_all_0s <= Cr25_et_zero & Cr34_et_zero & Cr43_et_zero & Cr52_et_zero
172 
                                          & Cr61_et_zero & Cr71_et_zero & Cr62_et_zero & Cr53_et_zero;
173 
                fourth_8_all_0s <= Cr44_et_zero & Cr35_et_zero & Cr26_et_zero & Cr17_et_zero
174 
                                          & Cr18_et_zero & Cr27_et_zero & Cr36_et_zero & Cr45_et_zero;
175 
                fifth_8_all_0s <= Cr54_et_zero & Cr63_et_zero & Cr72_et_zero & Cr81_et_zero
176 
                                          & Cr82_et_zero & Cr73_et_zero & Cr64_et_zero & Cr55_et_zero;
177 
                sixth_8_all_0s <= Cr46_et_zero & Cr37_et_zero & Cr28_et_zero & Cr38_et_zero
178 
                                          & Cr47_et_zero & Cr56_et_zero & Cr65_et_zero & Cr74_et_zero;
179 
                seventh_8_all_0s <= Cr83_et_zero & Cr84_et_zero & Cr75_et_zero & Cr66_et_zero
180 
                                          & Cr57_et_zero & Cr48_et_zero & Cr58_et_zero & Cr67_et_zero;
181 
                eighth_8_all_0s <= Cr76_et_zero & Cr85_et_zero & Cr86_et_zero & Cr77_et_zero
182 
                                          & Cr68_et_zero & Cr78_et_zero & Cr87_et_zero & Cr88_et_zero;
183 
                end
184 
end
185 
 
186 
 
187 
/* end_of_block checks to see if there are any nonzero elements left in the block
188 
If there aren't any nonzero elements left, then the last bits in the JPEG stream
189 
will be the end of block code.  The purpose of this register is to determine if the
190 
zero run length code 15-0 should be used or not.  It should be used if there are 15 or more
191 
zeros in a row, followed by a nonzero value.  If there are only zeros left in the block,
192 
then end_of_block will be 1.  If there are any nonzero values left in the block, end_of_block
193 
will be 0. */
194 
 
195 
always @(posedge clk)
196 
begin
197 
        if (rst)
198 
                end_of_block <= 0;
199 
        else if (enable)
200 
                end_of_block <= 0;
201 
        else if (enable_module & block_counter < 32)
202 
                end_of_block <= third_8_all_0s & fourth_8_all_0s & fifth_8_all_0s
203 
                                        & sixth_8_all_0s & seventh_8_all_0s & eighth_8_all_0s;
204 
        else if (enable_module & block_counter < 48)
205 
                end_of_block <= fifth_8_all_0s & sixth_8_all_0s & seventh_8_all_0s
206 
                                        & eighth_8_all_0s;
207 
        else if (enable_module & block_counter <= 64)
208 
                end_of_block <= seventh_8_all_0s & eighth_8_all_0s;
209 
        else if (enable_module & block_counter > 64)
210 
                end_of_block <= 1;
211 
end
212 
 
213 
always @(posedge clk)
214 
begin
215 
        if (rst) begin
216 
                block_counter <= 0;
217 
                end
218 
        else if (enable) begin
219 
                block_counter <= 0;
220 
                end
221 
        else if (enable_module) begin
222 
                block_counter <= block_counter + 1;
223 
                end
224 
end
225 
 
226 
always @(posedge clk)
227 
begin
228 
        if (rst) begin
229 
                output_reg_count <= 0;
230 
                end
231 
        else if (end_of_block_output) begin
232 
                output_reg_count <= 0;
233 
                end
234 
        else if (enable_6) begin
235 
                output_reg_count <= output_reg_count + Cr11_output_count;
236 
                end
237 
        else if (enable_latch_7) begin
238 
                output_reg_count <= output_reg_count + Cr12_oc_1;
239 
                end
240 
end
241 
 
242 
always @(posedge clk)
243 
begin
244 
        if (rst) begin
245 
                old_orc_1 <= 0;
246 
                end
247 
        else if (end_of_block_output) begin
248 
                old_orc_1 <= 0;
249 
                end
250 
        else if (enable_module) begin
251 
                old_orc_1 <= output_reg_count;
252 
                end
253 
end
254 
 
255 
always @(posedge clk)
256 
begin
257 
        if (rst) begin
258 
                rollover <= 0; rollover_1 <= 0; rollover_2 <= 0;
259 
                rollover_3 <= 0; rollover_4 <= 0; rollover_5 <= 0;
260 
                rollover_6 <= 0; rollover_7 <= 0;
261 
                old_orc_2 <= 0;
262 
                orc_3 <= 0; orc_4 <= 0; orc_5 <= 0; orc_6 <= 0;
263 
                orc_7 <= 0; orc_8 <= 0; data_ready <= 0;
264 
                end_of_block_output <= 0; end_of_block_empty <= 0;
265 
                end
266 
        else if (enable_module) begin
267 
                rollover <= (old_orc_1 > output_reg_count);
268 
                rollover_1 <= rollover;
269 
                rollover_2 <= rollover_1;
270 
                rollover_3 <= rollover_2;
271 
                rollover_4 <= rollover_3;
272 
                rollover_5 <= rollover_4;
273 
                rollover_6 <= rollover_5;
274 
                rollover_7 <= rollover_6;
275 
                old_orc_2 <= old_orc_1;
276 
                orc_3 <= old_orc_2;
277 
                orc_4 <= orc_3; orc_5 <= orc_4;
278 
                orc_6 <= orc_5; orc_7 <= orc_6;
279 
                orc_8 <= orc_7;
280 
                data_ready <= rollover_6 | block_counter == 77;
281 
                end_of_block_output <= block_counter == 77;
282 
                end_of_block_empty <= rollover_7 & block_counter == 77 & output_reg_count == 0;
283 
                end
284 
end
285 
 
286 
 
287 
 
288 
always @(posedge clk)
289 
begin
290 
        if (rst) begin
291 
                JPEG_bs_5 <= 0;
292 
                end
293 
        else if (enable_module) begin
294 
                JPEG_bs_5[31] <= (rollover_6 & orc_7 > 0) ? JPEG_ro_bs_4[31] : JPEG_bs_4[31];
295 
                JPEG_bs_5[30] <= (rollover_6 & orc_7 > 1) ? JPEG_ro_bs_4[30] : JPEG_bs_4[30];
296 
                JPEG_bs_5[29] <= (rollover_6 & orc_7 > 2) ? JPEG_ro_bs_4[29] : JPEG_bs_4[29];
297 
                JPEG_bs_5[28] <= (rollover_6 & orc_7 > 3) ? JPEG_ro_bs_4[28] : JPEG_bs_4[28];
298 
                JPEG_bs_5[27] <= (rollover_6 & orc_7 > 4) ? JPEG_ro_bs_4[27] : JPEG_bs_4[27];
299 
                JPEG_bs_5[26] <= (rollover_6 & orc_7 > 5) ? JPEG_ro_bs_4[26] : JPEG_bs_4[26];
300 
                JPEG_bs_5[25] <= (rollover_6 & orc_7 > 6) ? JPEG_ro_bs_4[25] : JPEG_bs_4[25];
301 
                JPEG_bs_5[24] <= (rollover_6 & orc_7 > 7) ? JPEG_ro_bs_4[24] : JPEG_bs_4[24];
302 
                JPEG_bs_5[23] <= (rollover_6 & orc_7 > 8) ? JPEG_ro_bs_4[23] : JPEG_bs_4[23];
303 
                JPEG_bs_5[22] <= (rollover_6 & orc_7 > 9) ? JPEG_ro_bs_4[22] : JPEG_bs_4[22];
304 
                JPEG_bs_5[21] <= (rollover_6 & orc_7 > 10) ? JPEG_ro_bs_4[21] : JPEG_bs_4[21];
305 
                JPEG_bs_5[20] <= (rollover_6 & orc_7 > 11) ? JPEG_ro_bs_4[20] : JPEG_bs_4[20];
306 
                JPEG_bs_5[19] <= (rollover_6 & orc_7 > 12) ? JPEG_ro_bs_4[19] : JPEG_bs_4[19];
307 
                JPEG_bs_5[18] <= (rollover_6 & orc_7 > 13) ? JPEG_ro_bs_4[18] : JPEG_bs_4[18];
308 
                JPEG_bs_5[17] <= (rollover_6 & orc_7 > 14) ? JPEG_ro_bs_4[17] : JPEG_bs_4[17];
309 
                JPEG_bs_5[16] <= (rollover_6 & orc_7 > 15) ? JPEG_ro_bs_4[16] : JPEG_bs_4[16];
310 
                JPEG_bs_5[15] <= (rollover_6 & orc_7 > 16) ? JPEG_ro_bs_4[15] : JPEG_bs_4[15];
311 
                JPEG_bs_5[14] <= (rollover_6 & orc_7 > 17) ? JPEG_ro_bs_4[14] : JPEG_bs_4[14];
312 
                JPEG_bs_5[13] <= (rollover_6 & orc_7 > 18) ? JPEG_ro_bs_4[13] : JPEG_bs_4[13];
313 
                JPEG_bs_5[12] <= (rollover_6 & orc_7 > 19) ? JPEG_ro_bs_4[12] : JPEG_bs_4[12];
314 
                JPEG_bs_5[11] <= (rollover_6 & orc_7 > 20) ? JPEG_ro_bs_4[11] : JPEG_bs_4[11];
315 
                JPEG_bs_5[10] <= (rollover_6 & orc_7 > 21) ? JPEG_ro_bs_4[10] : JPEG_bs_4[10];
316 
                JPEG_bs_5[9] <= (rollover_6 & orc_7 > 22) ? JPEG_ro_bs_4[9] : JPEG_bs_4[9];
317 
                JPEG_bs_5[8] <= (rollover_6 & orc_7 > 23) ? JPEG_ro_bs_4[8] : JPEG_bs_4[8];
318 
                JPEG_bs_5[7] <= (rollover_6 & orc_7 > 24) ? JPEG_ro_bs_4[7] : JPEG_bs_4[7];
319 
                JPEG_bs_5[6] <= (rollover_6 & orc_7 > 25) ? JPEG_ro_bs_4[6] : JPEG_bs_4[6];
320 
                JPEG_bs_5[5] <= (rollover_6 & orc_7 > 26) ? JPEG_ro_bs_4[5] : JPEG_bs_4[5];
321 
                JPEG_bs_5[4] <= (rollover_6 & orc_7 > 27) ? JPEG_ro_bs_4[4] : JPEG_bs_4[4];
322 
                JPEG_bs_5[3] <= (rollover_6 & orc_7 > 28) ? JPEG_ro_bs_4[3] : JPEG_bs_4[3];
323 
                JPEG_bs_5[2] <= (rollover_6 & orc_7 > 29) ? JPEG_ro_bs_4[2] : JPEG_bs_4[2];
324 
                JPEG_bs_5[1] <= (rollover_6 & orc_7 > 30) ? JPEG_ro_bs_4[1] : JPEG_bs_4[1];
325 
                JPEG_bs_5[0] <= JPEG_bs_4[0];
326 
                end
327 
end
328 
 
329 
always @(posedge clk)
330 
begin
331 
        if (rst) begin
332 
                JPEG_bs_4 <= 0; JPEG_ro_bs_4 <= 0;
333 
                end
334 
        else if (enable_module) begin
335 
                JPEG_bs_4 <= (old_orc_6 == 1) ? JPEG_bs_3 >> 1 : JPEG_bs_3;
336 
                JPEG_ro_bs_4 <= (Cr12_edge_4 <= 1) ? JPEG_ro_bs_3 << 1 : JPEG_ro_bs_3;
337 
                end
338 
end
339 
 
340 
always @(posedge clk)
341 
begin
342 
        if (rst) begin
343 
                JPEG_bs_3 <= 0; old_orc_6 <= 0; JPEG_ro_bs_3 <= 0;
344 
                Cr12_edge_4 <= 0;
345 
                end
346 
        else if (enable_module) begin
347 
                JPEG_bs_3 <= (old_orc_5 >= 2) ? JPEG_bs_2 >> 2 : JPEG_bs_2;
348 
                old_orc_6 <= (old_orc_5 >= 2) ? old_orc_5 - 2 : old_orc_5;
349 
                JPEG_ro_bs_3 <= (Cr12_edge_3 <= 2) ? JPEG_ro_bs_2 << 2 : JPEG_ro_bs_2;
350 
                Cr12_edge_4 <= (Cr12_edge_3 <= 2) ? Cr12_edge_3 : Cr12_edge_3 - 2;
351 
                end
352 
end
353 
 
354 
always @(posedge clk)
355 
begin
356 
        if (rst) begin
357 
                JPEG_bs_2 <= 0; old_orc_5 <= 0; JPEG_ro_bs_2 <= 0;
358 
                Cr12_edge_3 <= 0;
359 
                end
360 
        else if (enable_module) begin
361 
                JPEG_bs_2 <= (old_orc_4 >= 4) ? JPEG_bs_1 >> 4 : JPEG_bs_1;
362 
                old_orc_5 <= (old_orc_4 >= 4) ? old_orc_4 - 4 : old_orc_4;
363 
                JPEG_ro_bs_2 <= (Cr12_edge_2 <= 4) ? JPEG_ro_bs_1 << 4 : JPEG_ro_bs_1;
364 
                Cr12_edge_3 <= (Cr12_edge_2 <= 4) ? Cr12_edge_2 : Cr12_edge_2 - 4;
365 
                end
366 
end
367 
 
368 
always @(posedge clk)
369 
begin
370 
        if (rst) begin
371 
                JPEG_bs_1 <= 0; old_orc_4 <= 0; JPEG_ro_bs_1 <= 0;
372 
                Cr12_edge_2 <= 0;
373 
                end
374 
        else if (enable_module) begin
375 
                JPEG_bs_1 <= (old_orc_3 >= 8) ? JPEG_bs >> 8 : JPEG_bs;
376 
                old_orc_4 <= (old_orc_3 >= 8) ? old_orc_3 - 8 : old_orc_3;
377 
                JPEG_ro_bs_1 <= (Cr12_edge_1 <= 8) ? JPEG_ro_bs << 8 : JPEG_ro_bs;
378 
                Cr12_edge_2 <= (Cr12_edge_1 <= 8) ? Cr12_edge_1 : Cr12_edge_1 - 8;
379 
                end
380 
end
381 
 
382 
always @(posedge clk)
383 
begin
384 
        if (rst) begin
385 
                JPEG_bs <= 0; old_orc_3 <= 0; JPEG_ro_bs <= 0;
386 
                Cr12_edge_1 <= 0; Cr11_JPEG_bits_1 <= 0;
387 
                end
388 
        else if (enable_module) begin
389 
                JPEG_bs <= (old_orc_2 >= 16) ? Cr11_JPEG_bits >> 10 : Cr11_JPEG_bits << 6;
390 
                old_orc_3 <= (old_orc_2 >= 16) ? old_orc_2 - 16 : old_orc_2;
391 
                JPEG_ro_bs <= (Cr12_edge <= 16) ? Cr11_JPEG_bits_1 << 16 : Cr11_JPEG_bits_1;
392 
                Cr12_edge_1 <= (Cr12_edge <= 16) ? Cr12_edge : Cr12_edge - 16;
393 
                Cr11_JPEG_bits_1 <= Cr11_JPEG_bits;
394 
                end
395 
end
396 
 
397 
always @(posedge clk)
398 
begin
399 
        if (rst) begin
400 
                Cr12_JPEG_bits <= 0; Cr12_edge <= 0;
401 
                end
402 
        else if (enable_module) begin
403 
                Cr12_JPEG_bits[25] <= (Cr12_Huff_shift_1 >= 16) ? Cr12_JPEG_LSBs_4[25] : Cr12_Huff_2[15];
404 
                Cr12_JPEG_bits[24] <= (Cr12_Huff_shift_1 >= 15) ? Cr12_JPEG_LSBs_4[24] : Cr12_Huff_2[14];
405 
                Cr12_JPEG_bits[23] <= (Cr12_Huff_shift_1 >= 14) ? Cr12_JPEG_LSBs_4[23] : Cr12_Huff_2[13];
406 
                Cr12_JPEG_bits[22] <= (Cr12_Huff_shift_1 >= 13) ? Cr12_JPEG_LSBs_4[22] : Cr12_Huff_2[12];
407 
                Cr12_JPEG_bits[21] <= (Cr12_Huff_shift_1 >= 12) ? Cr12_JPEG_LSBs_4[21] : Cr12_Huff_2[11];
408 
                Cr12_JPEG_bits[20] <= (Cr12_Huff_shift_1 >= 11) ? Cr12_JPEG_LSBs_4[20] : Cr12_Huff_2[10];
409 
                Cr12_JPEG_bits[19] <= (Cr12_Huff_shift_1 >= 10) ? Cr12_JPEG_LSBs_4[19] : Cr12_Huff_2[9];
410 
                Cr12_JPEG_bits[18] <= (Cr12_Huff_shift_1 >= 9) ? Cr12_JPEG_LSBs_4[18] : Cr12_Huff_2[8];
411 
                Cr12_JPEG_bits[17] <= (Cr12_Huff_shift_1 >= 8) ? Cr12_JPEG_LSBs_4[17] : Cr12_Huff_2[7];
412 
                Cr12_JPEG_bits[16] <= (Cr12_Huff_shift_1 >= 7) ? Cr12_JPEG_LSBs_4[16] : Cr12_Huff_2[6];
413 
                Cr12_JPEG_bits[15] <= (Cr12_Huff_shift_1 >= 6) ? Cr12_JPEG_LSBs_4[15] : Cr12_Huff_2[5];
414 
                Cr12_JPEG_bits[14] <= (Cr12_Huff_shift_1 >= 5) ? Cr12_JPEG_LSBs_4[14] : Cr12_Huff_2[4];
415 
                Cr12_JPEG_bits[13] <= (Cr12_Huff_shift_1 >= 4) ? Cr12_JPEG_LSBs_4[13] : Cr12_Huff_2[3];
416 
                Cr12_JPEG_bits[12] <= (Cr12_Huff_shift_1 >= 3) ? Cr12_JPEG_LSBs_4[12] : Cr12_Huff_2[2];
417 
                Cr12_JPEG_bits[11] <= (Cr12_Huff_shift_1 >= 2) ? Cr12_JPEG_LSBs_4[11] : Cr12_Huff_2[1];
418 
                Cr12_JPEG_bits[10] <= (Cr12_Huff_shift_1 >= 1) ? Cr12_JPEG_LSBs_4[10] : Cr12_Huff_2[0];
419 
                Cr12_JPEG_bits[9:0] <= Cr12_JPEG_LSBs_4[9:0];
420 
                Cr12_edge <= old_orc_2 + 26; // 26 is the size of Cr11_JPEG_bits
421 
                end
422 
end
423 
 
424 
always @(posedge clk)
425 
begin
426 
        if (rst) begin
427 
                Cr11_JPEG_bits <= 0;
428 
                end
429 
        else if (enable_7) begin
430 
                Cr11_JPEG_bits[25] <= (Cr11_Huff_shift_1 >= 11) ? Cr11_JPEG_LSBs_3[21] : Cr11_Huff_2[10];
431 
                Cr11_JPEG_bits[24] <= (Cr11_Huff_shift_1 >= 10) ? Cr11_JPEG_LSBs_3[20] : Cr11_Huff_2[9];
432 
                Cr11_JPEG_bits[23] <= (Cr11_Huff_shift_1 >= 9) ? Cr11_JPEG_LSBs_3[19] : Cr11_Huff_2[8];
433 
                Cr11_JPEG_bits[22] <= (Cr11_Huff_shift_1 >= 8) ? Cr11_JPEG_LSBs_3[18] : Cr11_Huff_2[7];
434 
                Cr11_JPEG_bits[21] <= (Cr11_Huff_shift_1 >= 7) ? Cr11_JPEG_LSBs_3[17] : Cr11_Huff_2[6];
435 
                Cr11_JPEG_bits[20] <= (Cr11_Huff_shift_1 >= 6) ? Cr11_JPEG_LSBs_3[16] : Cr11_Huff_2[5];
436 
                Cr11_JPEG_bits[19] <= (Cr11_Huff_shift_1 >= 5) ? Cr11_JPEG_LSBs_3[15] : Cr11_Huff_2[4];
437 
                Cr11_JPEG_bits[18] <= (Cr11_Huff_shift_1 >= 4) ? Cr11_JPEG_LSBs_3[14] : Cr11_Huff_2[3];
438 
                Cr11_JPEG_bits[17] <= (Cr11_Huff_shift_1 >= 3) ? Cr11_JPEG_LSBs_3[13] : Cr11_Huff_2[2];
439 
                Cr11_JPEG_bits[16] <= (Cr11_Huff_shift_1 >= 2) ? Cr11_JPEG_LSBs_3[12] : Cr11_Huff_2[1];
440 
                Cr11_JPEG_bits[15] <= (Cr11_Huff_shift_1 >= 1) ? Cr11_JPEG_LSBs_3[11] : Cr11_Huff_2[0];
441 
                Cr11_JPEG_bits[14:4] <= Cr11_JPEG_LSBs_3[10:0];
442 
                end
443 
        else if (enable_latch_8) begin
444 
                Cr11_JPEG_bits <= Cr12_JPEG_bits;
445 
                end
446 
end
447 
 
448 
 
449 
always @(posedge clk)
450 
begin
451 
        if (rst) begin
452 
                Cr12_oc_1 <= 0; Cr12_JPEG_LSBs_4 <= 0;
453 
                Cr12_Huff_2 <= 0; Cr12_Huff_shift_1 <= 0;
454 
                end
455 
        else if (enable_module) begin
456 
                Cr12_oc_1 <= (Cr12_et_zero_5 & !code_15_0 & block_counter != 67) ? 0 :
457 
                        Cr12_bits_3 + Cr12_Huff_count_1;
458 
                Cr12_JPEG_LSBs_4 <= Cr12_JPEG_LSBs_3 << Cr12_Huff_shift;
459 
                Cr12_Huff_2 <= Cr12_Huff_1;
460 
                Cr12_Huff_shift_1 <= Cr12_Huff_shift;
461 
                end
462 
end
463 
 
464 
always @(posedge clk)
465 
begin
466 
        if (rst) begin
467 
                Cr11_JPEG_LSBs_3 <= 0; Cr11_Huff_2 <= 0;
468 
                Cr11_Huff_shift_1 <= 0;
469 
                end
470 
        else if (enable_6) begin
471 
                Cr11_JPEG_LSBs_3 <= Cr11_JPEG_LSBs_2 << Cr11_Huff_shift;
472 
                Cr11_Huff_2 <= Cr11_Huff_1;
473 
                Cr11_Huff_shift_1 <= Cr11_Huff_shift;
474 
                end
475 
end
476 
 
477 
 
478 
always @(posedge clk)
479 
begin
480 
        if (rst) begin
481 
                Cr12_Huff_shift <= 0;
482 
                Cr12_Huff_1 <= 0; Cr12_JPEG_LSBs_3 <= 0; Cr12_bits_3 <= 0;
483 
                Cr12_Huff_count_1 <= 0; Cr12_et_zero_5 <= 0; code_15_0 <= 0;
484 
                end
485 
        else if (enable_module) begin
486 
                Cr12_Huff_shift <= 16 - Cr12_Huff_count;
487 
                Cr12_Huff_1 <= Cr12_Huff;
488 
                Cr12_JPEG_LSBs_3 <= Cr12_JPEG_LSBs_2;
489 
                Cr12_bits_3 <= Cr12_bits_2;
490 
                Cr12_Huff_count_1 <= Cr12_Huff_count;
491 
                Cr12_et_zero_5 <= Cr12_et_zero_4;
492 
                code_15_0 <= zrl_et_15 & !end_of_block;
493 
                end
494 
end
495 
 
496 
always @(posedge clk)
497 
begin
498 
        if (rst) begin
499 
                Cr11_output_count <= 0; Cr11_JPEG_LSBs_2 <= 0; Cr11_Huff_shift <= 0;
500 
                Cr11_Huff_1 <= 0;
501 
                end
502 
        else if (enable_5) begin
503 
                Cr11_output_count <= Cr11_bits_1 + Cr11_Huff_count;
504 
                Cr11_JPEG_LSBs_2 <= Cr11_JPEG_LSBs_1 << Cr11_amp_shift;
505 
                Cr11_Huff_shift <= 11 - Cr11_Huff_count;
506 
                Cr11_Huff_1 <= Cr11_Huff;
507 
                end
508 
end
509 
 
510 
 
511 
always @(posedge clk)
512 
begin
513 
        if (rst) begin
514 
                Cr12_JPEG_LSBs_2 <= 0;
515 
                Cr12_Huff <= 0; Cr12_Huff_count <= 0; Cr12_bits_2 <= 0;
516 
                Cr12_et_zero_4 <= 0; zrl_et_15 <= 0; zrl_3 <= 0;
517 
                end
518 
        else if (enable_module) begin
519 
                Cr12_JPEG_LSBs_2 <= Cr12_JPEG_LSBs_1 << Cr12_amp_shift;
520 
                Cr12_Huff <= Cr_AC[Cr12_code_entry];
521 
                Cr12_Huff_count <= Cr_AC_code_length[Cr12_code_entry];
522 
                Cr12_bits_2 <= Cr12_bits_1;
523 
                Cr12_et_zero_4 <= Cr12_et_zero_3;
524 
                zrl_et_15 <= zrl_3 == 15;
525 
                zrl_3 <= zrl_2;
526 
                end
527 
end
528 
 
529 
always @(posedge clk)
530 
begin
531 
        if (rst) begin
532 
                Cr11_Huff <= 0; Cr11_Huff_count <= 0; Cr11_amp_shift <= 0;
533 
                Cr11_JPEG_LSBs_1 <= 0; Cr11_bits_1 <= 0;
534 
                end
535 
        else if (enable_4) begin
536 
                Cr11_Huff[10:0] <= Cr_DC[Cr11_bits];
537 
                Cr11_Huff_count <= Cr_DC_code_length[Cr11_bits];
538 
                Cr11_amp_shift <= 11 - Cr11_bits;
539 
                Cr11_JPEG_LSBs_1 <= Cr11_JPEG_LSBs;
540 
                Cr11_bits_1 <= Cr11_bits;
541 
                end
542 
end
543 
 
544 
always @(posedge clk)
545 
begin
546 
        if (rst) begin
547 
                Cr12_code_entry <= 0; Cr12_JPEG_LSBs_1 <= 0; Cr12_amp_shift <= 0;
548 
                Cr12_bits_1 <= 0; Cr12_et_zero_3 <= 0; zrl_2 <= 0;
549 
                end
550 
        else if (enable_module) begin
551 
                Cr12_code_entry <= Cr_AC_run_code[code_index];
552 
                Cr12_JPEG_LSBs_1 <= Cr12_JPEG_LSBs;
553 
                Cr12_amp_shift <= 10 - Cr12_bits;
554 
                Cr12_bits_1 <= Cr12_bits;
555 
                Cr12_et_zero_3 <= Cr12_et_zero_2;
556 
                zrl_2 <= zrl_1;
557 
                end
558 
end
559 
 
560 
always @(posedge clk)
561 
begin
562 
        if (rst) begin
563 
                Cr11_bits <= 0; Cr11_JPEG_LSBs <= 0;
564 
                end
565 
        else if (enable_3) begin
566 
                Cr11_bits <= Cr11_msb ? Cr11_bits_neg : Cr11_bits_pos;
567 
                Cr11_JPEG_LSBs <= Cr11_amp[10:0]; // The top bit of Cr11_amp is the sign bit
568 
                end
569 
end
570 
 
571 
always @(posedge clk)
572 
begin
573 
        if (rst) begin
574 
                Cr12_bits <= 0; Cr12_JPEG_LSBs <= 0; zrl_1 <= 0;
575 
                Cr12_et_zero_2 <= 0;
576 
                end
577 
        else if (enable_module) begin
578 
                Cr12_bits <= Cr12_msb_1 ? Cr12_bits_neg : Cr12_bits_pos;
579 
                Cr12_JPEG_LSBs <= Cr12_amp[9:0]; // The top bit of Cr12_amp is the sign bit
580 
                zrl_1 <= block_counter == 62 & Cr12_et_zero ? 0 : zero_run_length;
581 
                Cr12_et_zero_2 <= Cr12_et_zero_1;
582 
                end
583 
end
584 
 
585 
// Cr11_amp is the amplitude that will be represented in bits in the
586 
// JPEG code, following the run length code
587 
always @(posedge clk)
588 
begin
589 
        if (rst) begin
590 
                Cr11_amp <= 0;
591 
                end
592 
        else if (enable_2) begin
593 
                Cr11_amp <= Cr11_msb ? Cr11_1_neg : Cr11_1_pos;
594 
                end
595 
end
596 
 
597 
 
598 
always @(posedge clk)
599 
begin
600 
        if (rst)
601 
                zero_run_length <= 0;
602 
        else if (enable)
603 
                zero_run_length <= 0;
604 
        else if (enable_module)
605 
                zero_run_length <= Cr12_et_zero ? zero_run_length + 1: 0;
606 
end
607 
 
608 
always @(posedge clk)
609 
begin
610 
        if (rst) begin
611 
                Cr12_amp <= 0;
612 
                Cr12_et_zero_1 <= 0; Cr12_msb_1 <= 0;
613 
                end
614 
        else if (enable_module) begin
615 
                Cr12_amp <= Cr12_msb ? Cr12_neg : Cr12_pos;
616 
                Cr12_et_zero_1 <= Cr12_et_zero;
617 
                Cr12_msb_1 <= Cr12_msb;
618 
                end
619 
end
620 
 
621 
always @(posedge clk)
622 
begin
623 
        if (rst) begin
624 
                Cr11_1_pos <= 0; Cr11_1_neg <= 0; Cr11_msb <= 0;
625 
                Cr11_previous <= 0;
626 
                end
627 
        else if (enable_1) begin
628 
                Cr11_1_pos <= Cr11_diff;
629 
                Cr11_1_neg <= Cr11_diff - 1;
630 
                Cr11_msb <= Cr11_diff[11];
631 
                Cr11_previous <= Cr11_1;
632 
                end
633 
end
634 
 
635 
always @(posedge clk)
636 
begin
637 
        if (rst) begin
638 
                Cr12_pos <= 0; Cr12_neg <= 0; Cr12_msb <= 0; Cr12_et_zero <= 0;
639 
                Cr13_pos <= 0; Cr13_neg <= 0; Cr13_msb <= 0; Cr13_et_zero <= 0;
640 
                Cr14_pos <= 0; Cr14_neg <= 0; Cr14_msb <= 0; Cr14_et_zero <= 0;
641 
                Cr15_pos <= 0; Cr15_neg <= 0; Cr15_msb <= 0; Cr15_et_zero <= 0;
642 
                Cr16_pos <= 0; Cr16_neg <= 0; Cr16_msb <= 0; Cr16_et_zero <= 0;
643 
                Cr17_pos <= 0; Cr17_neg <= 0; Cr17_msb <= 0; Cr17_et_zero <= 0;
644 
                Cr18_pos <= 0; Cr18_neg <= 0; Cr18_msb <= 0; Cr18_et_zero <= 0;
645 
                Cr21_pos <= 0; Cr21_neg <= 0; Cr21_msb <= 0; Cr21_et_zero <= 0;
646 
                Cr22_pos <= 0; Cr22_neg <= 0; Cr22_msb <= 0; Cr22_et_zero <= 0;
647 
                Cr23_pos <= 0; Cr23_neg <= 0; Cr23_msb <= 0; Cr23_et_zero <= 0;
648 
                Cr24_pos <= 0; Cr24_neg <= 0; Cr24_msb <= 0; Cr24_et_zero <= 0;
649 
                Cr25_pos <= 0; Cr25_neg <= 0; Cr25_msb <= 0; Cr25_et_zero <= 0;
650 
                Cr26_pos <= 0; Cr26_neg <= 0; Cr26_msb <= 0; Cr26_et_zero <= 0;
651 
                Cr27_pos <= 0; Cr27_neg <= 0; Cr27_msb <= 0; Cr27_et_zero <= 0;
652 
                Cr28_pos <= 0; Cr28_neg <= 0; Cr28_msb <= 0; Cr28_et_zero <= 0;
653 
                Cr31_pos <= 0; Cr31_neg <= 0; Cr31_msb <= 0; Cr31_et_zero <= 0;
654 
                Cr32_pos <= 0; Cr32_neg <= 0; Cr32_msb <= 0; Cr32_et_zero <= 0;
655 
                Cr33_pos <= 0; Cr33_neg <= 0; Cr33_msb <= 0; Cr33_et_zero <= 0;
656 
                Cr34_pos <= 0; Cr34_neg <= 0; Cr34_msb <= 0; Cr34_et_zero <= 0;
657 
                Cr35_pos <= 0; Cr35_neg <= 0; Cr35_msb <= 0; Cr35_et_zero <= 0;
658 
                Cr36_pos <= 0; Cr36_neg <= 0; Cr36_msb <= 0; Cr36_et_zero <= 0;
659 
                Cr37_pos <= 0; Cr37_neg <= 0; Cr37_msb <= 0; Cr37_et_zero <= 0;
660 
                Cr38_pos <= 0; Cr38_neg <= 0; Cr38_msb <= 0; Cr38_et_zero <= 0;
661 
                Cr41_pos <= 0; Cr41_neg <= 0; Cr41_msb <= 0; Cr41_et_zero <= 0;
662 
                Cr42_pos <= 0; Cr42_neg <= 0; Cr42_msb <= 0; Cr42_et_zero <= 0;
663 
                Cr43_pos <= 0; Cr43_neg <= 0; Cr43_msb <= 0; Cr43_et_zero <= 0;
664 
                Cr44_pos <= 0; Cr44_neg <= 0; Cr44_msb <= 0; Cr44_et_zero <= 0;
665 
                Cr45_pos <= 0; Cr45_neg <= 0; Cr45_msb <= 0; Cr45_et_zero <= 0;
666 
                Cr46_pos <= 0; Cr46_neg <= 0; Cr46_msb <= 0; Cr46_et_zero <= 0;
667 
                Cr47_pos <= 0; Cr47_neg <= 0; Cr47_msb <= 0; Cr47_et_zero <= 0;
668 
                Cr48_pos <= 0; Cr48_neg <= 0; Cr48_msb <= 0; Cr48_et_zero <= 0;
669 
                Cr51_pos <= 0; Cr51_neg <= 0; Cr51_msb <= 0; Cr51_et_zero <= 0;
670 
                Cr52_pos <= 0; Cr52_neg <= 0; Cr52_msb <= 0; Cr52_et_zero <= 0;
671 
                Cr53_pos <= 0; Cr53_neg <= 0; Cr53_msb <= 0; Cr53_et_zero <= 0;
672 
                Cr54_pos <= 0; Cr54_neg <= 0; Cr54_msb <= 0; Cr54_et_zero <= 0;
673 
                Cr55_pos <= 0; Cr55_neg <= 0; Cr55_msb <= 0; Cr55_et_zero <= 0;
674 
                Cr56_pos <= 0; Cr56_neg <= 0; Cr56_msb <= 0; Cr56_et_zero <= 0;
675 
                Cr57_pos <= 0; Cr57_neg <= 0; Cr57_msb <= 0; Cr57_et_zero <= 0;
676 
                Cr58_pos <= 0; Cr58_neg <= 0; Cr58_msb <= 0; Cr58_et_zero <= 0;
677 
                Cr61_pos <= 0; Cr61_neg <= 0; Cr61_msb <= 0; Cr61_et_zero <= 0;
678 
                Cr62_pos <= 0; Cr62_neg <= 0; Cr62_msb <= 0; Cr62_et_zero <= 0;
679 
                Cr63_pos <= 0; Cr63_neg <= 0; Cr63_msb <= 0; Cr63_et_zero <= 0;
680 
                Cr64_pos <= 0; Cr64_neg <= 0; Cr64_msb <= 0; Cr64_et_zero <= 0;
681 
                Cr65_pos <= 0; Cr65_neg <= 0; Cr65_msb <= 0; Cr65_et_zero <= 0;
682 
                Cr66_pos <= 0; Cr66_neg <= 0; Cr66_msb <= 0; Cr66_et_zero <= 0;
683 
                Cr67_pos <= 0; Cr67_neg <= 0; Cr67_msb <= 0; Cr67_et_zero <= 0;
684 
                Cr68_pos <= 0; Cr68_neg <= 0; Cr68_msb <= 0; Cr68_et_zero <= 0;
685 
                Cr71_pos <= 0; Cr71_neg <= 0; Cr71_msb <= 0; Cr71_et_zero <= 0;
686 
                Cr72_pos <= 0; Cr72_neg <= 0; Cr72_msb <= 0; Cr72_et_zero <= 0;
687 
                Cr73_pos <= 0; Cr73_neg <= 0; Cr73_msb <= 0; Cr73_et_zero <= 0;
688 
                Cr74_pos <= 0; Cr74_neg <= 0; Cr74_msb <= 0; Cr74_et_zero <= 0;
689 
                Cr75_pos <= 0; Cr75_neg <= 0; Cr75_msb <= 0; Cr75_et_zero <= 0;
690 
                Cr76_pos <= 0; Cr76_neg <= 0; Cr76_msb <= 0; Cr76_et_zero <= 0;
691 
                Cr77_pos <= 0; Cr77_neg <= 0; Cr77_msb <= 0; Cr77_et_zero <= 0;
692 
                Cr78_pos <= 0; Cr78_neg <= 0; Cr78_msb <= 0; Cr78_et_zero <= 0;
693 
                Cr81_pos <= 0; Cr81_neg <= 0; Cr81_msb <= 0; Cr81_et_zero <= 0;
694 
                Cr82_pos <= 0; Cr82_neg <= 0; Cr82_msb <= 0; Cr82_et_zero <= 0;
695 
                Cr83_pos <= 0; Cr83_neg <= 0; Cr83_msb <= 0; Cr83_et_zero <= 0;
696 
                Cr84_pos <= 0; Cr84_neg <= 0; Cr84_msb <= 0; Cr84_et_zero <= 0;
697 
                Cr85_pos <= 0; Cr85_neg <= 0; Cr85_msb <= 0; Cr85_et_zero <= 0;
698 
                Cr86_pos <= 0; Cr86_neg <= 0; Cr86_msb <= 0; Cr86_et_zero <= 0;
699 
                Cr87_pos <= 0; Cr87_neg <= 0; Cr87_msb <= 0; Cr87_et_zero <= 0;
700 
                Cr88_pos <= 0; Cr88_neg <= 0; Cr88_msb <= 0; Cr88_et_zero <= 0;
701 
                end
702 
        else if (enable) begin
703 
                Cr12_pos <= Cr12;
704 
                Cr12_neg <= Cr12 - 1;
705 
                Cr12_msb <= Cr12[10];
706 
                Cr12_et_zero <= !(|Cr12);
707 
                Cr13_pos <= Cr13;
708 
                Cr13_neg <= Cr13 - 1;
709 
                Cr13_msb <= Cr13[10];
710 
                Cr13_et_zero <= !(|Cr13);
711 
                Cr14_pos <= Cr14;
712 
                Cr14_neg <= Cr14 - 1;
713 
                Cr14_msb <= Cr14[10];
714 
                Cr14_et_zero <= !(|Cr14);
715 
                Cr15_pos <= Cr15;
716 
                Cr15_neg <= Cr15 - 1;
717 
                Cr15_msb <= Cr15[10];
718 
                Cr15_et_zero <= !(|Cr15);
719 
                Cr16_pos <= Cr16;
720 
                Cr16_neg <= Cr16 - 1;
721 
                Cr16_msb <= Cr16[10];
722 
                Cr16_et_zero <= !(|Cr16);
723 
                Cr17_pos <= Cr17;
724 
                Cr17_neg <= Cr17 - 1;
725 
                Cr17_msb <= Cr17[10];
726 
                Cr17_et_zero <= !(|Cr17);
727 
                Cr18_pos <= Cr18;
728 
                Cr18_neg <= Cr18 - 1;
729 
                Cr18_msb <= Cr18[10];
730 
                Cr18_et_zero <= !(|Cr18);
731 
                Cr21_pos <= Cr21;
732 
                Cr21_neg <= Cr21 - 1;
733 
                Cr21_msb <= Cr21[10];
734 
                Cr21_et_zero <= !(|Cr21);
735 
                Cr22_pos <= Cr22;
736 
                Cr22_neg <= Cr22 - 1;
737 
                Cr22_msb <= Cr22[10];
738 
                Cr22_et_zero <= !(|Cr22);
739 
                Cr23_pos <= Cr23;
740 
                Cr23_neg <= Cr23 - 1;
741 
                Cr23_msb <= Cr23[10];
742 
                Cr23_et_zero <= !(|Cr23);
743 
                Cr24_pos <= Cr24;
744 
                Cr24_neg <= Cr24 - 1;
745 
                Cr24_msb <= Cr24[10];
746 
                Cr24_et_zero <= !(|Cr24);
747 
                Cr25_pos <= Cr25;
748 
                Cr25_neg <= Cr25 - 1;
749 
                Cr25_msb <= Cr25[10];
750 
                Cr25_et_zero <= !(|Cr25);
751 
                Cr26_pos <= Cr26;
752 
                Cr26_neg <= Cr26 - 1;
753 
                Cr26_msb <= Cr26[10];
754 
                Cr26_et_zero <= !(|Cr26);
755 
                Cr27_pos <= Cr27;
756 
                Cr27_neg <= Cr27 - 1;
757 
                Cr27_msb <= Cr27[10];
758 
                Cr27_et_zero <= !(|Cr27);
759 
                Cr28_pos <= Cr28;
760 
                Cr28_neg <= Cr28 - 1;
761 
                Cr28_msb <= Cr28[10];
762 
                Cr28_et_zero <= !(|Cr28);
763 
                Cr31_pos <= Cr31;
764 
                Cr31_neg <= Cr31 - 1;
765 
                Cr31_msb <= Cr31[10];
766 
                Cr31_et_zero <= !(|Cr31);
767 
                Cr32_pos <= Cr32;
768 
                Cr32_neg <= Cr32 - 1;
769 
                Cr32_msb <= Cr32[10];
770 
                Cr32_et_zero <= !(|Cr32);
771 
                Cr33_pos <= Cr33;
772 
                Cr33_neg <= Cr33 - 1;
773 
                Cr33_msb <= Cr33[10];
774 
                Cr33_et_zero <= !(|Cr33);
775 
                Cr34_pos <= Cr34;
776 
                Cr34_neg <= Cr34 - 1;
777 
                Cr34_msb <= Cr34[10];
778 
                Cr34_et_zero <= !(|Cr34);
779 
                Cr35_pos <= Cr35;
780 
                Cr35_neg <= Cr35 - 1;
781 
                Cr35_msb <= Cr35[10];
782 
                Cr35_et_zero <= !(|Cr35);
783 
                Cr36_pos <= Cr36;
784 
                Cr36_neg <= Cr36 - 1;
785 
                Cr36_msb <= Cr36[10];
786 
                Cr36_et_zero <= !(|Cr36);
787 
                Cr37_pos <= Cr37;
788 
                Cr37_neg <= Cr37 - 1;
789 
                Cr37_msb <= Cr37[10];
790 
                Cr37_et_zero <= !(|Cr37);
791 
                Cr38_pos <= Cr38;
792 
                Cr38_neg <= Cr38 - 1;
793 
                Cr38_msb <= Cr38[10];
794 
                Cr38_et_zero <= !(|Cr38);
795 
                Cr41_pos <= Cr41;
796 
                Cr41_neg <= Cr41 - 1;
797 
                Cr41_msb <= Cr41[10];
798 
                Cr41_et_zero <= !(|Cr41);
799 
                Cr42_pos <= Cr42;
800 
                Cr42_neg <= Cr42 - 1;
801 
                Cr42_msb <= Cr42[10];
802 
                Cr42_et_zero <= !(|Cr42);
803 
                Cr43_pos <= Cr43;
804 
                Cr43_neg <= Cr43 - 1;
805 
                Cr43_msb <= Cr43[10];
806 
                Cr43_et_zero <= !(|Cr43);
807 
                Cr44_pos <= Cr44;
808 
                Cr44_neg <= Cr44 - 1;
809 
                Cr44_msb <= Cr44[10];
810 
                Cr44_et_zero <= !(|Cr44);
811 
                Cr45_pos <= Cr45;
812 
                Cr45_neg <= Cr45 - 1;
813 
                Cr45_msb <= Cr45[10];
814 
                Cr45_et_zero <= !(|Cr45);
815 
                Cr46_pos <= Cr46;
816 
                Cr46_neg <= Cr46 - 1;
817 
                Cr46_msb <= Cr46[10];
818 
                Cr46_et_zero <= !(|Cr46);
819 
                Cr47_pos <= Cr47;
820 
                Cr47_neg <= Cr47 - 1;
821 
                Cr47_msb <= Cr47[10];
822 
                Cr47_et_zero <= !(|Cr47);
823 
                Cr48_pos <= Cr48;
824 
                Cr48_neg <= Cr48 - 1;
825 
                Cr48_msb <= Cr48[10];
826 
                Cr48_et_zero <= !(|Cr48);
827 
                Cr51_pos <= Cr51;
828 
                Cr51_neg <= Cr51 - 1;
829 
                Cr51_msb <= Cr51[10];
830 
                Cr51_et_zero <= !(|Cr51);
831 
                Cr52_pos <= Cr52;
832 
                Cr52_neg <= Cr52 - 1;
833 
                Cr52_msb <= Cr52[10];
834 
                Cr52_et_zero <= !(|Cr52);
835 
                Cr53_pos <= Cr53;
836 
                Cr53_neg <= Cr53 - 1;
837 
                Cr53_msb <= Cr53[10];
838 
                Cr53_et_zero <= !(|Cr53);
839 
                Cr54_pos <= Cr54;
840 
                Cr54_neg <= Cr54 - 1;
841 
                Cr54_msb <= Cr54[10];
842 
                Cr54_et_zero <= !(|Cr54);
843 
                Cr55_pos <= Cr55;
844 
                Cr55_neg <= Cr55 - 1;
845 
                Cr55_msb <= Cr55[10];
846 
                Cr55_et_zero <= !(|Cr55);
847 
                Cr56_pos <= Cr56;
848 
                Cr56_neg <= Cr56 - 1;
849 
                Cr56_msb <= Cr56[10];
850 
                Cr56_et_zero <= !(|Cr56);
851 
                Cr57_pos <= Cr57;
852 
                Cr57_neg <= Cr57 - 1;
853 
                Cr57_msb <= Cr57[10];
854 
                Cr57_et_zero <= !(|Cr57);
855 
                Cr58_pos <= Cr58;
856 
                Cr58_neg <= Cr58 - 1;
857 
                Cr58_msb <= Cr58[10];
858 
                Cr58_et_zero <= !(|Cr58);
859 
                Cr61_pos <= Cr61;
860 
                Cr61_neg <= Cr61 - 1;
861 
                Cr61_msb <= Cr61[10];
862 
                Cr61_et_zero <= !(|Cr61);
863 
                Cr62_pos <= Cr62;
864 
                Cr62_neg <= Cr62 - 1;
865 
                Cr62_msb <= Cr62[10];
866 
                Cr62_et_zero <= !(|Cr62);
867 
                Cr63_pos <= Cr63;
868 
                Cr63_neg <= Cr63 - 1;
869 
                Cr63_msb <= Cr63[10];
870 
                Cr63_et_zero <= !(|Cr63);
871 
                Cr64_pos <= Cr64;
872 
                Cr64_neg <= Cr64 - 1;
873 
                Cr64_msb <= Cr64[10];
874 
                Cr64_et_zero <= !(|Cr64);
875 
                Cr65_pos <= Cr65;
876 
                Cr65_neg <= Cr65 - 1;
877 
                Cr65_msb <= Cr65[10];
878 
                Cr65_et_zero <= !(|Cr65);
879 
                Cr66_pos <= Cr66;
880 
                Cr66_neg <= Cr66 - 1;
881 
                Cr66_msb <= Cr66[10];
882 
                Cr66_et_zero <= !(|Cr66);
883 
                Cr67_pos <= Cr67;
884 
                Cr67_neg <= Cr67 - 1;
885 
                Cr67_msb <= Cr67[10];
886 
                Cr67_et_zero <= !(|Cr67);
887 
                Cr68_pos <= Cr68;
888 
                Cr68_neg <= Cr68 - 1;
889 
                Cr68_msb <= Cr68[10];
890 
                Cr68_et_zero <= !(|Cr68);
891 
                Cr71_pos <= Cr71;
892 
                Cr71_neg <= Cr71 - 1;
893 
                Cr71_msb <= Cr71[10];
894 
                Cr71_et_zero <= !(|Cr71);
895 
                Cr72_pos <= Cr72;
896 
                Cr72_neg <= Cr72 - 1;
897 
                Cr72_msb <= Cr72[10];
898 
                Cr72_et_zero <= !(|Cr72);
899 
                Cr73_pos <= Cr73;
900 
                Cr73_neg <= Cr73 - 1;
901 
                Cr73_msb <= Cr73[10];
902 
                Cr73_et_zero <= !(|Cr73);
903 
                Cr74_pos <= Cr74;
904 
                Cr74_neg <= Cr74 - 1;
905 
                Cr74_msb <= Cr74[10];
906 
                Cr74_et_zero <= !(|Cr74);
907 
                Cr75_pos <= Cr75;
908 
                Cr75_neg <= Cr75 - 1;
909 
                Cr75_msb <= Cr75[10];
910 
                Cr75_et_zero <= !(|Cr75);
911 
                Cr76_pos <= Cr76;
912 
                Cr76_neg <= Cr76 - 1;
913 
                Cr76_msb <= Cr76[10];
914 
                Cr76_et_zero <= !(|Cr76);
915 
                Cr77_pos <= Cr77;
916 
                Cr77_neg <= Cr77 - 1;
917 
                Cr77_msb <= Cr77[10];
918 
                Cr77_et_zero <= !(|Cr77);
919 
                Cr78_pos <= Cr78;
920 
                Cr78_neg <= Cr78 - 1;
921 
                Cr78_msb <= Cr78[10];
922 
                Cr78_et_zero <= !(|Cr78);
923 
                Cr81_pos <= Cr81;
924 
                Cr81_neg <= Cr81 - 1;
925 
                Cr81_msb <= Cr81[10];
926 
                Cr81_et_zero <= !(|Cr81);
927 
                Cr82_pos <= Cr82;
928 
                Cr82_neg <= Cr82 - 1;
929 
                Cr82_msb <= Cr82[10];
930 
                Cr82_et_zero <= !(|Cr82);
931 
                Cr83_pos <= Cr83;
932 
                Cr83_neg <= Cr83 - 1;
933 
                Cr83_msb <= Cr83[10];
934 
                Cr83_et_zero <= !(|Cr83);
935 
                Cr84_pos <= Cr84;
936 
                Cr84_neg <= Cr84 - 1;
937 
                Cr84_msb <= Cr84[10];
938 
                Cr84_et_zero <= !(|Cr84);
939 
                Cr85_pos <= Cr85;
940 
                Cr85_neg <= Cr85 - 1;
941 
                Cr85_msb <= Cr85[10];
942 
                Cr85_et_zero <= !(|Cr85);
943 
                Cr86_pos <= Cr86;
944 
                Cr86_neg <= Cr86 - 1;
945 
                Cr86_msb <= Cr86[10];
946 
                Cr86_et_zero <= !(|Cr86);
947 
                Cr87_pos <= Cr87;
948 
                Cr87_neg <= Cr87 - 1;
949 
                Cr87_msb <= Cr87[10];
950 
                Cr87_et_zero <= !(|Cr87);
951 
                Cr88_pos <= Cr88;
952 
                Cr88_neg <= Cr88 - 1;
953 
                Cr88_msb <= Cr88[10];
954 
                Cr88_et_zero <= !(|Cr88);
955 
                end
956 
        else if (enable_module) begin
957 
                Cr12_pos <= Cr21_pos;
958 
                Cr12_neg <= Cr21_neg;
959 
                Cr12_msb <= Cr21_msb;
960 
                Cr12_et_zero <= Cr21_et_zero;
961 
                Cr21_pos <= Cr31_pos;
962 
                Cr21_neg <= Cr31_neg;
963 
                Cr21_msb <= Cr31_msb;
964 
                Cr21_et_zero <= Cr31_et_zero;
965 
                Cr31_pos <= Cr22_pos;
966 
                Cr31_neg <= Cr22_neg;
967 
                Cr31_msb <= Cr22_msb;
968 
                Cr31_et_zero <= Cr22_et_zero;
969 
                Cr22_pos <= Cr13_pos;
970 
                Cr22_neg <= Cr13_neg;
971 
                Cr22_msb <= Cr13_msb;
972 
                Cr22_et_zero <= Cr13_et_zero;
973 
                Cr13_pos <= Cr14_pos;
974 
                Cr13_neg <= Cr14_neg;
975 
                Cr13_msb <= Cr14_msb;
976 
                Cr13_et_zero <= Cr14_et_zero;
977 
                Cr14_pos <= Cr23_pos;
978 
                Cr14_neg <= Cr23_neg;
979 
                Cr14_msb <= Cr23_msb;
980 
                Cr14_et_zero <= Cr23_et_zero;
981 
                Cr23_pos <= Cr32_pos;
982 
                Cr23_neg <= Cr32_neg;
983 
                Cr23_msb <= Cr32_msb;
984 
                Cr23_et_zero <= Cr32_et_zero;
985 
                Cr32_pos <= Cr41_pos;
986 
                Cr32_neg <= Cr41_neg;
987 
                Cr32_msb <= Cr41_msb;
988 
                Cr32_et_zero <= Cr41_et_zero;
989 
                Cr41_pos <= Cr51_pos;
990 
                Cr41_neg <= Cr51_neg;
991 
                Cr41_msb <= Cr51_msb;
992 
                Cr41_et_zero <= Cr51_et_zero;
993 
                Cr51_pos <= Cr42_pos;
994 
                Cr51_neg <= Cr42_neg;
995 
                Cr51_msb <= Cr42_msb;
996 
                Cr51_et_zero <= Cr42_et_zero;
997 
                Cr42_pos <= Cr33_pos;
998 
                Cr42_neg <= Cr33_neg;
999 
                Cr42_msb <= Cr33_msb;
1000 
                Cr42_et_zero <= Cr33_et_zero;
1001 
                Cr33_pos <= Cr24_pos;
1002 
                Cr33_neg <= Cr24_neg;
1003 
                Cr33_msb <= Cr24_msb;
1004 
                Cr33_et_zero <= Cr24_et_zero;
1005 
                Cr24_pos <= Cr15_pos;
1006 
                Cr24_neg <= Cr15_neg;
1007 
                Cr24_msb <= Cr15_msb;
1008 
                Cr24_et_zero <= Cr15_et_zero;
1009 
                Cr15_pos <= Cr16_pos;
1010 
                Cr15_neg <= Cr16_neg;
1011 
                Cr15_msb <= Cr16_msb;
1012 
                Cr15_et_zero <= Cr16_et_zero;
1013 
                Cr16_pos <= Cr25_pos;
1014 
                Cr16_neg <= Cr25_neg;
1015 
                Cr16_msb <= Cr25_msb;
1016 
                Cr16_et_zero <= Cr25_et_zero;
1017 
                Cr25_pos <= Cr34_pos;
1018 
                Cr25_neg <= Cr34_neg;
1019 
                Cr25_msb <= Cr34_msb;
1020 
                Cr25_et_zero <= Cr34_et_zero;
1021 
                Cr34_pos <= Cr43_pos;
1022 
                Cr34_neg <= Cr43_neg;
1023 
                Cr34_msb <= Cr43_msb;
1024 
                Cr34_et_zero <= Cr43_et_zero;
1025 
                Cr43_pos <= Cr52_pos;
1026 
                Cr43_neg <= Cr52_neg;
1027 
                Cr43_msb <= Cr52_msb;
1028 
                Cr43_et_zero <= Cr52_et_zero;
1029 
                Cr52_pos <= Cr61_pos;
1030 
                Cr52_neg <= Cr61_neg;
1031 
                Cr52_msb <= Cr61_msb;
1032 
                Cr52_et_zero <= Cr61_et_zero;
1033 
                Cr61_pos <= Cr71_pos;
1034 
                Cr61_neg <= Cr71_neg;
1035 
                Cr61_msb <= Cr71_msb;
1036 
                Cr61_et_zero <= Cr71_et_zero;
1037 
                Cr71_pos <= Cr62_pos;
1038 
                Cr71_neg <= Cr62_neg;
1039 
                Cr71_msb <= Cr62_msb;
1040 
                Cr71_et_zero <= Cr62_et_zero;
1041 
                Cr62_pos <= Cr53_pos;
1042 
                Cr62_neg <= Cr53_neg;
1043 
                Cr62_msb <= Cr53_msb;
1044 
                Cr62_et_zero <= Cr53_et_zero;
1045 
                Cr53_pos <= Cr44_pos;
1046 
                Cr53_neg <= Cr44_neg;
1047 
                Cr53_msb <= Cr44_msb;
1048 
                Cr53_et_zero <= Cr44_et_zero;
1049 
                Cr44_pos <= Cr35_pos;
1050 
                Cr44_neg <= Cr35_neg;
1051 
                Cr44_msb <= Cr35_msb;
1052 
                Cr44_et_zero <= Cr35_et_zero;
1053 
                Cr35_pos <= Cr26_pos;
1054 
                Cr35_neg <= Cr26_neg;
1055 
                Cr35_msb <= Cr26_msb;
1056 
                Cr35_et_zero <= Cr26_et_zero;
1057 
                Cr26_pos <= Cr17_pos;
1058 
                Cr26_neg <= Cr17_neg;
1059 
                Cr26_msb <= Cr17_msb;
1060 
                Cr26_et_zero <= Cr17_et_zero;
1061 
                Cr17_pos <= Cr18_pos;
1062 
                Cr17_neg <= Cr18_neg;
1063 
                Cr17_msb <= Cr18_msb;
1064 
                Cr17_et_zero <= Cr18_et_zero;
1065 
                Cr18_pos <= Cr27_pos;
1066 
                Cr18_neg <= Cr27_neg;
1067 
                Cr18_msb <= Cr27_msb;
1068 
                Cr18_et_zero <= Cr27_et_zero;
1069 
                Cr27_pos <= Cr36_pos;
1070 
                Cr27_neg <= Cr36_neg;
1071 
                Cr27_msb <= Cr36_msb;
1072 
                Cr27_et_zero <= Cr36_et_zero;
1073 
                Cr36_pos <= Cr45_pos;
1074 
                Cr36_neg <= Cr45_neg;
1075 
                Cr36_msb <= Cr45_msb;
1076 
                Cr36_et_zero <= Cr45_et_zero;
1077 
                Cr45_pos <= Cr54_pos;
1078 
                Cr45_neg <= Cr54_neg;
1079 
                Cr45_msb <= Cr54_msb;
1080 
                Cr45_et_zero <= Cr54_et_zero;
1081 
                Cr54_pos <= Cr63_pos;
1082 
                Cr54_neg <= Cr63_neg;
1083 
                Cr54_msb <= Cr63_msb;
1084 
                Cr54_et_zero <= Cr63_et_zero;
1085 
                Cr63_pos <= Cr72_pos;
1086 
                Cr63_neg <= Cr72_neg;
1087 
                Cr63_msb <= Cr72_msb;
1088 
                Cr63_et_zero <= Cr72_et_zero;
1089 
                Cr72_pos <= Cr81_pos;
1090 
                Cr72_neg <= Cr81_neg;
1091 
                Cr72_msb <= Cr81_msb;
1092 
                Cr72_et_zero <= Cr81_et_zero;
1093 
                Cr81_pos <= Cr82_pos;
1094 
                Cr81_neg <= Cr82_neg;
1095 
                Cr81_msb <= Cr82_msb;
1096 
                Cr81_et_zero <= Cr82_et_zero;
1097 
                Cr82_pos <= Cr73_pos;
1098 
                Cr82_neg <= Cr73_neg;
1099 
                Cr82_msb <= Cr73_msb;
1100 
                Cr82_et_zero <= Cr73_et_zero;
1101 
                Cr73_pos <= Cr64_pos;
1102 
                Cr73_neg <= Cr64_neg;
1103 
                Cr73_msb <= Cr64_msb;
1104 
                Cr73_et_zero <= Cr64_et_zero;
1105 
                Cr64_pos <= Cr55_pos;
1106 
                Cr64_neg <= Cr55_neg;
1107 
                Cr64_msb <= Cr55_msb;
1108 
                Cr64_et_zero <= Cr55_et_zero;
1109 
                Cr55_pos <= Cr46_pos;
1110 
                Cr55_neg <= Cr46_neg;
1111 
                Cr55_msb <= Cr46_msb;
1112 
                Cr55_et_zero <= Cr46_et_zero;
1113 
                Cr46_pos <= Cr37_pos;
1114 
                Cr46_neg <= Cr37_neg;
1115 
                Cr46_msb <= Cr37_msb;
1116 
                Cr46_et_zero <= Cr37_et_zero;
1117 
                Cr37_pos <= Cr28_pos;
1118 
                Cr37_neg <= Cr28_neg;
1119 
                Cr37_msb <= Cr28_msb;
1120 
                Cr37_et_zero <= Cr28_et_zero;
1121 
                Cr28_pos <= Cr38_pos;
1122 
                Cr28_neg <= Cr38_neg;
1123 
                Cr28_msb <= Cr38_msb;
1124 
                Cr28_et_zero <= Cr38_et_zero;
1125 
                Cr38_pos <= Cr47_pos;
1126 
                Cr38_neg <= Cr47_neg;
1127 
                Cr38_msb <= Cr47_msb;
1128 
                Cr38_et_zero <= Cr47_et_zero;
1129 
                Cr47_pos <= Cr56_pos;
1130 
                Cr47_neg <= Cr56_neg;
1131 
                Cr47_msb <= Cr56_msb;
1132 
                Cr47_et_zero <= Cr56_et_zero;
1133 
                Cr56_pos <= Cr65_pos;
1134 
                Cr56_neg <= Cr65_neg;
1135 
                Cr56_msb <= Cr65_msb;
1136 
                Cr56_et_zero <= Cr65_et_zero;
1137 
                Cr65_pos <= Cr74_pos;
1138 
                Cr65_neg <= Cr74_neg;
1139 
                Cr65_msb <= Cr74_msb;
1140 
                Cr65_et_zero <= Cr74_et_zero;
1141 
                Cr74_pos <= Cr83_pos;
1142 
                Cr74_neg <= Cr83_neg;
1143 
                Cr74_msb <= Cr83_msb;
1144 
                Cr74_et_zero <= Cr83_et_zero;
1145 
                Cr83_pos <= Cr84_pos;
1146 
                Cr83_neg <= Cr84_neg;
1147 
                Cr83_msb <= Cr84_msb;
1148 
                Cr83_et_zero <= Cr84_et_zero;
1149 
                Cr84_pos <= Cr75_pos;
1150 
                Cr84_neg <= Cr75_neg;
1151 
                Cr84_msb <= Cr75_msb;
1152 
                Cr84_et_zero <= Cr75_et_zero;
1153 
                Cr75_pos <= Cr66_pos;
1154 
                Cr75_neg <= Cr66_neg;
1155 
                Cr75_msb <= Cr66_msb;
1156 
                Cr75_et_zero <= Cr66_et_zero;
1157 
                Cr66_pos <= Cr57_pos;
1158 
                Cr66_neg <= Cr57_neg;
1159 
                Cr66_msb <= Cr57_msb;
1160 
                Cr66_et_zero <= Cr57_et_zero;
1161 
                Cr57_pos <= Cr48_pos;
1162 
                Cr57_neg <= Cr48_neg;
1163 
                Cr57_msb <= Cr48_msb;
1164 
                Cr57_et_zero <= Cr48_et_zero;
1165 
                Cr48_pos <= Cr58_pos;
1166 
                Cr48_neg <= Cr58_neg;
1167 
                Cr48_msb <= Cr58_msb;
1168 
                Cr48_et_zero <= Cr58_et_zero;
1169 
                Cr58_pos <= Cr67_pos;
1170 
                Cr58_neg <= Cr67_neg;
1171 
                Cr58_msb <= Cr67_msb;
1172 
                Cr58_et_zero <= Cr67_et_zero;
1173 
                Cr67_pos <= Cr76_pos;
1174 
                Cr67_neg <= Cr76_neg;
1175 
                Cr67_msb <= Cr76_msb;
1176 
                Cr67_et_zero <= Cr76_et_zero;
1177 
                Cr76_pos <= Cr85_pos;
1178 
                Cr76_neg <= Cr85_neg;
1179 
                Cr76_msb <= Cr85_msb;
1180 
                Cr76_et_zero <= Cr85_et_zero;
1181 
                Cr85_pos <= Cr86_pos;
1182 
                Cr85_neg <= Cr86_neg;
1183 
                Cr85_msb <= Cr86_msb;
1184 
                Cr85_et_zero <= Cr86_et_zero;
1185 
                Cr86_pos <= Cr77_pos;
1186 
                Cr86_neg <= Cr77_neg;
1187 
                Cr86_msb <= Cr77_msb;
1188 
                Cr86_et_zero <= Cr77_et_zero;
1189 
                Cr77_pos <= Cr68_pos;
1190 
                Cr77_neg <= Cr68_neg;
1191 
                Cr77_msb <= Cr68_msb;
1192 
                Cr77_et_zero <= Cr68_et_zero;
1193 
                Cr68_pos <= Cr78_pos;
1194 
                Cr68_neg <= Cr78_neg;
1195 
                Cr68_msb <= Cr78_msb;
1196 
                Cr68_et_zero <= Cr78_et_zero;
1197 
                Cr78_pos <= Cr87_pos;
1198 
                Cr78_neg <= Cr87_neg;
1199 
                Cr78_msb <= Cr87_msb;
1200 
                Cr78_et_zero <= Cr87_et_zero;
1201 
                Cr87_pos <= Cr88_pos;
1202 
                Cr87_neg <= Cr88_neg;
1203 
                Cr87_msb <= Cr88_msb;
1204 
                Cr87_et_zero <= Cr88_et_zero;
1205 
                Cr88_pos <= 0;
1206 
                Cr88_neg <= 0;
1207 
                Cr88_msb <= 0;
1208 
                Cr88_et_zero <= 1;
1209 
                end
1210 
end
1211 
 
1212 
always @(posedge clk)
1213 
begin
1214 
        if (rst) begin
1215 
                Cr11_diff <= 0; Cr11_1 <= 0;
1216 
                end
1217 
        else if (enable) begin // Need to sign extend Cr11 to 12 bits
1218 
                Cr11_diff <= {Cr11[10], Cr11} - Cr11_previous;
1219 
                Cr11_1 <= Cr11[10] ? { 1'b1, Cr11 } : { 1'b0, Cr11 };
1220 
                end
1221 
end
1222 
 
1223 
always @(posedge clk)
1224 
begin
1225 
        if (rst)
1226 
                Cr11_bits_pos <= 0;
1227 
        else if (Cr11_1_pos[10] == 1)
1228 
                Cr11_bits_pos <= 11;
1229 
        else if (Cr11_1_pos[9] == 1)
1230 
                Cr11_bits_pos <= 10;
1231 
        else if (Cr11_1_pos[8] == 1)
1232 
                Cr11_bits_pos <= 9;
1233 
        else if (Cr11_1_pos[7] == 1)
1234 
                Cr11_bits_pos <= 8;
1235 
        else if (Cr11_1_pos[6] == 1)
1236 
                Cr11_bits_pos <= 7;
1237 
        else if (Cr11_1_pos[5] == 1)
1238 
                Cr11_bits_pos <= 6;
1239 
        else if (Cr11_1_pos[4] == 1)
1240 
                Cr11_bits_pos <= 5;
1241 
        else if (Cr11_1_pos[3] == 1)
1242 
                Cr11_bits_pos <= 4;
1243 
        else if (Cr11_1_pos[2] == 1)
1244 
                Cr11_bits_pos <= 3;
1245 
        else if (Cr11_1_pos[1] == 1)
1246 
                Cr11_bits_pos <= 2;
1247 
        else if (Cr11_1_pos[0] == 1)
1248 
                Cr11_bits_pos <= 1;
1249 
        else
1250 
                Cr11_bits_pos <= 0;
1251 
end
1252 
 
1253 
always @(posedge clk)
1254 
begin
1255 
        if (rst)
1256 
                Cr11_bits_neg <= 0;
1257 
        else if (Cr11_1_neg[10] == 0)
1258 
                Cr11_bits_neg <= 11;
1259 
        else if (Cr11_1_neg[9] == 0)
1260 
                Cr11_bits_neg <= 10;
1261 
        else if (Cr11_1_neg[8] == 0)
1262 
                Cr11_bits_neg <= 9;
1263 
        else if (Cr11_1_neg[7] == 0)
1264 
                Cr11_bits_neg <= 8;
1265 
        else if (Cr11_1_neg[6] == 0)
1266 
                Cr11_bits_neg <= 7;
1267 
        else if (Cr11_1_neg[5] == 0)
1268 
                Cr11_bits_neg <= 6;
1269 
        else if (Cr11_1_neg[4] == 0)
1270 
                Cr11_bits_neg <= 5;
1271 
        else if (Cr11_1_neg[3] == 0)
1272 
                Cr11_bits_neg <= 4;
1273 
        else if (Cr11_1_neg[2] == 0)
1274 
                Cr11_bits_neg <= 3;
1275 
        else if (Cr11_1_neg[1] == 0)
1276 
                Cr11_bits_neg <= 2;
1277 
        else if (Cr11_1_neg[0] == 0)
1278 
                Cr11_bits_neg <= 1;
1279 
        else
1280 
                Cr11_bits_neg <= 0;
1281 
end
1282 
 
1283 
 
1284 
always @(posedge clk)
1285 
begin
1286 
        if (rst)
1287 
                Cr12_bits_pos <= 0;
1288 
        else if (Cr12_pos[9] == 1)
1289 
                Cr12_bits_pos <= 10;
1290 
        else if (Cr12_pos[8] == 1)
1291 
                Cr12_bits_pos <= 9;
1292 
        else if (Cr12_pos[7] == 1)
1293 
                Cr12_bits_pos <= 8;
1294 
        else if (Cr12_pos[6] == 1)
1295 
                Cr12_bits_pos <= 7;
1296 
        else if (Cr12_pos[5] == 1)
1297 
                Cr12_bits_pos <= 6;
1298 
        else if (Cr12_pos[4] == 1)
1299 
                Cr12_bits_pos <= 5;
1300 
        else if (Cr12_pos[3] == 1)
1301 
                Cr12_bits_pos <= 4;
1302 
        else if (Cr12_pos[2] == 1)
1303 
                Cr12_bits_pos <= 3;
1304 
        else if (Cr12_pos[1] == 1)
1305 
                Cr12_bits_pos <= 2;
1306 
        else if (Cr12_pos[0] == 1)
1307 
                Cr12_bits_pos <= 1;
1308 
        else
1309 
                Cr12_bits_pos <= 0;
1310 
end
1311 
 
1312 
always @(posedge clk)
1313 
begin
1314 
        if (rst)
1315 
                Cr12_bits_neg <= 0;
1316 
        else if (Cr12_neg[9] == 0)
1317 
                Cr12_bits_neg <= 10;
1318 
        else if (Cr12_neg[8] == 0)
1319 
                Cr12_bits_neg <= 9;
1320 
        else if (Cr12_neg[7] == 0)
1321 
                Cr12_bits_neg <= 8;
1322 
        else if (Cr12_neg[6] == 0)
1323 
                Cr12_bits_neg <= 7;
1324 
        else if (Cr12_neg[5] == 0)
1325 
                Cr12_bits_neg <= 6;
1326 
        else if (Cr12_neg[4] == 0)
1327 
                Cr12_bits_neg <= 5;
1328 
        else if (Cr12_neg[3] == 0)
1329 
                Cr12_bits_neg <= 4;
1330 
        else if (Cr12_neg[2] == 0)
1331 
                Cr12_bits_neg <= 3;
1332 
        else if (Cr12_neg[1] == 0)
1333 
                Cr12_bits_neg <= 2;
1334 
        else if (Cr12_neg[0] == 0)
1335 
                Cr12_bits_neg <= 1;
1336 
        else
1337 
                Cr12_bits_neg <= 0;
1338 
end
1339 
 
1340 
always @(posedge clk)
1341 
begin
1342 
        if (rst) begin
1343 
                enable_module <= 0;
1344 
                end
1345 
        else if (enable) begin
1346 
                enable_module <= 1;
1347 
                end
1348 
end
1349 
 
1350 
always @(posedge clk)
1351 
begin
1352 
        if (rst) begin
1353 
                enable_latch_7 <= 0;
1354 
                end
1355 
        else if (block_counter == 68)  begin
1356 
                enable_latch_7 <= 0;
1357 
                end
1358 
        else if (enable_6) begin
1359 
                enable_latch_7 <= 1;
1360 
                end
1361 
end
1362 
 
1363 
always @(posedge clk)
1364 
begin
1365 
        if (rst) begin
1366 
                enable_latch_8 <= 0;
1367 
                end
1368 
        else if (enable_7) begin
1369 
                enable_latch_8 <= 1;
1370 
                end
1371 
end
1372 
 
1373 
always @(posedge clk)
1374 
begin
1375 
        if (rst) begin
1376 
                enable_1 <= 0; enable_2 <= 0; enable_3 <= 0;
1377 
                enable_4 <= 0; enable_5 <= 0; enable_6 <= 0;
1378 
                enable_7 <= 0; enable_8 <= 0; enable_9 <= 0;
1379 
                enable_10 <= 0; enable_11 <= 0; enable_12 <= 0;
1380 
                enable_13 <= 0;
1381 
                end
1382 
        else begin
1383 
                enable_1 <= enable; enable_2 <= enable_1; enable_3 <= enable_2;
1384 
                enable_4 <= enable_3; enable_5 <= enable_4; enable_6 <= enable_5;
1385 
                enable_7 <= enable_6; enable_8 <= enable_7; enable_9 <= enable_8;
1386 
                enable_10 <= enable_9; enable_11 <= enable_10; enable_12 <= enable_11;
1387 
                enable_13 <= enable_12;
1388 
                end
1389 
end
1390 
 
1391 
/* These Cr DC and AC code lengths, run lengths, and bit codes
1392 
were created from the Huffman table entries in the JPEG file header.
1393 
For different Huffman tables for different images, these values
1394 
below will need to be changed.  I created a matlab file to automatically
1395 
create these entries from the already encoded JPEG image. This matlab program
1396 
won't be any help if you're starting from scratch with a .tif or other
1397 
raw image file format.  The values below come from a Huffman table, they
1398 
do not actually create the Huffman table based on the probabilities of
1399 
each code created from the image data.  Crou will need another program to
1400 
create the optimal Huffman table, or you can go with a generic Huffman table,
1401 
which will have slightly less than the best compression.*/
1402 
 
1403 
 
1404 
always @(posedge clk)
1405 
begin
1406 
Cr_DC_code_length[0] <= 2;
1407 
Cr_DC_code_length[1] <= 2;
1408 
Cr_DC_code_length[2] <= 2;
1409 
Cr_DC_code_length[3] <= 3;
1410 
Cr_DC_code_length[4] <= 4;
1411 
Cr_DC_code_length[5] <= 5;
1412 
Cr_DC_code_length[6] <= 6;
1413 
Cr_DC_code_length[7] <= 7;
1414 
Cr_DC_code_length[8] <= 8;
1415 
Cr_DC_code_length[9] <= 9;
1416 
Cr_DC_code_length[10] <= 10;
1417 
Cr_DC_code_length[11] <= 11;
1418 
Cr_DC[0] <= 11'b00000000000;
1419 
Cr_DC[1] <= 11'b01000000000;
1420 
Cr_DC[2] <= 11'b10000000000;
1421 
Cr_DC[3] <= 11'b11000000000;
1422 
Cr_DC[4] <= 11'b11100000000;
1423 
Cr_DC[5] <= 11'b11110000000;
1424 
Cr_DC[6] <= 11'b11111000000;
1425 
Cr_DC[7] <= 11'b11111100000;
1426 
Cr_DC[8] <= 11'b11111110000;
1427 
Cr_DC[9] <= 11'b11111111000;
1428 
Cr_DC[10] <= 11'b11111111100;
1429 
Cr_DC[11] <= 11'b11111111110;
1430 
Cr_AC_code_length[0] <= 2;
1431 
Cr_AC_code_length[1] <= 2;
1432 
Cr_AC_code_length[2] <= 3;
1433 
Cr_AC_code_length[3] <= 4;
1434 
Cr_AC_code_length[4] <= 4;
1435 
Cr_AC_code_length[5] <= 4;
1436 
Cr_AC_code_length[6] <= 5;
1437 
Cr_AC_code_length[7] <= 5;
1438 
Cr_AC_code_length[8] <= 5;
1439 
Cr_AC_code_length[9] <= 6;
1440 
Cr_AC_code_length[10] <= 6;
1441 
Cr_AC_code_length[11] <= 7;
1442 
Cr_AC_code_length[12] <= 7;
1443 
Cr_AC_code_length[13] <= 7;
1444 
Cr_AC_code_length[14] <= 7;
1445 
Cr_AC_code_length[15] <= 8;
1446 
Cr_AC_code_length[16] <= 8;
1447 
Cr_AC_code_length[17] <= 8;
1448 
Cr_AC_code_length[18] <= 9;
1449 
Cr_AC_code_length[19] <= 9;
1450 
Cr_AC_code_length[20] <= 9;
1451 
Cr_AC_code_length[21] <= 9;
1452 
Cr_AC_code_length[22] <= 9;
1453 
Cr_AC_code_length[23] <= 10;
1454 
Cr_AC_code_length[24] <= 10;
1455 
Cr_AC_code_length[25] <= 10;
1456 
Cr_AC_code_length[26] <= 10;
1457 
Cr_AC_code_length[27] <= 10;
1458 
Cr_AC_code_length[28] <= 11;
1459 
Cr_AC_code_length[29] <= 11;
1460 
Cr_AC_code_length[30] <= 11;
1461 
Cr_AC_code_length[31] <= 11;
1462 
Cr_AC_code_length[32] <= 12;
1463 
Cr_AC_code_length[33] <= 12;
1464 
Cr_AC_code_length[34] <= 12;
1465 
Cr_AC_code_length[35] <= 12;
1466 
Cr_AC_code_length[36] <= 15;
1467 
Cr_AC_code_length[37] <= 16;
1468 
Cr_AC_code_length[38] <= 16;
1469 
Cr_AC_code_length[39] <= 16;
1470 
Cr_AC_code_length[40] <= 16;
1471 
Cr_AC_code_length[41] <= 16;
1472 
Cr_AC_code_length[42] <= 16;
1473 
Cr_AC_code_length[43] <= 16;
1474 
Cr_AC_code_length[44] <= 16;
1475 
Cr_AC_code_length[45] <= 16;
1476 
Cr_AC_code_length[46] <= 16;
1477 
Cr_AC_code_length[47] <= 16;
1478 
Cr_AC_code_length[48] <= 16;
1479 
Cr_AC_code_length[49] <= 16;
1480 
Cr_AC_code_length[50] <= 16;
1481 
Cr_AC_code_length[51] <= 16;
1482 
Cr_AC_code_length[52] <= 16;
1483 
Cr_AC_code_length[53] <= 16;
1484 
Cr_AC_code_length[54] <= 16;
1485 
Cr_AC_code_length[55] <= 16;
1486 
Cr_AC_code_length[56] <= 16;
1487 
Cr_AC_code_length[57] <= 16;
1488 
Cr_AC_code_length[58] <= 16;
1489 
Cr_AC_code_length[59] <= 16;
1490 
Cr_AC_code_length[60] <= 16;
1491 
Cr_AC_code_length[61] <= 16;
1492 
Cr_AC_code_length[62] <= 16;
1493 
Cr_AC_code_length[63] <= 16;
1494 
Cr_AC_code_length[64] <= 16;
1495 
Cr_AC_code_length[65] <= 16;
1496 
Cr_AC_code_length[66] <= 16;
1497 
Cr_AC_code_length[67] <= 16;
1498 
Cr_AC_code_length[68] <= 16;
1499 
Cr_AC_code_length[69] <= 16;
1500 
Cr_AC_code_length[70] <= 16;
1501 
Cr_AC_code_length[71] <= 16;
1502 
Cr_AC_code_length[72] <= 16;
1503 
Cr_AC_code_length[73] <= 16;
1504 
Cr_AC_code_length[74] <= 16;
1505 
Cr_AC_code_length[75] <= 16;
1506 
Cr_AC_code_length[76] <= 16;
1507 
Cr_AC_code_length[77] <= 16;
1508 
Cr_AC_code_length[78] <= 16;
1509 
Cr_AC_code_length[79] <= 16;
1510 
Cr_AC_code_length[80] <= 16;
1511 
Cr_AC_code_length[81] <= 16;
1512 
Cr_AC_code_length[82] <= 16;
1513 
Cr_AC_code_length[83] <= 16;
1514 
Cr_AC_code_length[84] <= 16;
1515 
Cr_AC_code_length[85] <= 16;
1516 
Cr_AC_code_length[86] <= 16;
1517 
Cr_AC_code_length[87] <= 16;
1518 
Cr_AC_code_length[88] <= 16;
1519 
Cr_AC_code_length[89] <= 16;
1520 
Cr_AC_code_length[90] <= 16;
1521 
Cr_AC_code_length[91] <= 16;
1522 
Cr_AC_code_length[92] <= 16;
1523 
Cr_AC_code_length[93] <= 16;
1524 
Cr_AC_code_length[94] <= 16;
1525 
Cr_AC_code_length[95] <= 16;
1526 
Cr_AC_code_length[96] <= 16;
1527 
Cr_AC_code_length[97] <= 16;
1528 
Cr_AC_code_length[98] <= 16;
1529 
Cr_AC_code_length[99] <= 16;
1530 
Cr_AC_code_length[100] <= 16;
1531 
Cr_AC_code_length[101] <= 16;
1532 
Cr_AC_code_length[102] <= 16;
1533 
Cr_AC_code_length[103] <= 16;
1534 
Cr_AC_code_length[104] <= 16;
1535 
Cr_AC_code_length[105] <= 16;
1536 
Cr_AC_code_length[106] <= 16;
1537 
Cr_AC_code_length[107] <= 16;
1538 
Cr_AC_code_length[108] <= 16;
1539 
Cr_AC_code_length[109] <= 16;
1540 
Cr_AC_code_length[110] <= 16;
1541 
Cr_AC_code_length[111] <= 16;
1542 
Cr_AC_code_length[112] <= 16;
1543 
Cr_AC_code_length[113] <= 16;
1544 
Cr_AC_code_length[114] <= 16;
1545 
Cr_AC_code_length[115] <= 16;
1546 
Cr_AC_code_length[116] <= 16;
1547 
Cr_AC_code_length[117] <= 16;
1548 
Cr_AC_code_length[118] <= 16;
1549 
Cr_AC_code_length[119] <= 16;
1550 
Cr_AC_code_length[120] <= 16;
1551 
Cr_AC_code_length[121] <= 16;
1552 
Cr_AC_code_length[122] <= 16;
1553 
Cr_AC_code_length[123] <= 16;
1554 
Cr_AC_code_length[124] <= 16;
1555 
Cr_AC_code_length[125] <= 16;
1556 
Cr_AC_code_length[126] <= 16;
1557 
Cr_AC_code_length[127] <= 16;
1558 
Cr_AC_code_length[128] <= 16;
1559 
Cr_AC_code_length[129] <= 16;
1560 
Cr_AC_code_length[130] <= 16;
1561 
Cr_AC_code_length[131] <= 16;
1562 
Cr_AC_code_length[132] <= 16;
1563 
Cr_AC_code_length[133] <= 16;
1564 
Cr_AC_code_length[134] <= 16;
1565 
Cr_AC_code_length[135] <= 16;
1566 
Cr_AC_code_length[136] <= 16;
1567 
Cr_AC_code_length[137] <= 16;
1568 
Cr_AC_code_length[138] <= 16;
1569 
Cr_AC_code_length[139] <= 16;
1570 
Cr_AC_code_length[140] <= 16;
1571 
Cr_AC_code_length[141] <= 16;
1572 
Cr_AC_code_length[142] <= 16;
1573 
Cr_AC_code_length[143] <= 16;
1574 
Cr_AC_code_length[144] <= 16;
1575 
Cr_AC_code_length[145] <= 16;
1576 
Cr_AC_code_length[146] <= 16;
1577 
Cr_AC_code_length[147] <= 16;
1578 
Cr_AC_code_length[148] <= 16;
1579 
Cr_AC_code_length[149] <= 16;
1580 
Cr_AC_code_length[150] <= 16;
1581 
Cr_AC_code_length[151] <= 16;
1582 
Cr_AC_code_length[152] <= 16;
1583 
Cr_AC_code_length[153] <= 16;
1584 
Cr_AC_code_length[154] <= 16;
1585 
Cr_AC_code_length[155] <= 16;
1586 
Cr_AC_code_length[156] <= 16;
1587 
Cr_AC_code_length[157] <= 16;
1588 
Cr_AC_code_length[158] <= 16;
1589 
Cr_AC_code_length[159] <= 16;
1590 
Cr_AC_code_length[160] <= 16;
1591 
Cr_AC_code_length[161] <= 16;
1592 
Cr_AC[0] <= 16'b0000000000000000;
1593 
Cr_AC[1] <= 16'b0100000000000000;
1594 
Cr_AC[2] <= 16'b1000000000000000;
1595 
Cr_AC[3] <= 16'b1010000000000000;
1596 
Cr_AC[4] <= 16'b1011000000000000;
1597 
Cr_AC[5] <= 16'b1100000000000000;
1598 
Cr_AC[6] <= 16'b1101000000000000;
1599 
Cr_AC[7] <= 16'b1101100000000000;
1600 
Cr_AC[8] <= 16'b1110000000000000;
1601 
Cr_AC[9] <= 16'b1110100000000000;
1602 
Cr_AC[10] <= 16'b1110110000000000;
1603 
Cr_AC[11] <= 16'b1111000000000000;
1604 
Cr_AC[12] <= 16'b1111001000000000;
1605 
Cr_AC[13] <= 16'b1111010000000000;
1606 
Cr_AC[14] <= 16'b1111011000000000;
1607 
Cr_AC[15] <= 16'b1111100000000000;
1608 
Cr_AC[16] <= 16'b1111100100000000;
1609 
Cr_AC[17] <= 16'b1111101000000000;
1610 
Cr_AC[18] <= 16'b1111101100000000;
1611 
Cr_AC[19] <= 16'b1111101110000000;
1612 
Cr_AC[20] <= 16'b1111110000000000;
1613 
Cr_AC[21] <= 16'b1111110010000000;
1614 
Cr_AC[22] <= 16'b1111110100000000;
1615 
Cr_AC[23] <= 16'b1111110110000000;
1616 
Cr_AC[24] <= 16'b1111110111000000;
1617 
Cr_AC[25] <= 16'b1111111000000000;
1618 
Cr_AC[26] <= 16'b1111111001000000;
1619 
Cr_AC[27] <= 16'b1111111010000000;
1620 
Cr_AC[28] <= 16'b1111111011000000;
1621 
Cr_AC[29] <= 16'b1111111011100000;
1622 
Cr_AC[30] <= 16'b1111111100000000;
1623 
Cr_AC[31] <= 16'b1111111100100000;
1624 
Cr_AC[32] <= 16'b1111111101000000;
1625 
Cr_AC[33] <= 16'b1111111101010000;
1626 
Cr_AC[34] <= 16'b1111111101100000;
1627 
Cr_AC[35] <= 16'b1111111101110000;
1628 
Cr_AC[36] <= 16'b1111111110000000;
1629 
Cr_AC[37] <= 16'b1111111110000010;
1630 
Cr_AC[38] <= 16'b1111111110000011;
1631 
Cr_AC[39] <= 16'b1111111110000100;
1632 
Cr_AC[40] <= 16'b1111111110000101;
1633 
Cr_AC[41] <= 16'b1111111110000110;
1634 
Cr_AC[42] <= 16'b1111111110000111;
1635 
Cr_AC[43] <= 16'b1111111110001000;
1636 
Cr_AC[44] <= 16'b1111111110001001;
1637 
Cr_AC[45] <= 16'b1111111110001010;
1638 
Cr_AC[46] <= 16'b1111111110001011;
1639 
Cr_AC[47] <= 16'b1111111110001100;
1640 
Cr_AC[48] <= 16'b1111111110001101;
1641 
Cr_AC[49] <= 16'b1111111110001110;
1642 
Cr_AC[50] <= 16'b1111111110001111;
1643 
Cr_AC[51] <= 16'b1111111110010000;
1644 
Cr_AC[52] <= 16'b1111111110010001;
1645 
Cr_AC[53] <= 16'b1111111110010010;
1646 
Cr_AC[54] <= 16'b1111111110010011;
1647 
Cr_AC[55] <= 16'b1111111110010100;
1648 
Cr_AC[56] <= 16'b1111111110010101;
1649 
Cr_AC[57] <= 16'b1111111110010110;
1650 
Cr_AC[58] <= 16'b1111111110010111;
1651 
Cr_AC[59] <= 16'b1111111110011000;
1652 
Cr_AC[60] <= 16'b1111111110011001;
1653 
Cr_AC[61] <= 16'b1111111110011010;
1654 
Cr_AC[62] <= 16'b1111111110011011;
1655 
Cr_AC[63] <= 16'b1111111110011100;
1656 
Cr_AC[64] <= 16'b1111111110011101;
1657 
Cr_AC[65] <= 16'b1111111110011110;
1658 
Cr_AC[66] <= 16'b1111111110011111;
1659 
Cr_AC[67] <= 16'b1111111110100000;
1660 
Cr_AC[68] <= 16'b1111111110100001;
1661 
Cr_AC[69] <= 16'b1111111110100010;
1662 
Cr_AC[70] <= 16'b1111111110100011;
1663 
Cr_AC[71] <= 16'b1111111110100100;
1664 
Cr_AC[72] <= 16'b1111111110100101;
1665 
Cr_AC[73] <= 16'b1111111110100110;
1666 
Cr_AC[74] <= 16'b1111111110100111;
1667 
Cr_AC[75] <= 16'b1111111110101000;
1668 
Cr_AC[76] <= 16'b1111111110101001;
1669 
Cr_AC[77] <= 16'b1111111110101010;
1670 
Cr_AC[78] <= 16'b1111111110101011;
1671 
Cr_AC[79] <= 16'b1111111110101100;
1672 
Cr_AC[80] <= 16'b1111111110101101;
1673 
Cr_AC[81] <= 16'b1111111110101110;
1674 
Cr_AC[82] <= 16'b1111111110101111;
1675 
Cr_AC[83] <= 16'b1111111110110000;
1676 
Cr_AC[84] <= 16'b1111111110110001;
1677 
Cr_AC[85] <= 16'b1111111110110010;
1678 
Cr_AC[86] <= 16'b1111111110110011;
1679 
Cr_AC[87] <= 16'b1111111110110100;
1680 
Cr_AC[88] <= 16'b1111111110110101;
1681 
Cr_AC[89] <= 16'b1111111110110110;
1682 
Cr_AC[90] <= 16'b1111111110110111;
1683 
Cr_AC[91] <= 16'b1111111110111000;
1684 
Cr_AC[92] <= 16'b1111111110111001;
1685 
Cr_AC[93] <= 16'b1111111110111010;
1686 
Cr_AC[94] <= 16'b1111111110111011;
1687 
Cr_AC[95] <= 16'b1111111110111100;
1688 
Cr_AC[96] <= 16'b1111111110111101;
1689 
Cr_AC[97] <= 16'b1111111110111110;
1690 
Cr_AC[98] <= 16'b1111111110111111;
1691 
Cr_AC[99] <= 16'b1111111111000000;
1692 
Cr_AC[100] <= 16'b1111111111000001;
1693 
Cr_AC[101] <= 16'b1111111111000010;
1694 
Cr_AC[102] <= 16'b1111111111000011;
1695 
Cr_AC[103] <= 16'b1111111111000100;
1696 
Cr_AC[104] <= 16'b1111111111000101;
1697 
Cr_AC[105] <= 16'b1111111111000110;
1698 
Cr_AC[106] <= 16'b1111111111000111;
1699 
Cr_AC[107] <= 16'b1111111111001000;
1700 
Cr_AC[108] <= 16'b1111111111001001;
1701 
Cr_AC[109] <= 16'b1111111111001010;
1702 
Cr_AC[110] <= 16'b1111111111001011;
1703 
Cr_AC[111] <= 16'b1111111111001100;
1704 
Cr_AC[112] <= 16'b1111111111001101;
1705 
Cr_AC[113] <= 16'b1111111111001110;
1706 
Cr_AC[114] <= 16'b1111111111001111;
1707 
Cr_AC[115] <= 16'b1111111111010000;
1708 
Cr_AC[116] <= 16'b1111111111010001;
1709 
Cr_AC[117] <= 16'b1111111111010010;
1710 
Cr_AC[118] <= 16'b1111111111010011;
1711 
Cr_AC[119] <= 16'b1111111111010100;
1712 
Cr_AC[120] <= 16'b1111111111010101;
1713 
Cr_AC[121] <= 16'b1111111111010110;
1714 
Cr_AC[122] <= 16'b1111111111010111;
1715 
Cr_AC[123] <= 16'b1111111111011000;
1716 
Cr_AC[124] <= 16'b1111111111011001;
1717 
Cr_AC[125] <= 16'b1111111111011010;
1718 
Cr_AC[126] <= 16'b1111111111011011;
1719 
Cr_AC[127] <= 16'b1111111111011100;
1720 
Cr_AC[128] <= 16'b1111111111011101;
1721 
Cr_AC[129] <= 16'b1111111111011110;
1722 
Cr_AC[130] <= 16'b1111111111011111;
1723 
Cr_AC[131] <= 16'b1111111111100000;
1724 
Cr_AC[132] <= 16'b1111111111100001;
1725 
Cr_AC[133] <= 16'b1111111111100010;
1726 
Cr_AC[134] <= 16'b1111111111100011;
1727 
Cr_AC[135] <= 16'b1111111111100100;
1728 
Cr_AC[136] <= 16'b1111111111100101;
1729 
Cr_AC[137] <= 16'b1111111111100110;
1730 
Cr_AC[138] <= 16'b1111111111100111;
1731 
Cr_AC[139] <= 16'b1111111111101000;
1732 
Cr_AC[140] <= 16'b1111111111101001;
1733 
Cr_AC[141] <= 16'b1111111111101010;
1734 
Cr_AC[142] <= 16'b1111111111101011;
1735 
Cr_AC[143] <= 16'b1111111111101100;
1736 
Cr_AC[144] <= 16'b1111111111101101;
1737 
Cr_AC[145] <= 16'b1111111111101110;
1738 
Cr_AC[146] <= 16'b1111111111101111;
1739 
Cr_AC[147] <= 16'b1111111111110000;
1740 
Cr_AC[148] <= 16'b1111111111110001;
1741 
Cr_AC[149] <= 16'b1111111111110010;
1742 
Cr_AC[150] <= 16'b1111111111110011;
1743 
Cr_AC[151] <= 16'b1111111111110100;
1744 
Cr_AC[152] <= 16'b1111111111110101;
1745 
Cr_AC[153] <= 16'b1111111111110110;
1746 
Cr_AC[154] <= 16'b1111111111110111;
1747 
Cr_AC[155] <= 16'b1111111111111000;
1748 
Cr_AC[156] <= 16'b1111111111111001;
1749 
Cr_AC[157] <= 16'b1111111111111010;
1750 
Cr_AC[158] <= 16'b1111111111111011;
1751 
Cr_AC[159] <= 16'b1111111111111100;
1752 
Cr_AC[160] <= 16'b1111111111111101;
1753 
Cr_AC[161] <= 16'b1111111111111110;
1754 
Cr_AC_run_code[1] <= 0;
1755 
Cr_AC_run_code[2] <= 1;
1756 
Cr_AC_run_code[3] <= 2;
1757 
Cr_AC_run_code[0] <= 3;
1758 
Cr_AC_run_code[4] <= 4;
1759 
Cr_AC_run_code[17] <= 5;
1760 
Cr_AC_run_code[5] <= 6;
1761 
Cr_AC_run_code[18] <= 7;
1762 
Cr_AC_run_code[33] <= 8;
1763 
Cr_AC_run_code[49] <= 9;
1764 
Cr_AC_run_code[65] <= 10;
1765 
Cr_AC_run_code[6] <= 11;
1766 
Cr_AC_run_code[19] <= 12;
1767 
Cr_AC_run_code[81] <= 13;
1768 
Cr_AC_run_code[97] <= 14;
1769 
Cr_AC_run_code[7] <= 15;
1770 
Cr_AC_run_code[34] <= 16;
1771 
Cr_AC_run_code[113] <= 17;
1772 
Cr_AC_run_code[20] <= 18;
1773 
Cr_AC_run_code[50] <= 19;
1774 
Cr_AC_run_code[129] <= 20;
1775 
Cr_AC_run_code[145] <= 21;
1776 
Cr_AC_run_code[161] <= 22;
1777 
Cr_AC_run_code[8] <= 23;
1778 
Cr_AC_run_code[35] <= 24;
1779 
Cr_AC_run_code[66] <= 25;
1780 
Cr_AC_run_code[177] <= 26;
1781 
Cr_AC_run_code[193] <= 27;
1782 
Cr_AC_run_code[21] <= 28;
1783 
Cr_AC_run_code[82] <= 29;
1784 
Cr_AC_run_code[209] <= 30;
1785 
Cr_AC_run_code[240] <= 31;
1786 
Cr_AC_run_code[36] <= 32;
1787 
Cr_AC_run_code[51] <= 33;
1788 
Cr_AC_run_code[98] <= 34;
1789 
Cr_AC_run_code[114] <= 35;
1790 
Cr_AC_run_code[130] <= 36;
1791 
Cr_AC_run_code[9] <= 37;
1792 
Cr_AC_run_code[10] <= 38;
1793 
Cr_AC_run_code[22] <= 39;
1794 
Cr_AC_run_code[23] <= 40;
1795 
Cr_AC_run_code[24] <= 41;
1796 
Cr_AC_run_code[25] <= 42;
1797 
Cr_AC_run_code[26] <= 43;
1798 
Cr_AC_run_code[37] <= 44;
1799 
Cr_AC_run_code[38] <= 45;
1800 
Cr_AC_run_code[39] <= 46;
1801 
Cr_AC_run_code[40] <= 47;
1802 
Cr_AC_run_code[41] <= 48;
1803 
Cr_AC_run_code[42] <= 49;
1804 
Cr_AC_run_code[52] <= 50;
1805 
Cr_AC_run_code[53] <= 51;
1806 
Cr_AC_run_code[54] <= 52;
1807 
Cr_AC_run_code[55] <= 53;
1808 
Cr_AC_run_code[56] <= 54;
1809 
Cr_AC_run_code[57] <= 55;
1810 
Cr_AC_run_code[58] <= 56;
1811 
Cr_AC_run_code[67] <= 57;
1812 
Cr_AC_run_code[68] <= 58;
1813 
Cr_AC_run_code[69] <= 59;
1814 
Cr_AC_run_code[70] <= 60;
1815 
Cr_AC_run_code[71] <= 61;
1816 
Cr_AC_run_code[72] <= 62;
1817 
Cr_AC_run_code[73] <= 63;
1818 
Cr_AC_run_code[74] <= 64;
1819 
Cr_AC_run_code[83] <= 65;
1820 
Cr_AC_run_code[84] <= 66;
1821 
Cr_AC_run_code[85] <= 67;
1822 
Cr_AC_run_code[86] <= 68;
1823 
Cr_AC_run_code[87] <= 69;
1824 
Cr_AC_run_code[88] <= 70;
1825 
Cr_AC_run_code[89] <= 71;
1826 
Cr_AC_run_code[90] <= 72;
1827 
Cr_AC_run_code[99] <= 73;
1828 
Cr_AC_run_code[100] <= 74;
1829 
Cr_AC_run_code[101] <= 75;
1830 
Cr_AC_run_code[102] <= 76;
1831 
Cr_AC_run_code[103] <= 77;
1832 
Cr_AC_run_code[104] <= 78;
1833 
Cr_AC_run_code[105] <= 79;
1834 
Cr_AC_run_code[106] <= 80;
1835 
Cr_AC_run_code[115] <= 81;
1836 
Cr_AC_run_code[116] <= 82;
1837 
Cr_AC_run_code[117] <= 83;
1838 
Cr_AC_run_code[118] <= 84;
1839 
Cr_AC_run_code[119] <= 85;
1840 
Cr_AC_run_code[120] <= 86;
1841 
Cr_AC_run_code[121] <= 87;
1842 
Cr_AC_run_code[122] <= 88;
1843 
Cr_AC_run_code[131] <= 89;
1844 
Cr_AC_run_code[132] <= 90;
1845 
Cr_AC_run_code[133] <= 91;
1846 
Cr_AC_run_code[134] <= 92;
1847 
Cr_AC_run_code[135] <= 93;
1848 
Cr_AC_run_code[136] <= 94;
1849 
Cr_AC_run_code[137] <= 95;
1850 
Cr_AC_run_code[138] <= 96;
1851 
Cr_AC_run_code[146] <= 97;
1852 
Cr_AC_run_code[147] <= 98;
1853 
Cr_AC_run_code[148] <= 99;
1854 
Cr_AC_run_code[149] <= 100;
1855 
Cr_AC_run_code[150] <= 101;
1856 
Cr_AC_run_code[151] <= 102;
1857 
Cr_AC_run_code[152] <= 103;
1858 
Cr_AC_run_code[153] <= 104;
1859 
Cr_AC_run_code[154] <= 105;
1860 
Cr_AC_run_code[162] <= 106;
1861 
Cr_AC_run_code[163] <= 107;
1862 
Cr_AC_run_code[164] <= 108;
1863 
Cr_AC_run_code[165] <= 109;
1864 
Cr_AC_run_code[166] <= 110;
1865 
Cr_AC_run_code[167] <= 111;
1866 
Cr_AC_run_code[168] <= 112;
1867 
Cr_AC_run_code[169] <= 113;
1868 
Cr_AC_run_code[170] <= 114;
1869 
Cr_AC_run_code[178] <= 115;
1870 
Cr_AC_run_code[179] <= 116;
1871 
Cr_AC_run_code[180] <= 117;
1872 
Cr_AC_run_code[181] <= 118;
1873 
Cr_AC_run_code[182] <= 119;
1874 
Cr_AC_run_code[183] <= 120;
1875 
Cr_AC_run_code[184] <= 121;
1876 
Cr_AC_run_code[185] <= 122;
1877 
Cr_AC_run_code[186] <= 123;
1878 
Cr_AC_run_code[194] <= 124;
1879 
Cr_AC_run_code[195] <= 125;
1880 
Cr_AC_run_code[196] <= 126;
1881 
Cr_AC_run_code[197] <= 127;
1882 
Cr_AC_run_code[198] <= 128;
1883 
Cr_AC_run_code[199] <= 129;
1884 
Cr_AC_run_code[200] <= 130;
1885 
Cr_AC_run_code[201] <= 131;
1886 
Cr_AC_run_code[202] <= 132;
1887 
Cr_AC_run_code[210] <= 133;
1888 
Cr_AC_run_code[211] <= 134;
1889 
Cr_AC_run_code[212] <= 135;
1890 
Cr_AC_run_code[213] <= 136;
1891 
Cr_AC_run_code[214] <= 137;
1892 
Cr_AC_run_code[215] <= 138;
1893 
Cr_AC_run_code[216] <= 139;
1894 
Cr_AC_run_code[217] <= 140;
1895 
Cr_AC_run_code[218] <= 141;
1896 
Cr_AC_run_code[225] <= 142;
1897 
Cr_AC_run_code[226] <= 143;
1898 
Cr_AC_run_code[227] <= 144;
1899 
Cr_AC_run_code[228] <= 145;
1900 
Cr_AC_run_code[229] <= 146;
1901 
Cr_AC_run_code[230] <= 147;
1902 
Cr_AC_run_code[231] <= 148;
1903 
Cr_AC_run_code[232] <= 149;
1904 
Cr_AC_run_code[233] <= 150;
1905 
Cr_AC_run_code[234] <= 151;
1906 
Cr_AC_run_code[241] <= 152;
1907 
Cr_AC_run_code[242] <= 153;
1908 
Cr_AC_run_code[243] <= 154;
1909 
Cr_AC_run_code[244] <= 155;
1910 
Cr_AC_run_code[245] <= 156;
1911 
Cr_AC_run_code[246] <= 157;
1912 
Cr_AC_run_code[247] <= 158;
1913 
Cr_AC_run_code[248] <= 159;
1914 
Cr_AC_run_code[249] <= 160;
1915 
Cr_AC_run_code[250] <= 161;
1916 
        Cr_AC_run_code[16] <= 0;
1917 
        Cr_AC_run_code[32] <= 0;
1918 
        Cr_AC_run_code[48] <= 0;
1919 
        Cr_AC_run_code[64] <= 0;
1920 
        Cr_AC_run_code[80] <= 0;
1921 
        Cr_AC_run_code[96] <= 0;
1922 
        Cr_AC_run_code[112] <= 0;
1923 
        Cr_AC_run_code[128] <= 0;
1924 
        Cr_AC_run_code[144] <= 0;
1925 
        Cr_AC_run_code[160] <= 0;
1926 
        Cr_AC_run_code[176] <= 0;
1927 
        Cr_AC_run_code[192] <= 0;
1928 
        Cr_AC_run_code[208] <= 0;
1929 
        Cr_AC_run_code[224] <= 0;
1930 
end
1931 
 
1932 
 
1933 
 
1934 
 
1935 
always @(posedge clk)
1936 
begin
1937 
        if (rst)
1938 
                JPEG_bitstream[31] <= 0;
1939 
        else if (enable_module && rollover_7)
1940 
                JPEG_bitstream[31] <= JPEG_bs_5[31];
1941 
        else if (enable_module && orc_8 == 0)
1942 
                JPEG_bitstream[31] <= JPEG_bs_5[31];
1943 
end
1944 
 
1945 
always @(posedge clk)
1946 
begin
1947 
        if (rst)
1948 
                JPEG_bitstream[30] <= 0;
1949 
        else if (enable_module && rollover_7)
1950 
                JPEG_bitstream[30] <= JPEG_bs_5[30];
1951 
        else if (enable_module && orc_8 <= 1)
1952 
                JPEG_bitstream[30] <= JPEG_bs_5[30];
1953 
end
1954 
 
1955 
always @(posedge clk)
1956 
begin
1957 
        if (rst)
1958 
                JPEG_bitstream[29] <= 0;
1959 
        else if (enable_module && rollover_7)
1960 
                JPEG_bitstream[29] <= JPEG_bs_5[29];
1961 
        else if (enable_module && orc_8 <= 2)
1962 
                JPEG_bitstream[29] <= JPEG_bs_5[29];
1963 
end
1964 
 
1965 
always @(posedge clk)
1966 
begin
1967 
        if (rst)
1968 
                JPEG_bitstream[28] <= 0;
1969 
        else if (enable_module && rollover_7)
1970 
                JPEG_bitstream[28] <= JPEG_bs_5[28];
1971 
        else if (enable_module && orc_8 <= 3)
1972 
                JPEG_bitstream[28] <= JPEG_bs_5[28];
1973 
end
1974 
 
1975 
always @(posedge clk)
1976 
begin
1977 
        if (rst)
1978 
                JPEG_bitstream[27] <= 0;
1979 
        else if (enable_module && rollover_7)
1980 
                JPEG_bitstream[27] <= JPEG_bs_5[27];
1981 
        else if (enable_module && orc_8 <= 4)
1982 
                JPEG_bitstream[27] <= JPEG_bs_5[27];
1983 
end
1984 
 
1985 
always @(posedge clk)
1986 
begin
1987 
        if (rst)
1988 
                JPEG_bitstream[26] <= 0;
1989 
        else if (enable_module && rollover_7)
1990 
                JPEG_bitstream[26] <= JPEG_bs_5[26];
1991 
        else if (enable_module && orc_8 <= 5)
1992 
                JPEG_bitstream[26] <= JPEG_bs_5[26];
1993 
end
1994 
 
1995 
always @(posedge clk)
1996 
begin
1997 
        if (rst)
1998 
                JPEG_bitstream[25] <= 0;
1999 
        else if (enable_module && rollover_7)
2000 
                JPEG_bitstream[25] <= JPEG_bs_5[25];
2001 
        else if (enable_module && orc_8 <= 6)
2002 
                JPEG_bitstream[25] <= JPEG_bs_5[25];
2003 
end
2004 
 
2005 
always @(posedge clk)
2006 
begin
2007 
        if (rst)
2008 
                JPEG_bitstream[24] <= 0;
2009 
        else if (enable_module && rollover_7)
2010 
                JPEG_bitstream[24] <= JPEG_bs_5[24];
2011 
        else if (enable_module && orc_8 <= 7)
2012 
                JPEG_bitstream[24] <= JPEG_bs_5[24];
2013 
end
2014 
 
2015 
always @(posedge clk)
2016 
begin
2017 
        if (rst)
2018 
                JPEG_bitstream[23] <= 0;
2019 
        else if (enable_module && rollover_7)
2020 
                JPEG_bitstream[23] <= JPEG_bs_5[23];
2021 
        else if (enable_module && orc_8 <= 8)
2022 
                JPEG_bitstream[23] <= JPEG_bs_5[23];
2023 
end
2024 
 
2025 
always @(posedge clk)
2026 
begin
2027 
        if (rst)
2028 
                JPEG_bitstream[22] <= 0;
2029 
        else if (enable_module && rollover_7)
2030 
                JPEG_bitstream[22] <= JPEG_bs_5[22];
2031 
        else if (enable_module && orc_8 <= 9)
2032 
                JPEG_bitstream[22] <= JPEG_bs_5[22];
2033 
end
2034 
 
2035 
always @(posedge clk)
2036 
begin
2037 
        if (rst)
2038 
                JPEG_bitstream[21] <= 0;
2039 
        else if (enable_module && rollover_7)
2040 
                JPEG_bitstream[21] <= JPEG_bs_5[21];
2041 
        else if (enable_module && orc_8 <= 10)
2042 
                JPEG_bitstream[21] <= JPEG_bs_5[21];
2043 
end
2044 
 
2045 
always @(posedge clk)
2046 
begin
2047 
        if (rst)
2048 
                JPEG_bitstream[20] <= 0;
2049 
        else if (enable_module && rollover_7)
2050 
                JPEG_bitstream[20] <= JPEG_bs_5[20];
2051 
        else if (enable_module && orc_8 <= 11)
2052 
                JPEG_bitstream[20] <= JPEG_bs_5[20];
2053 
end
2054 
 
2055 
always @(posedge clk)
2056 
begin
2057 
        if (rst)
2058 
                JPEG_bitstream[19] <= 0;
2059 
        else if (enable_module && rollover_7)
2060 
                JPEG_bitstream[19] <= JPEG_bs_5[19];
2061 
        else if (enable_module && orc_8 <= 12)
2062 
                JPEG_bitstream[19] <= JPEG_bs_5[19];
2063 
end
2064 
 
2065 
always @(posedge clk)
2066 
begin
2067 
        if (rst)
2068 
                JPEG_bitstream[18] <= 0;
2069 
        else if (enable_module && rollover_7)
2070 
                JPEG_bitstream[18] <= JPEG_bs_5[18];
2071 
        else if (enable_module && orc_8 <= 13)
2072 
                JPEG_bitstream[18] <= JPEG_bs_5[18];
2073 
end
2074 
 
2075 
always @(posedge clk)
2076 
begin
2077 
        if (rst)
2078 
                JPEG_bitstream[17] <= 0;
2079 
        else if (enable_module && rollover_7)
2080 
                JPEG_bitstream[17] <= JPEG_bs_5[17];
2081 
        else if (enable_module && orc_8 <= 14)
2082 
                JPEG_bitstream[17] <= JPEG_bs_5[17];
2083 
end
2084 
 
2085 
always @(posedge clk)
2086 
begin
2087 
        if (rst)
2088 
                JPEG_bitstream[16] <= 0;
2089 
        else if (enable_module && rollover_7)
2090 
                JPEG_bitstream[16] <= JPEG_bs_5[16];
2091 
        else if (enable_module && orc_8 <= 15)
2092 
                JPEG_bitstream[16] <= JPEG_bs_5[16];
2093 
end
2094 
 
2095 
always @(posedge clk)
2096 
begin
2097 
        if (rst)
2098 
                JPEG_bitstream[15] <= 0;
2099 
        else if (enable_module && rollover_7)
2100 
                JPEG_bitstream[15] <= JPEG_bs_5[15];
2101 
        else if (enable_module && orc_8 <= 16)
2102 
                JPEG_bitstream[15] <= JPEG_bs_5[15];
2103 
end
2104 
 
2105 
always @(posedge clk)
2106 
begin
2107 
        if (rst)
2108 
                JPEG_bitstream[14] <= 0;
2109 
        else if (enable_module && rollover_7)
2110 
                JPEG_bitstream[14] <= JPEG_bs_5[14];
2111 
        else if (enable_module && orc_8 <= 17)
2112 
                JPEG_bitstream[14] <= JPEG_bs_5[14];
2113 
end
2114 
 
2115 
always @(posedge clk)
2116 
begin
2117 
        if (rst)
2118 
                JPEG_bitstream[13] <= 0;
2119 
        else if (enable_module && rollover_7)
2120 
                JPEG_bitstream[13] <= JPEG_bs_5[13];
2121 
        else if (enable_module && orc_8 <= 18)
2122 
                JPEG_bitstream[13] <= JPEG_bs_5[13];
2123 
end
2124 
 
2125 
always @(posedge clk)
2126 
begin
2127 
        if (rst)
2128 
                JPEG_bitstream[12] <= 0;
2129 
        else if (enable_module && rollover_7)
2130 
                JPEG_bitstream[12] <= JPEG_bs_5[12];
2131 
        else if (enable_module && orc_8 <= 19)
2132 
                JPEG_bitstream[12] <= JPEG_bs_5[12];
2133 
end
2134 
 
2135 
always @(posedge clk)
2136 
begin
2137 
        if (rst)
2138 
                JPEG_bitstream[11] <= 0;
2139 
        else if (enable_module && rollover_7)
2140 
                JPEG_bitstream[11] <= JPEG_bs_5[11];
2141 
        else if (enable_module && orc_8 <= 20)
2142 
                JPEG_bitstream[11] <= JPEG_bs_5[11];
2143 
end
2144 
 
2145 
always @(posedge clk)
2146 
begin
2147 
        if (rst)
2148 
                JPEG_bitstream[10] <= 0;
2149 
        else if (enable_module && rollover_7)
2150 
                JPEG_bitstream[10] <= JPEG_bs_5[10];
2151 
        else if (enable_module && orc_8 <= 21)
2152 
                JPEG_bitstream[10] <= JPEG_bs_5[10];
2153 
end
2154 
 
2155 
always @(posedge clk)
2156 
begin
2157 
        if (rst)
2158 
                JPEG_bitstream[9] <= 0;
2159 
        else if (enable_module && rollover_7)
2160 
                JPEG_bitstream[9] <= JPEG_bs_5[9];
2161 
        else if (enable_module && orc_8 <= 22)
2162 
                JPEG_bitstream[9] <= JPEG_bs_5[9];
2163 
end
2164 
 
2165 
always @(posedge clk)
2166 
begin
2167 
        if (rst)
2168 
                JPEG_bitstream[8] <= 0;
2169 
        else if (enable_module && rollover_7)
2170 
                JPEG_bitstream[8] <= JPEG_bs_5[8];
2171 
        else if (enable_module && orc_8 <= 23)
2172 
                JPEG_bitstream[8] <= JPEG_bs_5[8];
2173 
end
2174 
 
2175 
always @(posedge clk)
2176 
begin
2177 
        if (rst)
2178 
                JPEG_bitstream[7] <= 0;
2179 
        else if (enable_module && rollover_7)
2180 
                JPEG_bitstream[7] <= JPEG_bs_5[7];
2181 
        else if (enable_module && orc_8 <= 24)
2182 
                JPEG_bitstream[7] <= JPEG_bs_5[7];
2183 
end
2184 
 
2185 
always @(posedge clk)
2186 
begin
2187 
        if (rst)
2188 
                JPEG_bitstream[6] <= 0;
2189 
        else if (enable_module && rollover_7)
2190 
                JPEG_bitstream[6] <= JPEG_bs_5[6];
2191 
        else if (enable_module && orc_8 <= 25)
2192 
                JPEG_bitstream[6] <= JPEG_bs_5[6];
2193 
end
2194 
 
2195 
always @(posedge clk)
2196 
begin
2197 
        if (rst)
2198 
                JPEG_bitstream[5] <= 0;
2199 
        else if (enable_module && rollover_7)
2200 
                JPEG_bitstream[5] <= JPEG_bs_5[5];
2201 
        else if (enable_module && orc_8 <= 26)
2202 
                JPEG_bitstream[5] <= JPEG_bs_5[5];
2203 
end
2204 
 
2205 
always @(posedge clk)
2206 
begin
2207 
        if (rst)
2208 
                JPEG_bitstream[4] <= 0;
2209 
        else if (enable_module && rollover_7)
2210 
                JPEG_bitstream[4] <= JPEG_bs_5[4];
2211 
        else if (enable_module && orc_8 <= 27)
2212 
                JPEG_bitstream[4] <= JPEG_bs_5[4];
2213 
end
2214 
 
2215 
always @(posedge clk)
2216 
begin
2217 
        if (rst)
2218 
                JPEG_bitstream[3] <= 0;
2219 
        else if (enable_module && rollover_7)
2220 
                JPEG_bitstream[3] <= JPEG_bs_5[3];
2221 
        else if (enable_module && orc_8 <= 28)
2222 
                JPEG_bitstream[3] <= JPEG_bs_5[3];
2223 
end
2224 
 
2225 
always @(posedge clk)
2226 
begin
2227 
        if (rst)
2228 
                JPEG_bitstream[2] <= 0;
2229 
        else if (enable_module && rollover_7)
2230 
                JPEG_bitstream[2] <= JPEG_bs_5[2];
2231 
        else if (enable_module && orc_8 <= 29)
2232 
                JPEG_bitstream[2] <= JPEG_bs_5[2];
2233 
end
2234 
 
2235 
always @(posedge clk)
2236 
begin
2237 
        if (rst)
2238 
                JPEG_bitstream[1] <= 0;
2239 
        else if (enable_module && rollover_7)
2240 
                JPEG_bitstream[1] <= JPEG_bs_5[1];
2241 
        else if (enable_module && orc_8 <= 30)
2242 
                JPEG_bitstream[1] <= JPEG_bs_5[1];
2243 
end
2244 
 
2245 
always @(posedge clk)
2246 
begin
2247 
        if (rst)
2248 
                JPEG_bitstream[0] <= 0;
2249 
        else if (enable_module && rollover_7)
2250 
                JPEG_bitstream[0] <= JPEG_bs_5[0];
2251 
        else if (enable_module && orc_8 <= 31)
2252 
                JPEG_bitstream[0] <= JPEG_bs_5[0];
2253 
end
2254 
endmodule

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