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1 2 davidklun 
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  JPEG Encoder Core - Verilog                                ////
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////                                                             ////
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////  Author: David Lundgren                                     ////
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////          davidklun@gmail.com                                ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2009 David Lundgren                           ////
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////                  davidklun@gmail.com                        ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
33 
 
34 
/* This module comes after the dct module.  The 64 matrix entries calculated after
35 
performing the 2D DCT are inputs to this quantization module.  This module quantizes
36 
the entire 8x8 block of Cr values.  The outputs from this module
37 
are the quantized Cr values for one 8x8 block. */
38 
 
39 
`timescale 1ns / 100ps
40 
 
41 
module cr_quantizer(clk, rst, enable,
42 
Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28,
43 
Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48,
44 
Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58, Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68,
45 
Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78, Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88,
46 
Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28,
47 
Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48,
48 
Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68,
49 
Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78, Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88,
50 
out_enable);
51 
input           clk;
52 
input           rst;
53 
input           enable;
54 
input  [10:0]  Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z21, Z22, Z23, Z24;
55 
input  [10:0]  Z25, Z26, Z27, Z28, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38;
56 
input  [10:0]  Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z51, Z52, Z53, Z54;
57 
input  [10:0]  Z55, Z56, Z57, Z58, Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68;
58 
input  [10:0]  Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78, Z81, Z82, Z83, Z84;
59 
input  [10:0]  Z85, Z86, Z87, Z88;
60 
output  [10:0]  Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q21, Q22, Q23, Q24;
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output  [10:0]  Q25, Q26, Q27, Q28, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38;
62 
output  [10:0]  Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q51, Q52, Q53, Q54;
63 
output  [10:0]  Q55, Q56, Q57, Q58, Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68;
64 
output  [10:0]  Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78, Q81, Q82, Q83, Q84;
65 
output  [10:0]  Q85, Q86, Q87, Q88;
66 
output          out_enable;
67 
 
68 
/* Below are the quantization values, these can be changed for different
69 
quantization levels */
70 
 
71 
parameter Q1_1  = 1;
72 
parameter Q1_2  = 1;
73 
parameter Q1_3  = 1;
74 
parameter Q1_4  = 1;
75 
parameter Q1_5  = 1;
76 
parameter Q1_6  = 1;
77 
parameter Q1_7  = 1;
78 
parameter Q1_8  = 1;
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parameter Q2_1  = 1;
80 
parameter Q2_2  = 1;
81 
parameter Q2_3  = 1;
82 
parameter Q2_4  = 1;
83 
parameter Q2_5  = 1;
84 
parameter Q2_6  = 1;
85 
parameter Q2_7  = 1;
86 
parameter Q2_8  = 1;
87 
parameter Q3_1  = 1;
88 
parameter Q3_2  = 1;
89 
parameter Q3_3  = 1;
90 
parameter Q3_4  = 1;
91 
parameter Q3_5  = 1;
92 
parameter Q3_6  = 1;
93 
parameter Q3_7  = 1;
94 
parameter Q3_8  = 1;
95 
parameter Q4_1  = 1;
96 
parameter Q4_2  = 1;
97 
parameter Q4_3  = 1;
98 
parameter Q4_4  = 1;
99 
parameter Q4_5  = 1;
100 
parameter Q4_6  = 1;
101 
parameter Q4_7  = 1;
102 
parameter Q4_8  = 1;
103 
parameter Q5_1  = 1;
104 
parameter Q5_2  = 1;
105 
parameter Q5_3  = 1;
106 
parameter Q5_4  = 1;
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parameter Q5_5  = 1;
108 
parameter Q5_6  = 1;
109 
parameter Q5_7  = 1;
110 
parameter Q5_8  = 1;
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parameter Q6_1  = 1;
112 
parameter Q6_2  = 1;
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parameter Q6_3  = 1;
114 
parameter Q6_4  = 1;
115 
parameter Q6_5  = 1;
116 
parameter Q6_6  = 1;
117 
parameter Q6_7  = 1;
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parameter Q6_8  = 1;
119 
parameter Q7_1  = 1;
120 
parameter Q7_2  = 1;
121 
parameter Q7_3  = 1;
122 
parameter Q7_4  = 1;
123 
parameter Q7_5  = 1;
124 
parameter Q7_6  = 1;
125 
parameter Q7_7  = 1;
126 
parameter Q7_8  = 1;
127 
parameter Q8_1  = 1;
128 
parameter Q8_2  = 1;
129 
parameter Q8_3  = 1;
130 
parameter Q8_4  = 1;
131 
parameter Q8_5  = 1;
132 
parameter Q8_6  = 1;
133 
parameter Q8_7  = 1;
134 
parameter Q8_8  = 1;
135 
// End of Quantization Values
136 
 
137 
/* The following parameters hold the values of 4096 divided by the corresponding
138 
individual quantization values.  These values are needed to get around
139 
actually dividing the Y, Cb, and Cr values by the quantization values.
140 
Instead, you can multiply by the values below, and then divide by 4096
141 
to get the same result.  And 4096 = 2^12, so instead of dividing, you can
142 
just shift the bottom 12 bits out.  This is a lossy process, as 4096/Q divided
143 
by 4096 doesn't always equal the same value as if you were just dividing by Q.  But
144 
the quantization process is also lossy, so the additional loss of precision is
145 
negligible.  To decrease the loss, you could use a larger number than 4096 to
146 
get around the actual use of division.  Like take 8192/Q and then divide by 8192.*/
147 
 
148 
parameter QQ1_1 = 4096/Q1_1;
149 
parameter QQ1_2 = 4096/Q1_2;
150 
parameter QQ1_3 = 4096/Q1_3;
151 
parameter QQ1_4 = 4096/Q1_4;
152 
parameter QQ1_5 = 4096/Q1_5;
153 
parameter QQ1_6 = 4096/Q1_6;
154 
parameter QQ1_7 = 4096/Q1_7;
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parameter QQ1_8 = 4096/Q1_8;
156 
parameter QQ2_1 = 4096/Q2_1;
157 
parameter QQ2_2 = 4096/Q2_2;
158 
parameter QQ2_3 = 4096/Q2_3;
159 
parameter QQ2_4 = 4096/Q2_4;
160 
parameter QQ2_5 = 4096/Q2_5;
161 
parameter QQ2_6 = 4096/Q2_6;
162 
parameter QQ2_7 = 4096/Q2_7;
163 
parameter QQ2_8 = 4096/Q2_8;
164 
parameter QQ3_1 = 4096/Q3_1;
165 
parameter QQ3_2 = 4096/Q3_2;
166 
parameter QQ3_3 = 4096/Q3_3;
167 
parameter QQ3_4 = 4096/Q3_4;
168 
parameter QQ3_5 = 4096/Q3_5;
169 
parameter QQ3_6 = 4096/Q3_6;
170 
parameter QQ3_7 = 4096/Q3_7;
171 
parameter QQ3_8 = 4096/Q3_8;
172 
parameter QQ4_1 = 4096/Q4_1;
173 
parameter QQ4_2 = 4096/Q4_2;
174 
parameter QQ4_3 = 4096/Q4_3;
175 
parameter QQ4_4 = 4096/Q4_4;
176 
parameter QQ4_5 = 4096/Q4_5;
177 
parameter QQ4_6 = 4096/Q4_6;
178 
parameter QQ4_7 = 4096/Q4_7;
179 
parameter QQ4_8 = 4096/Q4_8;
180 
parameter QQ5_1 = 4096/Q5_1;
181 
parameter QQ5_2 = 4096/Q5_2;
182 
parameter QQ5_3 = 4096/Q5_3;
183 
parameter QQ5_4 = 4096/Q5_4;
184 
parameter QQ5_5 = 4096/Q5_5;
185 
parameter QQ5_6 = 4096/Q5_6;
186 
parameter QQ5_7 = 4096/Q5_7;
187 
parameter QQ5_8 = 4096/Q5_8;
188 
parameter QQ6_1 = 4096/Q6_1;
189 
parameter QQ6_2 = 4096/Q6_2;
190 
parameter QQ6_3 = 4096/Q6_3;
191 
parameter QQ6_4 = 4096/Q6_4;
192 
parameter QQ6_5 = 4096/Q6_5;
193 
parameter QQ6_6 = 4096/Q6_6;
194 
parameter QQ6_7 = 4096/Q6_7;
195 
parameter QQ6_8 = 4096/Q6_8;
196 
parameter QQ7_1 = 4096/Q7_1;
197 
parameter QQ7_2 = 4096/Q7_2;
198 
parameter QQ7_3 = 4096/Q7_3;
199 
parameter QQ7_4 = 4096/Q7_4;
200 
parameter QQ7_5 = 4096/Q7_5;
201 
parameter QQ7_6 = 4096/Q7_6;
202 
parameter QQ7_7 = 4096/Q7_7;
203 
parameter QQ7_8 = 4096/Q7_8;
204 
parameter QQ8_1 = 4096/Q8_1;
205 
parameter QQ8_2 = 4096/Q8_2;
206 
parameter QQ8_3 = 4096/Q8_3;
207 
parameter QQ8_4 = 4096/Q8_4;
208 
parameter QQ8_5 = 4096/Q8_5;
209 
parameter QQ8_6 = 4096/Q8_6;
210 
parameter QQ8_7 = 4096/Q8_7;
211 
parameter QQ8_8 = 4096/Q8_8;
212 
 
213 
wire [12:0] QM1_1 = QQ1_1;
214 
wire [12:0] QM1_2 = QQ1_2;
215 
wire [12:0] QM1_3 = QQ1_3;
216 
wire [12:0] QM1_4 = QQ1_4;
217 
wire [12:0] QM1_5 = QQ1_5;
218 
wire [12:0] QM1_6 = QQ1_6;
219 
wire [12:0] QM1_7 = QQ1_7;
220 
wire [12:0] QM1_8 = QQ1_8;
221 
wire [12:0] QM2_1 = QQ2_1;
222 
wire [12:0] QM2_2 = QQ2_2;
223 
wire [12:0] QM2_3 = QQ2_3;
224 
wire [12:0] QM2_4 = QQ2_4;
225 
wire [12:0] QM2_5 = QQ2_5;
226 
wire [12:0] QM2_6 = QQ2_6;
227 
wire [12:0] QM2_7 = QQ2_7;
228 
wire [12:0] QM2_8 = QQ2_8;
229 
wire [12:0] QM3_1 = QQ3_1;
230 
wire [12:0] QM3_2 = QQ3_2;
231 
wire [12:0] QM3_3 = QQ3_3;
232 
wire [12:0] QM3_4 = QQ3_4;
233 
wire [12:0] QM3_5 = QQ3_5;
234 
wire [12:0] QM3_6 = QQ3_6;
235 
wire [12:0] QM3_7 = QQ3_7;
236 
wire [12:0] QM3_8 = QQ3_8;
237 
wire [12:0] QM4_1 = QQ4_1;
238 
wire [12:0] QM4_2 = QQ4_2;
239 
wire [12:0] QM4_3 = QQ4_3;
240 
wire [12:0] QM4_4 = QQ4_4;
241 
wire [12:0] QM4_5 = QQ4_5;
242 
wire [12:0] QM4_6 = QQ4_6;
243 
wire [12:0] QM4_7 = QQ4_7;
244 
wire [12:0] QM4_8 = QQ4_8;
245 
wire [12:0] QM5_1 = QQ5_1;
246 
wire [12:0] QM5_2 = QQ5_2;
247 
wire [12:0] QM5_3 = QQ5_3;
248 
wire [12:0] QM5_4 = QQ5_4;
249 
wire [12:0] QM5_5 = QQ5_5;
250 
wire [12:0] QM5_6 = QQ5_6;
251 
wire [12:0] QM5_7 = QQ5_7;
252 
wire [12:0] QM5_8 = QQ5_8;
253 
wire [12:0] QM6_1 = QQ6_1;
254 
wire [12:0] QM6_2 = QQ6_2;
255 
wire [12:0] QM6_3 = QQ6_3;
256 
wire [12:0] QM6_4 = QQ6_4;
257 
wire [12:0] QM6_5 = QQ6_5;
258 
wire [12:0] QM6_6 = QQ6_6;
259 
wire [12:0] QM6_7 = QQ6_7;
260 
wire [12:0] QM6_8 = QQ6_8;
261 
wire [12:0] QM7_1 = QQ7_1;
262 
wire [12:0] QM7_2 = QQ7_2;
263 
wire [12:0] QM7_3 = QQ7_3;
264 
wire [12:0] QM7_4 = QQ7_4;
265 
wire [12:0] QM7_5 = QQ7_5;
266 
wire [12:0] QM7_6 = QQ7_6;
267 
wire [12:0] QM7_7 = QQ7_7;
268 
wire [12:0] QM7_8 = QQ7_8;
269 
wire [12:0] QM8_1 = QQ8_1;
270 
wire [12:0] QM8_2 = QQ8_2;
271 
wire [12:0] QM8_3 = QQ8_3;
272 
wire [12:0] QM8_4 = QQ8_4;
273 
wire [12:0] QM8_5 = QQ8_5;
274 
wire [12:0] QM8_6 = QQ8_6;
275 
wire [12:0] QM8_7 = QQ8_7;
276 
wire [12:0] QM8_8 = QQ8_8;
277 
reg [22:0] Z11_temp, Z12_temp, Z13_temp, Z14_temp, Z15_temp, Z16_temp, Z17_temp, Z18_temp;
278 
reg [22:0] Z21_temp, Z22_temp, Z23_temp, Z24_temp, Z25_temp, Z26_temp, Z27_temp, Z28_temp;
279 
reg [22:0] Z31_temp, Z32_temp, Z33_temp, Z34_temp, Z35_temp, Z36_temp, Z37_temp, Z38_temp;
280 
reg [22:0] Z41_temp, Z42_temp, Z43_temp, Z44_temp, Z45_temp, Z46_temp, Z47_temp, Z48_temp;
281 
reg [22:0] Z51_temp, Z52_temp, Z53_temp, Z54_temp, Z55_temp, Z56_temp, Z57_temp, Z58_temp;
282 
reg [22:0] Z61_temp, Z62_temp, Z63_temp, Z64_temp, Z65_temp, Z66_temp, Z67_temp, Z68_temp;
283 
reg [22:0] Z71_temp, Z72_temp, Z73_temp, Z74_temp, Z75_temp, Z76_temp, Z77_temp, Z78_temp;
284 
reg [22:0] Z81_temp, Z82_temp, Z83_temp, Z84_temp, Z85_temp, Z86_temp, Z87_temp, Z88_temp;
285 
reg [22:0] Z11_temp_1, Z12_temp_1, Z13_temp_1, Z14_temp_1, Z15_temp_1, Z16_temp_1, Z17_temp_1, Z18_temp_1;
286 
reg [22:0] Z21_temp_1, Z22_temp_1, Z23_temp_1, Z24_temp_1, Z25_temp_1, Z26_temp_1, Z27_temp_1, Z28_temp_1;
287 
reg [22:0] Z31_temp_1, Z32_temp_1, Z33_temp_1, Z34_temp_1, Z35_temp_1, Z36_temp_1, Z37_temp_1, Z38_temp_1;
288 
reg [22:0] Z41_temp_1, Z42_temp_1, Z43_temp_1, Z44_temp_1, Z45_temp_1, Z46_temp_1, Z47_temp_1, Z48_temp_1;
289 
reg [22:0] Z51_temp_1, Z52_temp_1, Z53_temp_1, Z54_temp_1, Z55_temp_1, Z56_temp_1, Z57_temp_1, Z58_temp_1;
290 
reg [22:0] Z61_temp_1, Z62_temp_1, Z63_temp_1, Z64_temp_1, Z65_temp_1, Z66_temp_1, Z67_temp_1, Z68_temp_1;
291 
reg [22:0] Z71_temp_1, Z72_temp_1, Z73_temp_1, Z74_temp_1, Z75_temp_1, Z76_temp_1, Z77_temp_1, Z78_temp_1;
292 
reg [22:0] Z81_temp_1, Z82_temp_1, Z83_temp_1, Z84_temp_1, Z85_temp_1, Z86_temp_1, Z87_temp_1, Z88_temp_1;
293 
reg [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18;
294 
reg [10:0] Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28;
295 
reg [10:0] Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38;
296 
reg [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48;
297 
reg [10:0] Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58;
298 
reg [10:0] Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68;
299 
reg [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78;
300 
reg [10:0] Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88;
301 
reg out_enable, enable_1, enable_2, enable_3;
302 
integer Z11_int, Z12_int, Z13_int, Z14_int, Z15_int, Z16_int, Z17_int, Z18_int;
303 
integer Z21_int, Z22_int, Z23_int, Z24_int, Z25_int, Z26_int, Z27_int, Z28_int;
304 
integer Z31_int, Z32_int, Z33_int, Z34_int, Z35_int, Z36_int, Z37_int, Z38_int;
305 
integer Z41_int, Z42_int, Z43_int, Z44_int, Z45_int, Z46_int, Z47_int, Z48_int;
306 
integer Z51_int, Z52_int, Z53_int, Z54_int, Z55_int, Z56_int, Z57_int, Z58_int;
307 
integer Z61_int, Z62_int, Z63_int, Z64_int, Z65_int, Z66_int, Z67_int, Z68_int;
308 
integer Z71_int, Z72_int, Z73_int, Z74_int, Z75_int, Z76_int, Z77_int, Z78_int;
309 
integer Z81_int, Z82_int, Z83_int, Z84_int, Z85_int, Z86_int, Z87_int, Z88_int;
310 
 
311 
always @(posedge clk)
312 
begin
313 
        if (rst) begin
314 
                Z11_int <= 0; Z12_int <= 0; Z13_int <= 0; Z14_int <= 0;
315 
                Z15_int <= 0; Z16_int <= 0; Z17_int <= 0; Z18_int <= 0;
316 
                Z21_int <= 0; Z22_int <= 0; Z23_int <= 0; Z24_int <= 0;
317 
                Z25_int <= 0; Z26_int <= 0; Z27_int <= 0; Z28_int <= 0;
318 
                Z31_int <= 0; Z32_int <= 0; Z33_int <= 0; Z34_int <= 0;
319 
                Z35_int <= 0; Z36_int <= 0; Z37_int <= 0; Z38_int <= 0;
320 
                Z41_int <= 0; Z42_int <= 0; Z43_int <= 0; Z44_int <= 0;
321 
                Z45_int <= 0; Z46_int <= 0; Z47_int <= 0; Z48_int <= 0;
322 
                Z51_int <= 0; Z52_int <= 0; Z53_int <= 0; Z54_int <= 0;
323 
                Z55_int <= 0; Z56_int <= 0; Z57_int <= 0; Z58_int <= 0;
324 
                Z61_int <= 0; Z62_int <= 0; Z63_int <= 0; Z64_int <= 0;
325 
                Z65_int <= 0; Z66_int <= 0; Z67_int <= 0; Z68_int <= 0;
326 
                Z71_int <= 0; Z72_int <= 0; Z73_int <= 0; Z74_int <= 0;
327 
                Z75_int <= 0; Z76_int <= 0; Z77_int <= 0; Z78_int <= 0;
328 
                Z81_int <= 0; Z82_int <= 0; Z83_int <= 0; Z84_int <= 0;
329 
                Z85_int <= 0; Z86_int <= 0; Z87_int <= 0; Z88_int <= 0;
330 
                end
331 
        else if (enable) begin
332 
                Z11_int[10:0] <= Z11; Z12_int[10:0] <= Z12; Z13_int[10:0] <= Z13; Z14_int[10:0] <= Z14;
333 
                Z15_int[10:0] <= Z15; Z16_int[10:0] <= Z16; Z17_int[10:0] <= Z17; Z18_int[10:0] <= Z18;
334 
                Z21_int[10:0] <= Z21; Z22_int[10:0] <= Z22; Z23_int[10:0] <= Z23; Z24_int[10:0] <= Z24;
335 
                Z25_int[10:0] <= Z25; Z26_int[10:0] <= Z26; Z27_int[10:0] <= Z27; Z28_int[10:0] <= Z28;
336 
                Z31_int[10:0] <= Z31; Z32_int[10:0] <= Z32; Z33_int[10:0] <= Z33; Z34_int[10:0] <= Z34;
337 
                Z35_int[10:0] <= Z35; Z36_int[10:0] <= Z36; Z37_int[10:0] <= Z37; Z38_int[10:0] <= Z38;
338 
                Z41_int[10:0] <= Z41; Z42_int[10:0] <= Z42; Z43_int[10:0] <= Z43; Z44_int[10:0] <= Z44;
339 
                Z45_int[10:0] <= Z45; Z46_int[10:0] <= Z46; Z47_int[10:0] <= Z47; Z48_int[10:0] <= Z48;
340 
                Z51_int[10:0] <= Z51; Z52_int[10:0] <= Z52; Z53_int[10:0] <= Z53; Z54_int[10:0] <= Z54;
341 
                Z55_int[10:0] <= Z55; Z56_int[10:0] <= Z56; Z57_int[10:0] <= Z57; Z58_int[10:0] <= Z58;
342 
                Z61_int[10:0] <= Z61; Z62_int[10:0] <= Z62; Z63_int[10:0] <= Z63; Z64_int[10:0] <= Z64;
343 
                Z65_int[10:0] <= Z65; Z66_int[10:0] <= Z66; Z67_int[10:0] <= Z67; Z68_int[10:0] <= Z68;
344 
                Z71_int[10:0] <= Z71; Z72_int[10:0] <= Z72; Z73_int[10:0] <= Z73; Z74_int[10:0] <= Z74;
345 
                Z75_int[10:0] <= Z75; Z76_int[10:0] <= Z76; Z77_int[10:0] <= Z77; Z78_int[10:0] <= Z78;
346 
                Z81_int[10:0] <= Z81; Z82_int[10:0] <= Z82; Z83_int[10:0] <= Z83; Z84_int[10:0] <= Z84;
347 
                Z85_int[10:0] <= Z85; Z86_int[10:0] <= Z86; Z87_int[10:0] <= Z87; Z88_int[10:0] <= Z88;
348 
                // sign extend to make Z11_int a twos complement representation of Z11
349 
                Z11_int[31:11] <= Z11[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
350 
                Z12_int[31:11] <= Z12[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
351 
                Z13_int[31:11] <= Z13[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
352 
                Z14_int[31:11] <= Z14[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
353 
                Z15_int[31:11] <= Z15[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
354 
                Z16_int[31:11] <= Z16[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
355 
                Z17_int[31:11] <= Z17[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
356 
                Z18_int[31:11] <= Z18[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
357 
                Z21_int[31:11] <= Z21[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
358 
                Z22_int[31:11] <= Z22[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
359 
                Z23_int[31:11] <= Z23[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
360 
                Z24_int[31:11] <= Z24[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
361 
                Z25_int[31:11] <= Z25[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
362 
                Z26_int[31:11] <= Z26[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
363 
                Z27_int[31:11] <= Z27[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
364 
                Z28_int[31:11] <= Z28[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
365 
                Z31_int[31:11] <= Z31[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
366 
                Z32_int[31:11] <= Z32[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
367 
                Z33_int[31:11] <= Z33[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
368 
                Z34_int[31:11] <= Z34[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
369 
                Z35_int[31:11] <= Z35[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
370 
                Z36_int[31:11] <= Z36[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
371 
                Z37_int[31:11] <= Z37[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
372 
                Z38_int[31:11] <= Z38[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
373 
                Z41_int[31:11] <= Z41[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
374 
                Z42_int[31:11] <= Z42[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
375 
                Z43_int[31:11] <= Z43[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
376 
                Z44_int[31:11] <= Z44[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
377 
                Z45_int[31:11] <= Z45[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
378 
                Z46_int[31:11] <= Z46[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
379 
                Z47_int[31:11] <= Z47[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
380 
                Z48_int[31:11] <= Z48[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
381 
                Z51_int[31:11] <= Z51[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
382 
                Z52_int[31:11] <= Z52[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
383 
                Z53_int[31:11] <= Z53[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
384 
                Z54_int[31:11] <= Z54[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
385 
                Z55_int[31:11] <= Z55[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
386 
                Z56_int[31:11] <= Z56[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
387 
                Z57_int[31:11] <= Z57[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
388 
                Z58_int[31:11] <= Z58[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
389 
                Z61_int[31:11] <= Z61[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
390 
                Z62_int[31:11] <= Z62[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
391 
                Z63_int[31:11] <= Z63[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
392 
                Z64_int[31:11] <= Z64[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
393 
                Z65_int[31:11] <= Z65[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
394 
                Z66_int[31:11] <= Z66[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
395 
                Z67_int[31:11] <= Z67[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
396 
                Z68_int[31:11] <= Z68[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
397 
                Z71_int[31:11] <= Z71[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
398 
                Z72_int[31:11] <= Z72[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
399 
                Z73_int[31:11] <= Z73[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
400 
                Z74_int[31:11] <= Z74[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
401 
                Z75_int[31:11] <= Z75[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
402 
                Z76_int[31:11] <= Z76[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
403 
                Z77_int[31:11] <= Z77[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
404 
                Z78_int[31:11] <= Z78[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
405 
                Z81_int[31:11] <= Z81[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
406 
                Z82_int[31:11] <= Z82[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
407 
                Z83_int[31:11] <= Z83[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
408 
                Z84_int[31:11] <= Z84[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
409 
                Z85_int[31:11] <= Z85[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
410 
                Z86_int[31:11] <= Z86[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
411 
                Z87_int[31:11] <= Z87[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
412 
                Z88_int[31:11] <= Z88[10] ? 21'b111111111111111111111 : 21'b000000000000000000000;
413 
                end
414 
end
415 
 
416 
always @(posedge clk)
417 
begin
418 
        if (rst) begin
419 
                Z11_temp <= 0; Z12_temp <= 0; Z13_temp <= 0; Z14_temp <= 0;
420 
                Z12_temp <= 0; Z16_temp <= 0; Z17_temp <= 0; Z18_temp <= 0;
421 
                Z21_temp <= 0; Z22_temp <= 0; Z23_temp <= 0; Z24_temp <= 0;
422 
                Z22_temp <= 0; Z26_temp <= 0; Z27_temp <= 0; Z28_temp <= 0;
423 
                Z31_temp <= 0; Z32_temp <= 0; Z33_temp <= 0; Z34_temp <= 0;
424 
                Z32_temp <= 0; Z36_temp <= 0; Z37_temp <= 0; Z38_temp <= 0;
425 
                Z41_temp <= 0; Z42_temp <= 0; Z43_temp <= 0; Z44_temp <= 0;
426 
                Z42_temp <= 0; Z46_temp <= 0; Z47_temp <= 0; Z48_temp <= 0;
427 
                Z51_temp <= 0; Z52_temp <= 0; Z53_temp <= 0; Z54_temp <= 0;
428 
                Z52_temp <= 0; Z56_temp <= 0; Z57_temp <= 0; Z58_temp <= 0;
429 
                Z61_temp <= 0; Z62_temp <= 0; Z63_temp <= 0; Z64_temp <= 0;
430 
                Z62_temp <= 0; Z66_temp <= 0; Z67_temp <= 0; Z68_temp <= 0;
431 
                Z71_temp <= 0; Z72_temp <= 0; Z73_temp <= 0; Z74_temp <= 0;
432 
                Z72_temp <= 0; Z76_temp <= 0; Z77_temp <= 0; Z78_temp <= 0;
433 
                Z81_temp <= 0; Z82_temp <= 0; Z83_temp <= 0; Z84_temp <= 0;
434 
                Z82_temp <= 0; Z86_temp <= 0; Z87_temp <= 0; Z88_temp <= 0;
435 
                end
436 
        else if (enable_1) begin
437 
                Z11_temp <= Z11_int * QM1_1; Z12_temp <= Z12_int * QM1_2;
438 
                Z13_temp <= Z13_int * QM1_3; Z14_temp <= Z14_int * QM1_4;
439 
                Z15_temp <= Z15_int * QM1_5; Z16_temp <= Z16_int * QM1_6;
440 
                Z17_temp <= Z17_int * QM1_7; Z18_temp <= Z18_int * QM1_8;
441 
                Z21_temp <= Z21_int * QM2_1; Z22_temp <= Z22_int * QM2_2;
442 
                Z23_temp <= Z23_int * QM2_3; Z24_temp <= Z24_int * QM2_4;
443 
                Z25_temp <= Z25_int * QM2_5; Z26_temp <= Z26_int * QM2_6;
444 
                Z27_temp <= Z27_int * QM2_7; Z28_temp <= Z28_int * QM2_8;
445 
                Z31_temp <= Z31_int * QM3_1; Z32_temp <= Z32_int * QM3_2;
446 
                Z33_temp <= Z33_int * QM3_3; Z34_temp <= Z34_int * QM3_4;
447 
                Z35_temp <= Z35_int * QM3_5; Z36_temp <= Z36_int * QM3_6;
448 
                Z37_temp <= Z37_int * QM3_7; Z38_temp <= Z38_int * QM3_8;
449 
                Z41_temp <= Z41_int * QM4_1; Z42_temp <= Z42_int * QM4_2;
450 
                Z43_temp <= Z43_int * QM4_3; Z44_temp <= Z44_int * QM4_4;
451 
                Z45_temp <= Z45_int * QM4_5; Z46_temp <= Z46_int * QM4_6;
452 
                Z47_temp <= Z47_int * QM4_7; Z48_temp <= Z48_int * QM4_8;
453 
                Z51_temp <= Z51_int * QM5_1; Z52_temp <= Z52_int * QM5_2;
454 
                Z53_temp <= Z53_int * QM5_3; Z54_temp <= Z54_int * QM5_4;
455 
                Z55_temp <= Z55_int * QM5_5; Z56_temp <= Z56_int * QM5_6;
456 
                Z57_temp <= Z57_int * QM5_7; Z58_temp <= Z58_int * QM5_8;
457 
                Z61_temp <= Z61_int * QM6_1; Z62_temp <= Z62_int * QM6_2;
458 
                Z63_temp <= Z63_int * QM6_3; Z64_temp <= Z64_int * QM6_4;
459 
                Z65_temp <= Z65_int * QM6_5; Z66_temp <= Z66_int * QM6_6;
460 
                Z67_temp <= Z67_int * QM6_7; Z68_temp <= Z68_int * QM6_8;
461 
                Z71_temp <= Z71_int * QM7_1; Z72_temp <= Z72_int * QM7_2;
462 
                Z73_temp <= Z73_int * QM7_3; Z74_temp <= Z74_int * QM7_4;
463 
                Z75_temp <= Z75_int * QM7_5; Z76_temp <= Z76_int * QM7_6;
464 
                Z77_temp <= Z77_int * QM7_7; Z78_temp <= Z78_int * QM7_8;
465 
                Z81_temp <= Z81_int * QM8_1; Z82_temp <= Z82_int * QM8_2;
466 
                Z83_temp <= Z83_int * QM8_3; Z84_temp <= Z84_int * QM8_4;
467 
                Z85_temp <= Z85_int * QM8_5; Z86_temp <= Z86_int * QM8_6;
468 
                Z87_temp <= Z87_int * QM8_7; Z88_temp <= Z88_int * QM8_8;
469 
                end
470 
end
471 
 
472 
 
473 
always @(posedge clk)
474 
begin
475 
        if (rst) begin
476 
                Z11_temp_1 <= 0; Z12_temp_1 <= 0; Z13_temp_1 <= 0; Z14_temp_1 <= 0;
477 
                Z12_temp_1 <= 0; Z16_temp_1 <= 0; Z17_temp_1 <= 0; Z18_temp_1 <= 0;
478 
                Z21_temp_1 <= 0; Z22_temp_1 <= 0; Z23_temp_1 <= 0; Z24_temp_1 <= 0;
479 
                Z22_temp_1 <= 0; Z26_temp_1 <= 0; Z27_temp_1 <= 0; Z28_temp_1 <= 0;
480 
                Z31_temp_1 <= 0; Z32_temp_1 <= 0; Z33_temp_1 <= 0; Z34_temp_1 <= 0;
481 
                Z32_temp_1 <= 0; Z36_temp_1 <= 0; Z37_temp_1 <= 0; Z38_temp_1 <= 0;
482 
                Z41_temp_1 <= 0; Z42_temp_1 <= 0; Z43_temp_1 <= 0; Z44_temp_1 <= 0;
483 
                Z42_temp_1 <= 0; Z46_temp_1 <= 0; Z47_temp_1 <= 0; Z48_temp_1 <= 0;
484 
                Z51_temp_1 <= 0; Z52_temp_1 <= 0; Z53_temp_1 <= 0; Z54_temp_1 <= 0;
485 
                Z52_temp_1 <= 0; Z56_temp_1 <= 0; Z57_temp_1 <= 0; Z58_temp_1 <= 0;
486 
                Z61_temp_1 <= 0; Z62_temp_1 <= 0; Z63_temp_1 <= 0; Z64_temp_1 <= 0;
487 
                Z62_temp_1 <= 0; Z66_temp_1 <= 0; Z67_temp_1 <= 0; Z68_temp_1 <= 0;
488 
                Z71_temp_1 <= 0; Z72_temp_1 <= 0; Z73_temp_1 <= 0; Z74_temp_1 <= 0;
489 
                Z72_temp_1 <= 0; Z76_temp_1 <= 0; Z77_temp_1 <= 0; Z78_temp_1 <= 0;
490 
                Z81_temp_1 <= 0; Z82_temp_1 <= 0; Z83_temp_1 <= 0; Z84_temp_1 <= 0;
491 
                Z82_temp_1 <= 0; Z86_temp_1 <= 0; Z87_temp_1 <= 0; Z88_temp_1 <= 0;
492 
                end
493 
        else if (enable_2) begin
494 
                Z11_temp_1 <= Z11_temp; Z12_temp_1 <= Z12_temp;
495 
                Z13_temp_1 <= Z13_temp; Z14_temp_1 <= Z14_temp;
496 
                Z15_temp_1 <= Z15_temp; Z16_temp_1 <= Z16_temp;
497 
                Z17_temp_1 <= Z17_temp; Z18_temp_1 <= Z18_temp;
498 
                Z21_temp_1 <= Z21_temp; Z22_temp_1 <= Z22_temp;
499 
                Z23_temp_1 <= Z23_temp; Z24_temp_1 <= Z24_temp;
500 
                Z25_temp_1 <= Z25_temp; Z26_temp_1 <= Z26_temp;
501 
                Z27_temp_1 <= Z27_temp; Z28_temp_1 <= Z28_temp;
502 
                Z31_temp_1 <= Z31_temp; Z32_temp_1 <= Z32_temp;
503 
                Z33_temp_1 <= Z33_temp; Z34_temp_1 <= Z34_temp;
504 
                Z35_temp_1 <= Z35_temp; Z36_temp_1 <= Z36_temp;
505 
                Z37_temp_1 <= Z37_temp; Z38_temp_1 <= Z38_temp;
506 
                Z41_temp_1 <= Z41_temp; Z42_temp_1 <= Z42_temp;
507 
                Z43_temp_1 <= Z43_temp; Z44_temp_1 <= Z44_temp;
508 
                Z45_temp_1 <= Z45_temp; Z46_temp_1 <= Z46_temp;
509 
                Z47_temp_1 <= Z47_temp; Z48_temp_1 <= Z48_temp;
510 
                Z51_temp_1 <= Z51_temp; Z52_temp_1 <= Z52_temp;
511 
                Z53_temp_1 <= Z53_temp; Z54_temp_1 <= Z54_temp;
512 
                Z55_temp_1 <= Z55_temp; Z56_temp_1 <= Z56_temp;
513 
                Z57_temp_1 <= Z57_temp; Z58_temp_1 <= Z58_temp;
514 
                Z61_temp_1 <= Z61_temp; Z62_temp_1 <= Z62_temp;
515 
                Z63_temp_1 <= Z63_temp; Z64_temp_1 <= Z64_temp;
516 
                Z65_temp_1 <= Z65_temp; Z66_temp_1 <= Z66_temp;
517 
                Z67_temp_1 <= Z67_temp; Z68_temp_1 <= Z68_temp;
518 
                Z71_temp_1 <= Z71_temp; Z72_temp_1 <= Z72_temp;
519 
                Z73_temp_1 <= Z73_temp; Z74_temp_1 <= Z74_temp;
520 
                Z75_temp_1 <= Z75_temp; Z76_temp_1 <= Z76_temp;
521 
                Z77_temp_1 <= Z77_temp; Z78_temp_1 <= Z78_temp;
522 
                Z81_temp_1 <= Z81_temp; Z82_temp_1 <= Z82_temp;
523 
                Z83_temp_1 <= Z83_temp; Z84_temp_1 <= Z84_temp;
524 
                Z85_temp_1 <= Z85_temp; Z86_temp_1 <= Z86_temp;
525 
                Z87_temp_1 <= Z87_temp; Z88_temp_1 <= Z88_temp;
526 
                end
527 
end
528 
 
529 
always @(posedge clk)
530 
begin
531 
        if (rst) begin
532 
                Q11 <= 0; Q12 <= 0; Q13 <= 0; Q14 <= 0; Q15 <= 0; Q16 <= 0; Q17 <= 0; Q18 <= 0;
533 
                Q21 <= 0; Q22 <= 0; Q23 <= 0; Q24 <= 0; Q25 <= 0; Q26 <= 0; Q27 <= 0; Q28 <= 0;
534 
                Q31 <= 0; Q32 <= 0; Q33 <= 0; Q34 <= 0; Q35 <= 0; Q36 <= 0; Q37 <= 0; Q38 <= 0;
535 
                Q41 <= 0; Q42 <= 0; Q43 <= 0; Q44 <= 0; Q45 <= 0; Q46 <= 0; Q47 <= 0; Q48 <= 0;
536 
                Q51 <= 0; Q52 <= 0; Q53 <= 0; Q54 <= 0; Q55 <= 0; Q56 <= 0; Q57 <= 0; Q58 <= 0;
537 
                Q61 <= 0; Q62 <= 0; Q63 <= 0; Q64 <= 0; Q65 <= 0; Q66 <= 0; Q67 <= 0; Q68 <= 0;
538 
                Q71 <= 0; Q72 <= 0; Q73 <= 0; Q74 <= 0; Q75 <= 0; Q76 <= 0; Q77 <= 0; Q78 <= 0;
539 
                Q81 <= 0; Q82 <= 0; Q83 <= 0; Q84 <= 0; Q85 <= 0; Q86 <= 0; Q87 <= 0; Q88 <= 0;
540 
                end
541 
        else if (enable_3) begin
542 
                // rounding Q11 based on the bit in the 11th place of Z11_temp
543 
                Q11 <= Z11_temp_1[11] ? Z11_temp_1[22:12] + 1 : Z11_temp_1[22:12];
544 
                Q12 <= Z12_temp_1[11] ? Z12_temp_1[22:12] + 1 : Z12_temp_1[22:12];
545 
                Q13 <= Z13_temp_1[11] ? Z13_temp_1[22:12] + 1 : Z13_temp_1[22:12];
546 
                Q14 <= Z14_temp_1[11] ? Z14_temp_1[22:12] + 1 : Z14_temp_1[22:12];
547 
                Q15 <= Z15_temp_1[11] ? Z15_temp_1[22:12] + 1 : Z15_temp_1[22:12];
548 
                Q16 <= Z16_temp_1[11] ? Z16_temp_1[22:12] + 1 : Z16_temp_1[22:12];
549 
                Q17 <= Z17_temp_1[11] ? Z17_temp_1[22:12] + 1 : Z17_temp_1[22:12];
550 
                Q18 <= Z18_temp_1[11] ? Z18_temp_1[22:12] + 1 : Z18_temp_1[22:12];
551 
                Q21 <= Z21_temp_1[11] ? Z21_temp_1[22:12] + 1 : Z21_temp_1[22:12];
552 
                Q22 <= Z22_temp_1[11] ? Z22_temp_1[22:12] + 1 : Z22_temp_1[22:12];
553 
                Q23 <= Z23_temp_1[11] ? Z23_temp_1[22:12] + 1 : Z23_temp_1[22:12];
554 
                Q24 <= Z24_temp_1[11] ? Z24_temp_1[22:12] + 1 : Z24_temp_1[22:12];
555 
                Q25 <= Z25_temp_1[11] ? Z25_temp_1[22:12] + 1 : Z25_temp_1[22:12];
556 
                Q26 <= Z26_temp_1[11] ? Z26_temp_1[22:12] + 1 : Z26_temp_1[22:12];
557 
                Q27 <= Z27_temp_1[11] ? Z27_temp_1[22:12] + 1 : Z27_temp_1[22:12];
558 
                Q28 <= Z28_temp_1[11] ? Z28_temp_1[22:12] + 1 : Z28_temp_1[22:12];
559 
                Q31 <= Z31_temp_1[11] ? Z31_temp_1[22:12] + 1 : Z31_temp_1[22:12];
560 
                Q32 <= Z32_temp_1[11] ? Z32_temp_1[22:12] + 1 : Z32_temp_1[22:12];
561 
                Q33 <= Z33_temp_1[11] ? Z33_temp_1[22:12] + 1 : Z33_temp_1[22:12];
562 
                Q34 <= Z34_temp_1[11] ? Z34_temp_1[22:12] + 1 : Z34_temp_1[22:12];
563 
                Q35 <= Z35_temp_1[11] ? Z35_temp_1[22:12] + 1 : Z35_temp_1[22:12];
564 
                Q36 <= Z36_temp_1[11] ? Z36_temp_1[22:12] + 1 : Z36_temp_1[22:12];
565 
                Q37 <= Z37_temp_1[11] ? Z37_temp_1[22:12] + 1 : Z37_temp_1[22:12];
566 
                Q38 <= Z38_temp_1[11] ? Z38_temp_1[22:12] + 1 : Z38_temp_1[22:12];
567 
                Q41 <= Z41_temp_1[11] ? Z41_temp_1[22:12] + 1 : Z41_temp_1[22:12];
568 
                Q42 <= Z42_temp_1[11] ? Z42_temp_1[22:12] + 1 : Z42_temp_1[22:12];
569 
                Q43 <= Z43_temp_1[11] ? Z43_temp_1[22:12] + 1 : Z43_temp_1[22:12];
570 
                Q44 <= Z44_temp_1[11] ? Z44_temp_1[22:12] + 1 : Z44_temp_1[22:12];
571 
                Q45 <= Z45_temp_1[11] ? Z45_temp_1[22:12] + 1 : Z45_temp_1[22:12];
572 
                Q46 <= Z46_temp_1[11] ? Z46_temp_1[22:12] + 1 : Z46_temp_1[22:12];
573 
                Q47 <= Z47_temp_1[11] ? Z47_temp_1[22:12] + 1 : Z47_temp_1[22:12];
574 
                Q48 <= Z48_temp_1[11] ? Z48_temp_1[22:12] + 1 : Z48_temp_1[22:12];
575 
                Q51 <= Z51_temp_1[11] ? Z51_temp_1[22:12] + 1 : Z51_temp_1[22:12];
576 
                Q52 <= Z52_temp_1[11] ? Z52_temp_1[22:12] + 1 : Z52_temp_1[22:12];
577 
                Q53 <= Z53_temp_1[11] ? Z53_temp_1[22:12] + 1 : Z53_temp_1[22:12];
578 
                Q54 <= Z54_temp_1[11] ? Z54_temp_1[22:12] + 1 : Z54_temp_1[22:12];
579 
                Q55 <= Z55_temp_1[11] ? Z55_temp_1[22:12] + 1 : Z55_temp_1[22:12];
580 
                Q56 <= Z56_temp_1[11] ? Z56_temp_1[22:12] + 1 : Z56_temp_1[22:12];
581 
                Q57 <= Z57_temp_1[11] ? Z57_temp_1[22:12] + 1 : Z57_temp_1[22:12];
582 
                Q58 <= Z58_temp_1[11] ? Z58_temp_1[22:12] + 1 : Z58_temp_1[22:12];
583 
                Q61 <= Z61_temp_1[11] ? Z61_temp_1[22:12] + 1 : Z61_temp_1[22:12];
584 
                Q62 <= Z62_temp_1[11] ? Z62_temp_1[22:12] + 1 : Z62_temp_1[22:12];
585 
                Q63 <= Z63_temp_1[11] ? Z63_temp_1[22:12] + 1 : Z63_temp_1[22:12];
586 
                Q64 <= Z64_temp_1[11] ? Z64_temp_1[22:12] + 1 : Z64_temp_1[22:12];
587 
                Q65 <= Z65_temp_1[11] ? Z65_temp_1[22:12] + 1 : Z65_temp_1[22:12];
588 
                Q66 <= Z66_temp_1[11] ? Z66_temp_1[22:12] + 1 : Z66_temp_1[22:12];
589 
                Q67 <= Z67_temp_1[11] ? Z67_temp_1[22:12] + 1 : Z67_temp_1[22:12];
590 
                Q68 <= Z68_temp_1[11] ? Z68_temp_1[22:12] + 1 : Z68_temp_1[22:12];
591 
                Q71 <= Z71_temp_1[11] ? Z71_temp_1[22:12] + 1 : Z71_temp_1[22:12];
592 
                Q72 <= Z72_temp_1[11] ? Z72_temp_1[22:12] + 1 : Z72_temp_1[22:12];
593 
                Q73 <= Z73_temp_1[11] ? Z73_temp_1[22:12] + 1 : Z73_temp_1[22:12];
594 
                Q74 <= Z74_temp_1[11] ? Z74_temp_1[22:12] + 1 : Z74_temp_1[22:12];
595 
                Q75 <= Z75_temp_1[11] ? Z75_temp_1[22:12] + 1 : Z75_temp_1[22:12];
596 
                Q76 <= Z76_temp_1[11] ? Z76_temp_1[22:12] + 1 : Z76_temp_1[22:12];
597 
                Q77 <= Z77_temp_1[11] ? Z77_temp_1[22:12] + 1 : Z77_temp_1[22:12];
598 
                Q78 <= Z78_temp_1[11] ? Z78_temp_1[22:12] + 1 : Z78_temp_1[22:12];
599 
                Q81 <= Z81_temp_1[11] ? Z81_temp_1[22:12] + 1 : Z81_temp_1[22:12];
600 
                Q82 <= Z82_temp_1[11] ? Z82_temp_1[22:12] + 1 : Z82_temp_1[22:12];
601 
                Q83 <= Z83_temp_1[11] ? Z83_temp_1[22:12] + 1 : Z83_temp_1[22:12];
602 
                Q84 <= Z84_temp_1[11] ? Z84_temp_1[22:12] + 1 : Z84_temp_1[22:12];
603 
                Q85 <= Z85_temp_1[11] ? Z85_temp_1[22:12] + 1 : Z85_temp_1[22:12];
604 
                Q86 <= Z86_temp_1[11] ? Z86_temp_1[22:12] + 1 : Z86_temp_1[22:12];
605 
                Q87 <= Z87_temp_1[11] ? Z87_temp_1[22:12] + 1 : Z87_temp_1[22:12];
606 
                Q88 <= Z88_temp_1[11] ? Z88_temp_1[22:12] + 1 : Z88_temp_1[22:12];
607 
                end
608 
end
609 
 
610 
 
611 
/* enable_1 is delayed one clock cycle from enable, and it's used to
612 
enable the logic that needs to execute on the clock cycle after enable goes high
613 
enable_2 is delayed two clock cycles, and out_enable signals the next module
614 
that its input data is ready*/
615 
 
616 
always @(posedge clk)
617 
begin
618 
        if (rst) begin
619 
                enable_1 <= 0; enable_2 <= 0; enable_3 <= 0;
620 
                out_enable <= 0;
621 
                end
622 
        else begin
623 
                enable_1 <= enable; enable_2 <= enable_1;
624 
                enable_3 <= enable_2;
625 
                out_enable <= enable_3;
626 
                end
627 
end
628 
 
629 
endmodule

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