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davidklun |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// JPEG Encoder Core - Verilog ////
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//// ////
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//// Author: David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/* This module takes the y, cb, and cr inputs from the pre_fifo module,
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and it combines the bits into the jpeg_bitstream. It uses 3 FIFO's to
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write the y, cb, and cr data while it's processing the data. The output
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of this module goes to the input of the ff_checker module, to check for
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any FF's in the bitstream.
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*/
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`timescale 1ns / 100ps
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module fifo_out(clk, rst, enable, data_in, JPEG_bitstream, data_ready, orc_reg);
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input clk, rst, enable;
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input [23:0] data_in;
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output [31:0] JPEG_bitstream;
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output data_ready;
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output [4:0] orc_reg;
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wire [31:0] cb_JPEG_bitstream, cr_JPEG_bitstream, y_JPEG_bitstream;
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wire [4:0] cr_orc, cb_orc, y_orc;
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wire [31:0] cr_bits_out, cb_bits_out, y_bits_out;
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wire cr_out_enable, cb_out_enable, y_out_enable;
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wire cb_data_ready, cr_data_ready, y_data_ready;
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wire end_of_block_output, y_eob_empty;
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wire cb_eob_empty, cr_eob_empty;
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wire cb_fifo_empty, cr_fifo_empty, y_fifo_empty;
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reg [4:0] orc, orc_reg, orc_cb, orc_cr, old_orc_reg, sorc_reg, roll_orc_reg;
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reg [4:0] orc_1, orc_2, orc_3, orc_4, orc_5, orc_reg_delay;
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reg [4:0] static_orc_1, static_orc_2, static_orc_3, static_orc_4, static_orc_5;
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reg [4:0] static_orc_6;
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reg [4:0] edge_ro_1, edge_ro_2, edge_ro_3, edge_ro_4, edge_ro_5;
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reg [31:0] jpeg_ro_1, jpeg_ro_2, jpeg_ro_3, jpeg_ro_4, jpeg_ro_5, jpeg_delay;
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reg [31:0] jpeg, jpeg_1, jpeg_2, jpeg_3, jpeg_4, jpeg_5, jpeg_6, JPEG_bitstream;
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reg [4:0] cr_orc_1, cb_orc_1, y_orc_1;
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reg cr_out_enable_1, cb_out_enable_1, y_out_enable_1, eob_1;
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reg eob_2, eob_3, eob_4;
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reg enable_1, enable_2, enable_3, enable_4, enable_5;
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reg enable_6, enable_7, enable_8, enable_9, enable_10;
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reg enable_11, enable_12, enable_13, enable_14, enable_15;
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reg enable_16, enable_17, enable_18, enable_19, enable_20;
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reg enable_21, enable_22, enable_23, enable_24, enable_25;
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reg enable_26, enable_27, enable_28, enable_29, enable_30;
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reg enable_31, enable_32, enable_33, enable_34, enable_35;
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reg [2:0] bits_mux, old_orc_mux, read_mux;
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reg bits_ready, br_1, br_2, br_3, br_4, br_5, br_6, br_7, br_8;
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reg rollover, rollover_1, rollover_2, rollover_3, rollover_eob;
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reg rollover_4, rollover_5, rollover_6, rollover_7;
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reg data_ready, eobe_1, cb_read_req, cr_read_req, y_read_req;
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reg eob_early_out_enable;
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wire cb_write_enable = cb_data_ready && !cb_eob_empty;
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wire cr_write_enable = cr_data_ready && !cr_eob_empty;
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wire y_write_enable = y_data_ready && !y_eob_empty;
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pre_fifo u14(.clk(clk), .rst(rst), .enable(enable), .data_in(data_in),
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.cr_JPEG_bitstream(cr_JPEG_bitstream), .cr_data_ready(cr_data_ready),
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.cr_orc(cr_orc), .cb_JPEG_bitstream(cb_JPEG_bitstream),
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.cb_data_ready(cb_data_ready), .cb_orc(cb_orc),
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.y_JPEG_bitstream(y_JPEG_bitstream), .y_data_ready(y_data_ready), .y_orc(y_orc),
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.y_eob_output(end_of_block_output), .y_eob_empty(y_eob_empty),
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.cb_eob_empty(cb_eob_empty), .cr_eob_empty(cr_eob_empty));
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sync_fifo_32 u15(.clk(clk), .rst(rst), .read_req(cb_read_req),
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.write_data(cb_JPEG_bitstream), .write_enable(cb_write_enable),
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.read_data(cb_bits_out),
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.fifo_empty(cb_fifo_empty), .rdata_valid(cb_out_enable));
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sync_fifo_32 u16(.clk(clk), .rst(rst), .read_req(cr_read_req),
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.write_data(cr_JPEG_bitstream), .write_enable(cr_write_enable),
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.read_data(cr_bits_out),
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.fifo_empty(cr_fifo_empty), .rdata_valid(cr_out_enable));
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sync_fifo_32 u17(.clk(clk), .rst(rst), .read_req(y_read_req),
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.write_data(y_JPEG_bitstream), .write_enable(y_write_enable),
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.read_data(y_bits_out),
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.fifo_empty(y_fifo_empty), .rdata_valid(y_out_enable));
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always @(posedge clk)
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begin
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if (y_fifo_empty || read_mux != 3'b001)
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y_read_req <= 0;
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else if (!y_fifo_empty && read_mux == 3'b001)
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y_read_req <= 1;
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end
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always @(posedge clk)
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begin
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if (cb_fifo_empty || read_mux != 3'b010)
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cb_read_req <= 0;
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else if (!cb_fifo_empty && read_mux == 3'b010)
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cb_read_req <= 1;
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end
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always @(posedge clk)
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begin
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if (cr_fifo_empty || read_mux != 3'b100)
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cr_read_req <= 0;
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else if (!cr_fifo_empty && read_mux == 3'b100)
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cr_read_req <= 1;
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end
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always @(posedge clk)
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begin
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if (rst) begin
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br_1 <= 0; br_2 <= 0; br_3 <= 0; br_4 <= 0; br_5 <= 0; br_6 <= 0;
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br_7 <= 0; br_8 <= 0;
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static_orc_1 <= 0; static_orc_2 <= 0; static_orc_3 <= 0;
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static_orc_4 <= 0; static_orc_5 <= 0; static_orc_6 <= 0;
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data_ready <= 0; eobe_1 <= 0;
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end
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else begin
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br_1 <= bits_ready & !eobe_1; br_2 <= br_1; br_3 <= br_2;
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br_4 <= br_3; br_5 <= br_4; br_6 <= br_5;
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br_7 <= br_6; br_8 <= br_7;
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static_orc_1 <= sorc_reg; static_orc_2 <= static_orc_1;
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static_orc_3 <= static_orc_2; static_orc_4 <= static_orc_3;
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static_orc_5 <= static_orc_4; static_orc_6 <= static_orc_5;
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data_ready <= br_6 & rollover_5;
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eobe_1 <= y_eob_empty;
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end
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end
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always @(posedge clk)
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begin
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if (rst)
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rollover_eob <= 0;
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else if (br_3)
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rollover_eob <= old_orc_reg >= roll_orc_reg;
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end
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always @(posedge clk)
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begin
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if (rst) begin
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rollover_1 <= 0; rollover_2 <= 0; rollover_3 <= 0;
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rollover_4 <= 0; rollover_5 <= 0; rollover_6 <= 0;
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rollover_7 <= 0; eob_1 <= 0; eob_2 <= 0;
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eob_3 <= 0; eob_4 <= 0;
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eob_early_out_enable <= 0;
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end
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else begin
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rollover_1 <= rollover; rollover_2 <= rollover_1;
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rollover_3 <= rollover_2;
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rollover_4 <= rollover_3 | rollover_eob;
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rollover_5 <= rollover_4; rollover_6 <= rollover_5;
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rollover_7 <= rollover_6; eob_1 <= end_of_block_output;
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eob_2 <= eob_1; eob_3 <= eob_2; eob_4 <= eob_3;
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eob_early_out_enable <= y_out_enable & y_out_enable_1 & eob_2;
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end
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end
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always @(posedge clk)
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begin
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case (bits_mux)
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3'b001: rollover <= y_out_enable_1 & !eob_4 & !eob_early_out_enable;
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3'b010: rollover <= cb_out_enable_1 & cb_out_enable;
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3'b100: rollover <= cr_out_enable_1 & cr_out_enable;
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default: rollover <= y_out_enable_1 & !eob_4;
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endcase
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end
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always @(posedge clk)
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begin
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if (rst)
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orc <= 0;
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else if (enable_20)
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orc <= orc_cr + cr_orc_1;
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end
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always @(posedge clk)
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begin
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if (rst)
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orc_cb <= 0;
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else if (eob_1)
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orc_cb <= orc + y_orc_1;
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end
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always @(posedge clk)
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begin
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if (rst)
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orc_cr <= 0;
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else if (enable_5)
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orc_cr <= orc_cb + cb_orc_1;
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end
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always @(posedge clk)
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begin
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if (rst) begin
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cr_out_enable_1 <= 0; cb_out_enable_1 <= 0; y_out_enable_1 <= 0;
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end
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else begin
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cr_out_enable_1 <= cr_out_enable;
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cb_out_enable_1 <= cb_out_enable;
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y_out_enable_1 <= y_out_enable;
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end
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end
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always @(posedge clk)
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begin
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case (bits_mux)
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3'b001: jpeg <= y_bits_out;
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3'b010: jpeg <= cb_bits_out;
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3'b100: jpeg <= cr_bits_out;
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default: jpeg <= y_bits_out;
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endcase
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end
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always @(posedge clk)
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begin
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case (bits_mux)
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3'b001: bits_ready <= y_out_enable;
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3'b010: bits_ready <= cb_out_enable;
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3'b100: bits_ready <= cr_out_enable;
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default: bits_ready <= y_out_enable;
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endcase
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end
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always @(posedge clk)
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begin
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case (bits_mux)
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3'b001: sorc_reg <= orc;
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3'b010: sorc_reg <= orc_cb;
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3'b100: sorc_reg <= orc_cr;
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default: sorc_reg <= orc;
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endcase
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end
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always @(posedge clk)
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begin
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case (old_orc_mux)
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3'b001: roll_orc_reg <= orc;
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3'b010: roll_orc_reg <= orc_cb;
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3'b100: roll_orc_reg <= orc_cr;
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default: roll_orc_reg <= orc;
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endcase
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end
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always @(posedge clk)
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begin
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case (bits_mux)
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3'b001: orc_reg <= orc;
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3'b010: orc_reg <= orc_cb;
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3'b100: orc_reg <= orc_cr;
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default: orc_reg <= orc;
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endcase
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end
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always @(posedge clk)
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begin
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case (old_orc_mux)
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3'b001: old_orc_reg <= orc_cr;
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3'b010: old_orc_reg <= orc;
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3'b100: old_orc_reg <= orc_cb;
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default: old_orc_reg <= orc_cr;
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endcase
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end
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always @(posedge clk)
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begin
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if (rst)
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bits_mux <= 3'b001; // Y
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else if (enable_3)
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bits_mux <= 3'b010; // Cb
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else if (enable_19)
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bits_mux <= 3'b100; // Cr
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else if (enable_35)
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bits_mux <= 3'b001; // Y
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end
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always @(posedge clk)
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begin
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if (rst)
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old_orc_mux <= 3'b001; // Y
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else if (enable_1)
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old_orc_mux <= 3'b010; // Cb
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else if (enable_6)
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old_orc_mux <= 3'b100; // Cr
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else if (enable_22)
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old_orc_mux <= 3'b001; // Y
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end
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309 |
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310 |
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always @(posedge clk)
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311 |
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begin
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312 |
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if (rst)
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read_mux <= 3'b001; // Y
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314 |
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else if (enable_1)
|
315 |
|
|
read_mux <= 3'b010; // Cb
|
316 |
|
|
else if (enable_17)
|
317 |
|
|
read_mux <= 3'b100; // Cr
|
318 |
|
|
else if (enable_33)
|
319 |
|
|
read_mux <= 3'b001; // Y
|
320 |
|
|
end
|
321 |
|
|
|
322 |
|
|
always @(posedge clk)
|
323 |
|
|
begin
|
324 |
|
|
if (rst) begin
|
325 |
|
|
cr_orc_1 <= 0; cb_orc_1 <= 0; y_orc_1 <= 0;
|
326 |
|
|
end
|
327 |
|
|
else if (end_of_block_output) begin
|
328 |
|
|
cr_orc_1 <= cr_orc;
|
329 |
|
|
cb_orc_1 <= cb_orc;
|
330 |
|
|
y_orc_1 <= y_orc;
|
331 |
|
|
end
|
332 |
|
|
end
|
333 |
|
|
|
334 |
|
|
|
335 |
|
|
always @(posedge clk)
|
336 |
|
|
begin
|
337 |
|
|
if (rst) begin
|
338 |
|
|
jpeg_ro_5 <= 0; edge_ro_5 <= 0;
|
339 |
|
|
end
|
340 |
|
|
else if (br_5) begin
|
341 |
|
|
jpeg_ro_5 <= (edge_ro_4 <= 1) ? jpeg_ro_4 << 1 : jpeg_ro_4;
|
342 |
|
|
edge_ro_5 <= (edge_ro_4 <= 1) ? edge_ro_4 : edge_ro_4 - 1;
|
343 |
|
|
end
|
344 |
|
|
end
|
345 |
|
|
|
346 |
|
|
always @(posedge clk)
|
347 |
|
|
begin
|
348 |
|
|
if (rst) begin
|
349 |
|
|
jpeg_5 <= 0; orc_5 <= 0; jpeg_ro_4 <= 0; edge_ro_4 <= 0;
|
350 |
|
|
end
|
351 |
|
|
else if (br_4) begin
|
352 |
|
|
jpeg_5 <= (orc_4 >= 1) ? jpeg_4 >> 1 : jpeg_4;
|
353 |
|
|
orc_5 <= (orc_4 >= 1) ? orc_4 - 1 : orc_4;
|
354 |
|
|
jpeg_ro_4 <= (edge_ro_3 <= 2) ? jpeg_ro_3 << 2 : jpeg_ro_3;
|
355 |
|
|
edge_ro_4 <= (edge_ro_3 <= 2) ? edge_ro_3 : edge_ro_3 - 2;
|
356 |
|
|
end
|
357 |
|
|
end
|
358 |
|
|
|
359 |
|
|
always @(posedge clk)
|
360 |
|
|
begin
|
361 |
|
|
if (rst) begin
|
362 |
|
|
jpeg_4 <= 0; orc_4 <= 0; jpeg_ro_3 <= 0; edge_ro_3 <= 0;
|
363 |
|
|
end
|
364 |
|
|
else if (br_3) begin
|
365 |
|
|
jpeg_4 <= (orc_3 >= 2) ? jpeg_3 >> 2 : jpeg_3;
|
366 |
|
|
orc_4 <= (orc_3 >= 2) ? orc_3 - 2 : orc_3;
|
367 |
|
|
jpeg_ro_3 <= (edge_ro_2 <= 4) ? jpeg_ro_2 << 4 : jpeg_ro_2;
|
368 |
|
|
edge_ro_3 <= (edge_ro_2 <= 4) ? edge_ro_2 : edge_ro_2 - 4;
|
369 |
|
|
end
|
370 |
|
|
end
|
371 |
|
|
|
372 |
|
|
always @(posedge clk)
|
373 |
|
|
begin
|
374 |
|
|
if (rst) begin
|
375 |
|
|
jpeg_3 <= 0; orc_3 <= 0; jpeg_ro_2 <= 0; edge_ro_2 <= 0;
|
376 |
|
|
end
|
377 |
|
|
else if (br_2) begin
|
378 |
|
|
jpeg_3 <= (orc_2 >= 4) ? jpeg_2 >> 4 : jpeg_2;
|
379 |
|
|
orc_3 <= (orc_2 >= 4) ? orc_2 - 4 : orc_2;
|
380 |
|
|
jpeg_ro_2 <= (edge_ro_1 <= 8) ? jpeg_ro_1 << 8 : jpeg_ro_1;
|
381 |
|
|
edge_ro_2 <= (edge_ro_1 <= 8) ? edge_ro_1 : edge_ro_1 - 8;
|
382 |
|
|
end
|
383 |
|
|
end
|
384 |
|
|
|
385 |
|
|
always @(posedge clk)
|
386 |
|
|
begin
|
387 |
|
|
if (rst) begin
|
388 |
|
|
jpeg_2 <= 0; orc_2 <= 0; jpeg_ro_1 <= 0; edge_ro_1 <= 0;
|
389 |
|
|
end
|
390 |
|
|
else if (br_1) begin
|
391 |
|
|
jpeg_2 <= (orc_1 >= 8) ? jpeg_1 >> 8 : jpeg_1;
|
392 |
|
|
orc_2 <= (orc_1 >= 8) ? orc_1 - 8 : orc_1;
|
393 |
|
|
jpeg_ro_1 <= (orc_reg_delay <= 16) ? jpeg_delay << 16 : jpeg_delay;
|
394 |
|
|
edge_ro_1 <= (orc_reg_delay <= 16) ? orc_reg_delay : orc_reg_delay - 16;
|
395 |
|
|
end
|
396 |
|
|
end
|
397 |
|
|
|
398 |
|
|
always @(posedge clk)
|
399 |
|
|
begin
|
400 |
|
|
if (rst) begin
|
401 |
|
|
jpeg_1 <= 0; orc_1 <= 0; jpeg_delay <= 0; orc_reg_delay <= 0;
|
402 |
|
|
end
|
403 |
|
|
else if (bits_ready) begin
|
404 |
|
|
jpeg_1 <= (orc_reg >= 16) ? jpeg >> 16 : jpeg;
|
405 |
|
|
orc_1 <= (orc_reg >= 16) ? orc_reg - 16 : orc_reg;
|
406 |
|
|
jpeg_delay <= jpeg;
|
407 |
|
|
orc_reg_delay <= orc_reg;
|
408 |
|
|
end
|
409 |
|
|
end
|
410 |
|
|
|
411 |
|
|
always @(posedge clk)
|
412 |
|
|
begin
|
413 |
|
|
if (rst) begin
|
414 |
|
|
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0; enable_4 <= 0; enable_5 <= 0;
|
415 |
|
|
enable_6 <= 0; enable_7 <= 0; enable_8 <= 0; enable_9 <= 0; enable_10 <= 0;
|
416 |
|
|
enable_11 <= 0; enable_12 <= 0; enable_13 <= 0; enable_14 <= 0; enable_15 <= 0;
|
417 |
|
|
enable_16 <= 0; enable_17 <= 0; enable_18 <= 0; enable_19 <= 0; enable_20 <= 0;
|
418 |
|
|
enable_21 <= 0; enable_22 <= 0; enable_23 <= 0; enable_24 <= 0; enable_25 <= 0;
|
419 |
|
|
enable_26 <= 0; enable_27 <= 0; enable_28 <= 0; enable_29 <= 0; enable_30 <= 0;
|
420 |
|
|
enable_31 <= 0; enable_32 <= 0; enable_33 <= 0; enable_34 <= 0; enable_35 <= 0;
|
421 |
|
|
end
|
422 |
|
|
else begin
|
423 |
|
|
enable_1 <= end_of_block_output; enable_2 <= enable_1;
|
424 |
|
|
enable_3 <= enable_2; enable_4 <= enable_3; enable_5 <= enable_4;
|
425 |
|
|
enable_6 <= enable_5; enable_7 <= enable_6; enable_8 <= enable_7;
|
426 |
|
|
enable_9 <= enable_8; enable_10 <= enable_9; enable_11 <= enable_10;
|
427 |
|
|
enable_12 <= enable_11; enable_13 <= enable_12; enable_14 <= enable_13;
|
428 |
|
|
enable_15 <= enable_14; enable_16 <= enable_15; enable_17 <= enable_16;
|
429 |
|
|
enable_18 <= enable_17; enable_19 <= enable_18; enable_20 <= enable_19;
|
430 |
|
|
enable_21 <= enable_20;
|
431 |
|
|
enable_22 <= enable_21; enable_23 <= enable_22; enable_24 <= enable_23;
|
432 |
|
|
enable_25 <= enable_24; enable_26 <= enable_25; enable_27 <= enable_26;
|
433 |
|
|
enable_28 <= enable_27; enable_29 <= enable_28; enable_30 <= enable_29;
|
434 |
|
|
enable_31 <= enable_30;
|
435 |
|
|
enable_32 <= enable_31; enable_33 <= enable_32; enable_34 <= enable_33;
|
436 |
|
|
enable_35 <= enable_34;
|
437 |
|
|
end
|
438 |
|
|
end
|
439 |
|
|
|
440 |
|
|
always @(posedge clk)
|
441 |
|
|
begin
|
442 |
|
|
if (rst)
|
443 |
|
|
JPEG_bitstream[31] <= 0;
|
444 |
|
|
else if (br_7 & rollover_6)
|
445 |
|
|
JPEG_bitstream[31] <= jpeg_6[31];
|
446 |
|
|
else if (br_6 && static_orc_6 == 0)
|
447 |
|
|
JPEG_bitstream[31] <= jpeg_6[31];
|
448 |
|
|
end
|
449 |
|
|
|
450 |
|
|
always @(posedge clk)
|
451 |
|
|
begin
|
452 |
|
|
if (rst)
|
453 |
|
|
JPEG_bitstream[30] <= 0;
|
454 |
|
|
else if (br_7 & rollover_6)
|
455 |
|
|
JPEG_bitstream[30] <= jpeg_6[30];
|
456 |
|
|
else if (br_6 && static_orc_6 <= 1)
|
457 |
|
|
JPEG_bitstream[30] <= jpeg_6[30];
|
458 |
|
|
end
|
459 |
|
|
|
460 |
|
|
always @(posedge clk)
|
461 |
|
|
begin
|
462 |
|
|
if (rst)
|
463 |
|
|
JPEG_bitstream[29] <= 0;
|
464 |
|
|
else if (br_7 & rollover_6)
|
465 |
|
|
JPEG_bitstream[29] <= jpeg_6[29];
|
466 |
|
|
else if (br_6 && static_orc_6 <= 2)
|
467 |
|
|
JPEG_bitstream[29] <= jpeg_6[29];
|
468 |
|
|
end
|
469 |
|
|
|
470 |
|
|
always @(posedge clk)
|
471 |
|
|
begin
|
472 |
|
|
if (rst)
|
473 |
|
|
JPEG_bitstream[28] <= 0;
|
474 |
|
|
else if (br_7 & rollover_6)
|
475 |
|
|
JPEG_bitstream[28] <= jpeg_6[28];
|
476 |
|
|
else if (br_6 && static_orc_6 <= 3)
|
477 |
|
|
JPEG_bitstream[28] <= jpeg_6[28];
|
478 |
|
|
end
|
479 |
|
|
|
480 |
|
|
always @(posedge clk)
|
481 |
|
|
begin
|
482 |
|
|
if (rst)
|
483 |
|
|
JPEG_bitstream[27] <= 0;
|
484 |
|
|
else if (br_7 & rollover_6)
|
485 |
|
|
JPEG_bitstream[27] <= jpeg_6[27];
|
486 |
|
|
else if (br_6 && static_orc_6 <= 4)
|
487 |
|
|
JPEG_bitstream[27] <= jpeg_6[27];
|
488 |
|
|
end
|
489 |
|
|
|
490 |
|
|
always @(posedge clk)
|
491 |
|
|
begin
|
492 |
|
|
if (rst)
|
493 |
|
|
JPEG_bitstream[26] <= 0;
|
494 |
|
|
else if (br_7 & rollover_6)
|
495 |
|
|
JPEG_bitstream[26] <= jpeg_6[26];
|
496 |
|
|
else if (br_6 && static_orc_6 <= 5)
|
497 |
|
|
JPEG_bitstream[26] <= jpeg_6[26];
|
498 |
|
|
end
|
499 |
|
|
|
500 |
|
|
always @(posedge clk)
|
501 |
|
|
begin
|
502 |
|
|
if (rst)
|
503 |
|
|
JPEG_bitstream[25] <= 0;
|
504 |
|
|
else if (br_7 & rollover_6)
|
505 |
|
|
JPEG_bitstream[25] <= jpeg_6[25];
|
506 |
|
|
else if (br_6 && static_orc_6 <= 6)
|
507 |
|
|
JPEG_bitstream[25] <= jpeg_6[25];
|
508 |
|
|
end
|
509 |
|
|
|
510 |
|
|
always @(posedge clk)
|
511 |
|
|
begin
|
512 |
|
|
if (rst)
|
513 |
|
|
JPEG_bitstream[24] <= 0;
|
514 |
|
|
else if (br_7 & rollover_6)
|
515 |
|
|
JPEG_bitstream[24] <= jpeg_6[24];
|
516 |
|
|
else if (br_6 && static_orc_6 <= 7)
|
517 |
|
|
JPEG_bitstream[24] <= jpeg_6[24];
|
518 |
|
|
end
|
519 |
|
|
|
520 |
|
|
always @(posedge clk)
|
521 |
|
|
begin
|
522 |
|
|
if (rst)
|
523 |
|
|
JPEG_bitstream[23] <= 0;
|
524 |
|
|
else if (br_7 & rollover_6)
|
525 |
|
|
JPEG_bitstream[23] <= jpeg_6[23];
|
526 |
|
|
else if (br_6 && static_orc_6 <= 8)
|
527 |
|
|
JPEG_bitstream[23] <= jpeg_6[23];
|
528 |
|
|
end
|
529 |
|
|
|
530 |
|
|
always @(posedge clk)
|
531 |
|
|
begin
|
532 |
|
|
if (rst)
|
533 |
|
|
JPEG_bitstream[22] <= 0;
|
534 |
|
|
else if (br_7 & rollover_6)
|
535 |
|
|
JPEG_bitstream[22] <= jpeg_6[22];
|
536 |
|
|
else if (br_6 && static_orc_6 <= 9)
|
537 |
|
|
JPEG_bitstream[22] <= jpeg_6[22];
|
538 |
|
|
end
|
539 |
|
|
|
540 |
|
|
always @(posedge clk)
|
541 |
|
|
begin
|
542 |
|
|
if (rst)
|
543 |
|
|
JPEG_bitstream[21] <= 0;
|
544 |
|
|
else if (br_7 & rollover_6)
|
545 |
|
|
JPEG_bitstream[21] <= jpeg_6[21];
|
546 |
|
|
else if (br_6 && static_orc_6 <= 10)
|
547 |
|
|
JPEG_bitstream[21] <= jpeg_6[21];
|
548 |
|
|
end
|
549 |
|
|
|
550 |
|
|
always @(posedge clk)
|
551 |
|
|
begin
|
552 |
|
|
if (rst)
|
553 |
|
|
JPEG_bitstream[20] <= 0;
|
554 |
|
|
else if (br_7 & rollover_6)
|
555 |
|
|
JPEG_bitstream[20] <= jpeg_6[20];
|
556 |
|
|
else if (br_6 && static_orc_6 <= 11)
|
557 |
|
|
JPEG_bitstream[20] <= jpeg_6[20];
|
558 |
|
|
end
|
559 |
|
|
|
560 |
|
|
always @(posedge clk)
|
561 |
|
|
begin
|
562 |
|
|
if (rst)
|
563 |
|
|
JPEG_bitstream[19] <= 0;
|
564 |
|
|
else if (br_7 & rollover_6)
|
565 |
|
|
JPEG_bitstream[19] <= jpeg_6[19];
|
566 |
|
|
else if (br_6 && static_orc_6 <= 12)
|
567 |
|
|
JPEG_bitstream[19] <= jpeg_6[19];
|
568 |
|
|
end
|
569 |
|
|
|
570 |
|
|
always @(posedge clk)
|
571 |
|
|
begin
|
572 |
|
|
if (rst)
|
573 |
|
|
JPEG_bitstream[18] <= 0;
|
574 |
|
|
else if (br_7 & rollover_6)
|
575 |
|
|
JPEG_bitstream[18] <= jpeg_6[18];
|
576 |
|
|
else if (br_6 && static_orc_6 <= 13)
|
577 |
|
|
JPEG_bitstream[18] <= jpeg_6[18];
|
578 |
|
|
end
|
579 |
|
|
|
580 |
|
|
always @(posedge clk)
|
581 |
|
|
begin
|
582 |
|
|
if (rst)
|
583 |
|
|
JPEG_bitstream[17] <= 0;
|
584 |
|
|
else if (br_7 & rollover_6)
|
585 |
|
|
JPEG_bitstream[17] <= jpeg_6[17];
|
586 |
|
|
else if (br_6 && static_orc_6 <= 14)
|
587 |
|
|
JPEG_bitstream[17] <= jpeg_6[17];
|
588 |
|
|
end
|
589 |
|
|
|
590 |
|
|
always @(posedge clk)
|
591 |
|
|
begin
|
592 |
|
|
if (rst)
|
593 |
|
|
JPEG_bitstream[16] <= 0;
|
594 |
|
|
else if (br_7 & rollover_6)
|
595 |
|
|
JPEG_bitstream[16] <= jpeg_6[16];
|
596 |
|
|
else if (br_6 && static_orc_6 <= 15)
|
597 |
|
|
JPEG_bitstream[16] <= jpeg_6[16];
|
598 |
|
|
end
|
599 |
|
|
|
600 |
|
|
always @(posedge clk)
|
601 |
|
|
begin
|
602 |
|
|
if (rst)
|
603 |
|
|
JPEG_bitstream[15] <= 0;
|
604 |
|
|
else if (br_7 & rollover_6)
|
605 |
|
|
JPEG_bitstream[15] <= jpeg_6[15];
|
606 |
|
|
else if (br_6 && static_orc_6 <= 16)
|
607 |
|
|
JPEG_bitstream[15] <= jpeg_6[15];
|
608 |
|
|
end
|
609 |
|
|
|
610 |
|
|
always @(posedge clk)
|
611 |
|
|
begin
|
612 |
|
|
if (rst)
|
613 |
|
|
JPEG_bitstream[14] <= 0;
|
614 |
|
|
else if (br_7 & rollover_6)
|
615 |
|
|
JPEG_bitstream[14] <= jpeg_6[14];
|
616 |
|
|
else if (br_6 && static_orc_6 <= 17)
|
617 |
|
|
JPEG_bitstream[14] <= jpeg_6[14];
|
618 |
|
|
end
|
619 |
|
|
|
620 |
|
|
always @(posedge clk)
|
621 |
|
|
begin
|
622 |
|
|
if (rst)
|
623 |
|
|
JPEG_bitstream[13] <= 0;
|
624 |
|
|
else if (br_7 & rollover_6)
|
625 |
|
|
JPEG_bitstream[13] <= jpeg_6[13];
|
626 |
|
|
else if (br_6 && static_orc_6 <= 18)
|
627 |
|
|
JPEG_bitstream[13] <= jpeg_6[13];
|
628 |
|
|
end
|
629 |
|
|
|
630 |
|
|
always @(posedge clk)
|
631 |
|
|
begin
|
632 |
|
|
if (rst)
|
633 |
|
|
JPEG_bitstream[12] <= 0;
|
634 |
|
|
else if (br_7 & rollover_6)
|
635 |
|
|
JPEG_bitstream[12] <= jpeg_6[12];
|
636 |
|
|
else if (br_6 && static_orc_6 <= 19)
|
637 |
|
|
JPEG_bitstream[12] <= jpeg_6[12];
|
638 |
|
|
end
|
639 |
|
|
|
640 |
|
|
always @(posedge clk)
|
641 |
|
|
begin
|
642 |
|
|
if (rst)
|
643 |
|
|
JPEG_bitstream[11] <= 0;
|
644 |
|
|
else if (br_7 & rollover_6)
|
645 |
|
|
JPEG_bitstream[11] <= jpeg_6[11];
|
646 |
|
|
else if (br_6 && static_orc_6 <= 20)
|
647 |
|
|
JPEG_bitstream[11] <= jpeg_6[11];
|
648 |
|
|
end
|
649 |
|
|
|
650 |
|
|
always @(posedge clk)
|
651 |
|
|
begin
|
652 |
|
|
if (rst)
|
653 |
|
|
JPEG_bitstream[10] <= 0;
|
654 |
|
|
else if (br_7 & rollover_6)
|
655 |
|
|
JPEG_bitstream[10] <= jpeg_6[10];
|
656 |
|
|
else if (br_6 && static_orc_6 <= 21)
|
657 |
|
|
JPEG_bitstream[10] <= jpeg_6[10];
|
658 |
|
|
end
|
659 |
|
|
|
660 |
|
|
always @(posedge clk)
|
661 |
|
|
begin
|
662 |
|
|
if (rst)
|
663 |
|
|
JPEG_bitstream[9] <= 0;
|
664 |
|
|
else if (br_7 & rollover_6)
|
665 |
|
|
JPEG_bitstream[9] <= jpeg_6[9];
|
666 |
|
|
else if (br_6 && static_orc_6 <= 22)
|
667 |
|
|
JPEG_bitstream[9] <= jpeg_6[9];
|
668 |
|
|
end
|
669 |
|
|
|
670 |
|
|
always @(posedge clk)
|
671 |
|
|
begin
|
672 |
|
|
if (rst)
|
673 |
|
|
JPEG_bitstream[8] <= 0;
|
674 |
|
|
else if (br_7 & rollover_6)
|
675 |
|
|
JPEG_bitstream[8] <= jpeg_6[8];
|
676 |
|
|
else if (br_6 && static_orc_6 <= 23)
|
677 |
|
|
JPEG_bitstream[8] <= jpeg_6[8];
|
678 |
|
|
end
|
679 |
|
|
|
680 |
|
|
always @(posedge clk)
|
681 |
|
|
begin
|
682 |
|
|
if (rst)
|
683 |
|
|
JPEG_bitstream[7] <= 0;
|
684 |
|
|
else if (br_7 & rollover_6)
|
685 |
|
|
JPEG_bitstream[7] <= jpeg_6[7];
|
686 |
|
|
else if (br_6 && static_orc_6 <= 24)
|
687 |
|
|
JPEG_bitstream[7] <= jpeg_6[7];
|
688 |
|
|
end
|
689 |
|
|
|
690 |
|
|
always @(posedge clk)
|
691 |
|
|
begin
|
692 |
|
|
if (rst)
|
693 |
|
|
JPEG_bitstream[6] <= 0;
|
694 |
|
|
else if (br_7 & rollover_6)
|
695 |
|
|
JPEG_bitstream[6] <= jpeg_6[6];
|
696 |
|
|
else if (br_6 && static_orc_6 <= 25)
|
697 |
|
|
JPEG_bitstream[6] <= jpeg_6[6];
|
698 |
|
|
end
|
699 |
|
|
|
700 |
|
|
always @(posedge clk)
|
701 |
|
|
begin
|
702 |
|
|
if (rst)
|
703 |
|
|
JPEG_bitstream[5] <= 0;
|
704 |
|
|
else if (br_7 & rollover_6)
|
705 |
|
|
JPEG_bitstream[5] <= jpeg_6[5];
|
706 |
|
|
else if (br_6 && static_orc_6 <= 26)
|
707 |
|
|
JPEG_bitstream[5] <= jpeg_6[5];
|
708 |
|
|
end
|
709 |
|
|
|
710 |
|
|
always @(posedge clk)
|
711 |
|
|
begin
|
712 |
|
|
if (rst)
|
713 |
|
|
JPEG_bitstream[4] <= 0;
|
714 |
|
|
else if (br_7 & rollover_6)
|
715 |
|
|
JPEG_bitstream[4] <= jpeg_6[4];
|
716 |
|
|
else if (br_6 && static_orc_6 <= 27)
|
717 |
|
|
JPEG_bitstream[4] <= jpeg_6[4];
|
718 |
|
|
end
|
719 |
|
|
|
720 |
|
|
always @(posedge clk)
|
721 |
|
|
begin
|
722 |
|
|
if (rst)
|
723 |
|
|
JPEG_bitstream[3] <= 0;
|
724 |
|
|
else if (br_7 & rollover_6)
|
725 |
|
|
JPEG_bitstream[3] <= jpeg_6[3];
|
726 |
|
|
else if (br_6 && static_orc_6 <= 28)
|
727 |
|
|
JPEG_bitstream[3] <= jpeg_6[3];
|
728 |
|
|
end
|
729 |
|
|
|
730 |
|
|
always @(posedge clk)
|
731 |
|
|
begin
|
732 |
|
|
if (rst)
|
733 |
|
|
JPEG_bitstream[2] <= 0;
|
734 |
|
|
else if (br_7 & rollover_6)
|
735 |
|
|
JPEG_bitstream[2] <= jpeg_6[2];
|
736 |
|
|
else if (br_6 && static_orc_6 <= 29)
|
737 |
|
|
JPEG_bitstream[2] <= jpeg_6[2];
|
738 |
|
|
end
|
739 |
|
|
|
740 |
|
|
always @(posedge clk)
|
741 |
|
|
begin
|
742 |
|
|
if (rst)
|
743 |
|
|
JPEG_bitstream[1] <= 0;
|
744 |
|
|
else if (br_7 & rollover_6)
|
745 |
|
|
JPEG_bitstream[1] <= jpeg_6[1];
|
746 |
|
|
else if (br_6 && static_orc_6 <= 30)
|
747 |
|
|
JPEG_bitstream[1] <= jpeg_6[1];
|
748 |
|
|
end
|
749 |
|
|
|
750 |
|
|
always @(posedge clk)
|
751 |
|
|
begin
|
752 |
|
|
if (rst)
|
753 |
|
|
JPEG_bitstream[0] <= 0;
|
754 |
|
|
else if (br_7 & rollover_6)
|
755 |
|
|
JPEG_bitstream[0] <= jpeg_6[0];
|
756 |
|
|
else if (br_6 && static_orc_6 <= 31)
|
757 |
|
|
JPEG_bitstream[0] <= jpeg_6[0];
|
758 |
|
|
end
|
759 |
|
|
|
760 |
|
|
always @(posedge clk)
|
761 |
|
|
begin
|
762 |
|
|
if (rst) begin
|
763 |
|
|
jpeg_6 <= 0;
|
764 |
|
|
end
|
765 |
|
|
else if (br_5 | br_6) begin
|
766 |
|
|
jpeg_6[31] <= (rollover_5 & static_orc_5 > 0) ? jpeg_ro_5[31] : jpeg_5[31];
|
767 |
|
|
jpeg_6[30] <= (rollover_5 & static_orc_5 > 1) ? jpeg_ro_5[30] : jpeg_5[30];
|
768 |
|
|
jpeg_6[29] <= (rollover_5 & static_orc_5 > 2) ? jpeg_ro_5[29] : jpeg_5[29];
|
769 |
|
|
jpeg_6[28] <= (rollover_5 & static_orc_5 > 3) ? jpeg_ro_5[28] : jpeg_5[28];
|
770 |
|
|
jpeg_6[27] <= (rollover_5 & static_orc_5 > 4) ? jpeg_ro_5[27] : jpeg_5[27];
|
771 |
|
|
jpeg_6[26] <= (rollover_5 & static_orc_5 > 5) ? jpeg_ro_5[26] : jpeg_5[26];
|
772 |
|
|
jpeg_6[25] <= (rollover_5 & static_orc_5 > 6) ? jpeg_ro_5[25] : jpeg_5[25];
|
773 |
|
|
jpeg_6[24] <= (rollover_5 & static_orc_5 > 7) ? jpeg_ro_5[24] : jpeg_5[24];
|
774 |
|
|
jpeg_6[23] <= (rollover_5 & static_orc_5 > 8) ? jpeg_ro_5[23] : jpeg_5[23];
|
775 |
|
|
jpeg_6[22] <= (rollover_5 & static_orc_5 > 9) ? jpeg_ro_5[22] : jpeg_5[22];
|
776 |
|
|
jpeg_6[21] <= (rollover_5 & static_orc_5 > 10) ? jpeg_ro_5[21] : jpeg_5[21];
|
777 |
|
|
jpeg_6[20] <= (rollover_5 & static_orc_5 > 11) ? jpeg_ro_5[20] : jpeg_5[20];
|
778 |
|
|
jpeg_6[19] <= (rollover_5 & static_orc_5 > 12) ? jpeg_ro_5[19] : jpeg_5[19];
|
779 |
|
|
jpeg_6[18] <= (rollover_5 & static_orc_5 > 13) ? jpeg_ro_5[18] : jpeg_5[18];
|
780 |
|
|
jpeg_6[17] <= (rollover_5 & static_orc_5 > 14) ? jpeg_ro_5[17] : jpeg_5[17];
|
781 |
|
|
jpeg_6[16] <= (rollover_5 & static_orc_5 > 15) ? jpeg_ro_5[16] : jpeg_5[16];
|
782 |
|
|
jpeg_6[15] <= (rollover_5 & static_orc_5 > 16) ? jpeg_ro_5[15] : jpeg_5[15];
|
783 |
|
|
jpeg_6[14] <= (rollover_5 & static_orc_5 > 17) ? jpeg_ro_5[14] : jpeg_5[14];
|
784 |
|
|
jpeg_6[13] <= (rollover_5 & static_orc_5 > 18) ? jpeg_ro_5[13] : jpeg_5[13];
|
785 |
|
|
jpeg_6[12] <= (rollover_5 & static_orc_5 > 19) ? jpeg_ro_5[12] : jpeg_5[12];
|
786 |
|
|
jpeg_6[11] <= (rollover_5 & static_orc_5 > 20) ? jpeg_ro_5[11] : jpeg_5[11];
|
787 |
|
|
jpeg_6[10] <= (rollover_5 & static_orc_5 > 21) ? jpeg_ro_5[10] : jpeg_5[10];
|
788 |
|
|
jpeg_6[9] <= (rollover_5 & static_orc_5 > 22) ? jpeg_ro_5[9] : jpeg_5[9];
|
789 |
|
|
jpeg_6[8] <= (rollover_5 & static_orc_5 > 23) ? jpeg_ro_5[8] : jpeg_5[8];
|
790 |
|
|
jpeg_6[7] <= (rollover_5 & static_orc_5 > 24) ? jpeg_ro_5[7] : jpeg_5[7];
|
791 |
|
|
jpeg_6[6] <= (rollover_5 & static_orc_5 > 25) ? jpeg_ro_5[6] : jpeg_5[6];
|
792 |
|
|
jpeg_6[5] <= (rollover_5 & static_orc_5 > 26) ? jpeg_ro_5[5] : jpeg_5[5];
|
793 |
|
|
jpeg_6[4] <= (rollover_5 & static_orc_5 > 27) ? jpeg_ro_5[4] : jpeg_5[4];
|
794 |
|
|
jpeg_6[3] <= (rollover_5 & static_orc_5 > 28) ? jpeg_ro_5[3] : jpeg_5[3];
|
795 |
|
|
jpeg_6[2] <= (rollover_5 & static_orc_5 > 29) ? jpeg_ro_5[2] : jpeg_5[2];
|
796 |
|
|
jpeg_6[1] <= (rollover_5 & static_orc_5 > 30) ? jpeg_ro_5[1] : jpeg_5[1];
|
797 |
|
|
jpeg_6[0] <= jpeg_5[0];
|
798 |
|
|
end
|
799 |
|
|
end
|
800 |
|
|
|
801 |
|
|
endmodule
|