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1 2 davidklun 
/////////////////////////////////////////////////////////////////////
2 
////                                                             ////
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////  JPEG Encoder Core - Verilog                                ////
4 
////                                                             ////
5 
////  Author: David Lundgren                                     ////
6 
////          davidklun@gmail.com                                ////
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////                                                             ////
8 
/////////////////////////////////////////////////////////////////////
9 
////                                                             ////
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//// Copyright (C) 2009 David Lundgren                           ////
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////                  davidklun@gmail.com                        ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
16 
//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
18 
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
19 
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
21 
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
33 
 
34 
/* This module is the Huffman encoder.  It takes in the quantized outputs
35 
from the quantizer, and creates the Huffman codes from these value.  The
36 
output from this module is the jpeg code of the actual pixel data.  The jpeg
37 
file headers will need to be generated separately.  The Huffman codes are constant,
38 
and they can be changed by changing the parameters in this module. */
39 
 
40 
`timescale 1ns / 100ps
41 
 
42 
module y_huff(clk, rst, enable,
43 
Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y21, Y22, Y23, Y24, Y25, Y26, Y27, Y28,
44 
Y31, Y32, Y33, Y34, Y35, Y36, Y37, Y38, Y41, Y42, Y43, Y44, Y45, Y46, Y47, Y48,
45 
Y51, Y52, Y53, Y54, Y55, Y56, Y57, Y58, Y61, Y62, Y63, Y64, Y65, Y66, Y67, Y68,
46 
Y71, Y72, Y73, Y74, Y75, Y76, Y77, Y78, Y81, Y82, Y83, Y84, Y85, Y86, Y87, Y88,
47 
JPEG_bitstream, data_ready, output_reg_count, end_of_block_output,
48 
 end_of_block_empty);
49 
input           clk;
50 
input           rst;
51 
input           enable;
52 
input  [10:0]  Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y21, Y22, Y23, Y24;
53 
input  [10:0]  Y25, Y26, Y27, Y28, Y31, Y32, Y33, Y34, Y35, Y36, Y37, Y38;
54 
input  [10:0]  Y41, Y42, Y43, Y44, Y45, Y46, Y47, Y48, Y51, Y52, Y53, Y54;
55 
input  [10:0]  Y55, Y56, Y57, Y58, Y61, Y62, Y63, Y64, Y65, Y66, Y67, Y68;
56 
input  [10:0]  Y71, Y72, Y73, Y74, Y75, Y76, Y77, Y78, Y81, Y82, Y83, Y84;
57 
input  [10:0]  Y85, Y86, Y87, Y88;
58 
output  [31:0]   JPEG_bitstream;
59 
output  data_ready;
60 
output  output_reg_count;
61 
output  end_of_block_output;
62 
output          end_of_block_empty;
63 
 
64 
reg             [7:0] block_counter;
65 
reg             [11:0]  Y11_amp, Y11_1_pos, Y11_1_neg, Y11_diff;
66 
reg             [11:0]  Y11_previous, Y11_1;
67 
reg             [10:0]  Y12_amp, Y12_pos, Y12_neg;
68 
reg             [10:0]  Y21_pos, Y21_neg, Y31_pos, Y31_neg, Y22_pos, Y22_neg;
69 
reg             [10:0]  Y13_pos, Y13_neg, Y14_pos, Y14_neg, Y15_pos, Y15_neg;
70 
reg             [10:0]  Y16_pos, Y16_neg, Y17_pos, Y17_neg, Y18_pos, Y18_neg;
71 
reg             [10:0]  Y23_pos, Y23_neg, Y24_pos, Y24_neg, Y25_pos, Y25_neg;
72 
reg             [10:0]  Y26_pos, Y26_neg, Y27_pos, Y27_neg, Y28_pos, Y28_neg;
73 
reg             [10:0]  Y32_pos, Y32_neg;
74 
reg             [10:0]  Y33_pos, Y33_neg, Y34_pos, Y34_neg, Y35_pos, Y35_neg;
75 
reg             [10:0]  Y36_pos, Y36_neg, Y37_pos, Y37_neg, Y38_pos, Y38_neg;
76 
reg             [10:0]  Y41_pos, Y41_neg, Y42_pos, Y42_neg;
77 
reg             [10:0]  Y43_pos, Y43_neg, Y44_pos, Y44_neg, Y45_pos, Y45_neg;
78 
reg             [10:0]  Y46_pos, Y46_neg, Y47_pos, Y47_neg, Y48_pos, Y48_neg;
79 
reg             [10:0]  Y51_pos, Y51_neg, Y52_pos, Y52_neg;
80 
reg             [10:0]  Y53_pos, Y53_neg, Y54_pos, Y54_neg, Y55_pos, Y55_neg;
81 
reg             [10:0]  Y56_pos, Y56_neg, Y57_pos, Y57_neg, Y58_pos, Y58_neg;
82 
reg             [10:0]  Y61_pos, Y61_neg, Y62_pos, Y62_neg;
83 
reg             [10:0]  Y63_pos, Y63_neg, Y64_pos, Y64_neg, Y65_pos, Y65_neg;
84 
reg             [10:0]  Y66_pos, Y66_neg, Y67_pos, Y67_neg, Y68_pos, Y68_neg;
85 
reg             [10:0]  Y71_pos, Y71_neg, Y72_pos, Y72_neg;
86 
reg             [10:0]  Y73_pos, Y73_neg, Y74_pos, Y74_neg, Y75_pos, Y75_neg;
87 
reg             [10:0]  Y76_pos, Y76_neg, Y77_pos, Y77_neg, Y78_pos, Y78_neg;
88 
reg             [10:0]  Y81_pos, Y81_neg, Y82_pos, Y82_neg;
89 
reg             [10:0]  Y83_pos, Y83_neg, Y84_pos, Y84_neg, Y85_pos, Y85_neg;
90 
reg             [10:0]  Y86_pos, Y86_neg, Y87_pos, Y87_neg, Y88_pos, Y88_neg;
91 
reg             [3:0]    Y11_bits_pos, Y11_bits_neg, Y11_bits, Y11_bits_1;
92 
reg             [3:0]    Y12_bits_pos, Y12_bits_neg, Y12_bits, Y12_bits_1;
93 
reg             [3:0]    Y12_bits_2, Y12_bits_3;
94 
reg             Y11_msb, Y12_msb, Y12_msb_1, data_ready;
95 
reg             enable_1, enable_2, enable_3, enable_4, enable_5, enable_6;
96 
reg             enable_7, enable_8, enable_9, enable_10, enable_11, enable_12;
97 
reg             enable_13, enable_module, enable_latch_7, enable_latch_8;
98 
reg             Y12_et_zero, rollover, rollover_1, rollover_2, rollover_3;
99 
reg             rollover_4, rollover_5, rollover_6, rollover_7;
100 
reg             Y21_et_zero, Y21_msb, Y31_et_zero, Y31_msb;
101 
reg             Y22_et_zero, Y22_msb, Y13_et_zero, Y13_msb;
102 
reg             Y14_et_zero, Y14_msb, Y15_et_zero, Y15_msb;
103 
reg             Y16_et_zero, Y16_msb, Y17_et_zero, Y17_msb;
104 
reg             Y18_et_zero, Y18_msb;
105 
reg             Y23_et_zero, Y23_msb, Y24_et_zero, Y24_msb;
106 
reg             Y25_et_zero, Y25_msb, Y26_et_zero, Y26_msb;
107 
reg             Y27_et_zero, Y27_msb, Y28_et_zero, Y28_msb;
108 
reg             Y32_et_zero, Y32_msb, Y33_et_zero, Y33_msb;
109 
reg             Y34_et_zero, Y34_msb, Y35_et_zero, Y35_msb;
110 
reg             Y36_et_zero, Y36_msb, Y37_et_zero, Y37_msb;
111 
reg             Y38_et_zero, Y38_msb;
112 
reg             Y41_et_zero, Y41_msb, Y42_et_zero, Y42_msb;
113 
reg             Y43_et_zero, Y43_msb, Y44_et_zero, Y44_msb;
114 
reg             Y45_et_zero, Y45_msb, Y46_et_zero, Y46_msb;
115 
reg             Y47_et_zero, Y47_msb, Y48_et_zero, Y48_msb;
116 
reg             Y51_et_zero, Y51_msb, Y52_et_zero, Y52_msb;
117 
reg             Y53_et_zero, Y53_msb, Y54_et_zero, Y54_msb;
118 
reg             Y55_et_zero, Y55_msb, Y56_et_zero, Y56_msb;
119 
reg             Y57_et_zero, Y57_msb, Y58_et_zero, Y58_msb;
120 
reg             Y61_et_zero, Y61_msb, Y62_et_zero, Y62_msb;
121 
reg             Y63_et_zero, Y63_msb, Y64_et_zero, Y64_msb;
122 
reg             Y65_et_zero, Y65_msb, Y66_et_zero, Y66_msb;
123 
reg             Y67_et_zero, Y67_msb, Y68_et_zero, Y68_msb;
124 
reg             Y71_et_zero, Y71_msb, Y72_et_zero, Y72_msb;
125 
reg             Y73_et_zero, Y73_msb, Y74_et_zero, Y74_msb;
126 
reg             Y75_et_zero, Y75_msb, Y76_et_zero, Y76_msb;
127 
reg             Y77_et_zero, Y77_msb, Y78_et_zero, Y78_msb;
128 
reg             Y81_et_zero, Y81_msb, Y82_et_zero, Y82_msb;
129 
reg             Y83_et_zero, Y83_msb, Y84_et_zero, Y84_msb;
130 
reg             Y85_et_zero, Y85_msb, Y86_et_zero, Y86_msb;
131 
reg             Y87_et_zero, Y87_msb, Y88_et_zero, Y88_msb;
132 
reg     Y12_et_zero_1, Y12_et_zero_2, Y12_et_zero_3, Y12_et_zero_4, Y12_et_zero_5;
133 
reg             [10:0] Y_DC [11:0];
134 
reg     [3:0] Y_DC_code_length [11:0];
135 
reg             [15:0] Y_AC [161:0];
136 
reg     [4:0] Y_AC_code_length [161:0];
137 
reg     [7:0] Y_AC_run_code [250:0];
138 
reg             [10:0] Y11_Huff, Y11_Huff_1, Y11_Huff_2;
139 
reg             [15:0] Y12_Huff, Y12_Huff_1, Y12_Huff_2;
140 
reg             [3:0] Y11_Huff_count, Y11_Huff_shift, Y11_Huff_shift_1, Y11_amp_shift, Y12_amp_shift;
141 
reg             [3:0] Y12_Huff_shift, Y12_Huff_shift_1, zero_run_length, zrl_1, zrl_2, zrl_3;
142 
reg             [4:0] Y12_Huff_count, Y12_Huff_count_1;
143 
reg             [4:0] output_reg_count, Y11_output_count, old_orc_1, old_orc_2;
144 
reg             [4:0] old_orc_3, old_orc_4, old_orc_5, old_orc_6, Y12_oc_1;
145 
reg             [4:0] orc_3, orc_4, orc_5, orc_6, orc_7, orc_8;
146 
reg             [4:0] Y12_output_count;
147 
reg     [4:0] Y12_edge, Y12_edge_1, Y12_edge_2, Y12_edge_3, Y12_edge_4;
148 
reg             [31:0]   JPEG_bitstream, JPEG_bs, JPEG_bs_1, JPEG_bs_2, JPEG_bs_3, JPEG_bs_4, JPEG_bs_5;
149 
reg             [31:0]   JPEG_Y12_bs, JPEG_Y12_bs_1, JPEG_Y12_bs_2, JPEG_Y12_bs_3, JPEG_Y12_bs_4;
150 
reg             [31:0]   JPEG_ro_bs, JPEG_ro_bs_1, JPEG_ro_bs_2, JPEG_ro_bs_3, JPEG_ro_bs_4;
151 
reg             [21:0]   Y11_JPEG_LSBs_3;
152 
reg             [10:0]   Y11_JPEG_LSBs, Y11_JPEG_LSBs_1, Y11_JPEG_LSBs_2;
153 
reg             [9:0]    Y12_JPEG_LSBs, Y12_JPEG_LSBs_1, Y12_JPEG_LSBs_2, Y12_JPEG_LSBs_3;
154 
reg             [25:0]   Y11_JPEG_bits, Y11_JPEG_bits_1, Y12_JPEG_bits, Y12_JPEG_LSBs_4;
155 
reg             [7:0]    Y12_code_entry;
156 
reg             third_8_all_0s, fourth_8_all_0s, fifth_8_all_0s, sixth_8_all_0s, seventh_8_all_0s;
157 
reg             eighth_8_all_0s, end_of_block, code_15_0, zrl_et_15, end_of_block_output;
158 
reg             end_of_block_empty;
159 
 
160 
wire    [7:0]    code_index = { zrl_2, Y12_bits };
161 
 
162 
 
163 
 
164 
always @(posedge clk)
165 
begin
166 
        if (rst) begin
167 
                third_8_all_0s <= 0; fourth_8_all_0s <= 0;
168 
                fifth_8_all_0s <= 0; sixth_8_all_0s <= 0; seventh_8_all_0s <= 0;
169 
                eighth_8_all_0s <= 0;
170 
                end
171 
        else if (enable_1) begin
172 
                third_8_all_0s <= Y25_et_zero & Y34_et_zero & Y43_et_zero & Y52_et_zero
173 
                                          & Y61_et_zero & Y71_et_zero & Y62_et_zero & Y53_et_zero;
174 
                fourth_8_all_0s <= Y44_et_zero & Y35_et_zero & Y26_et_zero & Y17_et_zero
175 
                                          & Y18_et_zero & Y27_et_zero & Y36_et_zero & Y45_et_zero;
176 
                fifth_8_all_0s <= Y54_et_zero & Y63_et_zero & Y72_et_zero & Y81_et_zero
177 
                                          & Y82_et_zero & Y73_et_zero & Y64_et_zero & Y55_et_zero;
178 
                sixth_8_all_0s <= Y46_et_zero & Y37_et_zero & Y28_et_zero & Y38_et_zero
179 
                                          & Y47_et_zero & Y56_et_zero & Y65_et_zero & Y74_et_zero;
180 
                seventh_8_all_0s <= Y83_et_zero & Y84_et_zero & Y75_et_zero & Y66_et_zero
181 
                                          & Y57_et_zero & Y48_et_zero & Y58_et_zero & Y67_et_zero;
182 
                eighth_8_all_0s <= Y76_et_zero & Y85_et_zero & Y86_et_zero & Y77_et_zero
183 
                                          & Y68_et_zero & Y78_et_zero & Y87_et_zero & Y88_et_zero;
184 
                end
185 
end
186 
 
187 
 
188 
/* end_of_block checks to see if there are any nonzero elements left in the block
189 
If there aren't any nonzero elements left, then the last bits in the JPEG stream
190 
will be the end of block code.  The purpose of this register is to determine if the
191 
zero run length code 15-0 should be used or not.  It should be used if there are 15 or more
192 
zeros in a row, followed by a nonzero value.  If there are only zeros left in the block,
193 
then end_of_block will be 1.  If there are any nonzero values left in the block, end_of_block
194 
will be 0. */
195 
 
196 
always @(posedge clk)
197 
begin
198 
        if (rst)
199 
                end_of_block <= 0;
200 
        else if (enable)
201 
                end_of_block <= 0;
202 
        else if (enable_module & block_counter < 32)
203 
                end_of_block <= third_8_all_0s & fourth_8_all_0s & fifth_8_all_0s
204 
                                        & sixth_8_all_0s & seventh_8_all_0s & eighth_8_all_0s;
205 
        else if (enable_module & block_counter < 48)
206 
                end_of_block <= fifth_8_all_0s & sixth_8_all_0s & seventh_8_all_0s
207 
                                        & eighth_8_all_0s;
208 
        else if (enable_module & block_counter <= 64)
209 
                end_of_block <= seventh_8_all_0s & eighth_8_all_0s;
210 
        else if (enable_module & block_counter > 64)
211 
                end_of_block <= 1;
212 
end
213 
 
214 
always @(posedge clk)
215 
begin
216 
        if (rst) begin
217 
                block_counter <= 0;
218 
                end
219 
        else if (enable) begin
220 
                block_counter <= 0;
221 
                end
222 
        else if (enable_module) begin
223 
                block_counter <= block_counter + 1;
224 
                end
225 
end
226 
 
227 
always @(posedge clk)
228 
begin
229 
        if (rst) begin
230 
                output_reg_count <= 0;
231 
                end
232 
        else if (end_of_block_output) begin
233 
                output_reg_count <= 0;
234 
                end
235 
        else if (enable_6) begin
236 
                output_reg_count <= output_reg_count + Y11_output_count;
237 
                end
238 
        else if (enable_latch_7) begin
239 
                output_reg_count <= output_reg_count + Y12_oc_1;
240 
                end
241 
end
242 
 
243 
always @(posedge clk)
244 
begin
245 
        if (rst) begin
246 
                old_orc_1 <= 0;
247 
                end
248 
        else if (end_of_block_output) begin
249 
                old_orc_1 <= 0;
250 
                end
251 
        else if (enable_module) begin
252 
                old_orc_1 <= output_reg_count;
253 
                end
254 
end
255 
 
256 
always @(posedge clk)
257 
begin
258 
        if (rst) begin
259 
                rollover <= 0; rollover_1 <= 0; rollover_2 <= 0;
260 
                rollover_3 <= 0; rollover_4 <= 0; rollover_5 <= 0;
261 
                rollover_6 <= 0; rollover_7 <= 0;
262 
                old_orc_2 <= 0;
263 
                orc_3 <= 0; orc_4 <= 0; orc_5 <= 0; orc_6 <= 0;
264 
                orc_7 <= 0; orc_8 <= 0; data_ready <= 0;
265 
                end_of_block_output <= 0; end_of_block_empty <= 0;
266 
                end
267 
        else if (enable_module) begin
268 
                rollover <= (old_orc_1 > output_reg_count);
269 
                rollover_1 <= rollover;
270 
                rollover_2 <= rollover_1;
271 
                rollover_3 <= rollover_2;
272 
                rollover_4 <= rollover_3;
273 
                rollover_5 <= rollover_4;
274 
                rollover_6 <= rollover_5;
275 
                rollover_7 <= rollover_6;
276 
                old_orc_2 <= old_orc_1;
277 
                orc_3 <= old_orc_2;
278 
                orc_4 <= orc_3; orc_5 <= orc_4;
279 
                orc_6 <= orc_5; orc_7 <= orc_6;
280 
                orc_8 <= orc_7;
281 
                data_ready <= rollover_6 | block_counter == 77;
282 
                end_of_block_output <= block_counter == 77;
283 
                end_of_block_empty <= rollover_7 & block_counter == 77 & output_reg_count == 0;
284 
                end
285 
end
286 
 
287 
 
288 
 
289 
always @(posedge clk)
290 
begin
291 
        if (rst) begin
292 
                JPEG_bs_5 <= 0;
293 
                end
294 
        else if (enable_module) begin
295 
                JPEG_bs_5[31] <= (rollover_6 & orc_7 > 0) ? JPEG_ro_bs_4[31] : JPEG_bs_4[31];
296 
                JPEG_bs_5[30] <= (rollover_6 & orc_7 > 1) ? JPEG_ro_bs_4[30] : JPEG_bs_4[30];
297 
                JPEG_bs_5[29] <= (rollover_6 & orc_7 > 2) ? JPEG_ro_bs_4[29] : JPEG_bs_4[29];
298 
                JPEG_bs_5[28] <= (rollover_6 & orc_7 > 3) ? JPEG_ro_bs_4[28] : JPEG_bs_4[28];
299 
                JPEG_bs_5[27] <= (rollover_6 & orc_7 > 4) ? JPEG_ro_bs_4[27] : JPEG_bs_4[27];
300 
                JPEG_bs_5[26] <= (rollover_6 & orc_7 > 5) ? JPEG_ro_bs_4[26] : JPEG_bs_4[26];
301 
                JPEG_bs_5[25] <= (rollover_6 & orc_7 > 6) ? JPEG_ro_bs_4[25] : JPEG_bs_4[25];
302 
                JPEG_bs_5[24] <= (rollover_6 & orc_7 > 7) ? JPEG_ro_bs_4[24] : JPEG_bs_4[24];
303 
                JPEG_bs_5[23] <= (rollover_6 & orc_7 > 8) ? JPEG_ro_bs_4[23] : JPEG_bs_4[23];
304 
                JPEG_bs_5[22] <= (rollover_6 & orc_7 > 9) ? JPEG_ro_bs_4[22] : JPEG_bs_4[22];
305 
                JPEG_bs_5[21] <= (rollover_6 & orc_7 > 10) ? JPEG_ro_bs_4[21] : JPEG_bs_4[21];
306 
                JPEG_bs_5[20] <= (rollover_6 & orc_7 > 11) ? JPEG_ro_bs_4[20] : JPEG_bs_4[20];
307 
                JPEG_bs_5[19] <= (rollover_6 & orc_7 > 12) ? JPEG_ro_bs_4[19] : JPEG_bs_4[19];
308 
                JPEG_bs_5[18] <= (rollover_6 & orc_7 > 13) ? JPEG_ro_bs_4[18] : JPEG_bs_4[18];
309 
                JPEG_bs_5[17] <= (rollover_6 & orc_7 > 14) ? JPEG_ro_bs_4[17] : JPEG_bs_4[17];
310 
                JPEG_bs_5[16] <= (rollover_6 & orc_7 > 15) ? JPEG_ro_bs_4[16] : JPEG_bs_4[16];
311 
                JPEG_bs_5[15] <= (rollover_6 & orc_7 > 16) ? JPEG_ro_bs_4[15] : JPEG_bs_4[15];
312 
                JPEG_bs_5[14] <= (rollover_6 & orc_7 > 17) ? JPEG_ro_bs_4[14] : JPEG_bs_4[14];
313 
                JPEG_bs_5[13] <= (rollover_6 & orc_7 > 18) ? JPEG_ro_bs_4[13] : JPEG_bs_4[13];
314 
                JPEG_bs_5[12] <= (rollover_6 & orc_7 > 19) ? JPEG_ro_bs_4[12] : JPEG_bs_4[12];
315 
                JPEG_bs_5[11] <= (rollover_6 & orc_7 > 20) ? JPEG_ro_bs_4[11] : JPEG_bs_4[11];
316 
                JPEG_bs_5[10] <= (rollover_6 & orc_7 > 21) ? JPEG_ro_bs_4[10] : JPEG_bs_4[10];
317 
                JPEG_bs_5[9] <= (rollover_6 & orc_7 > 22) ? JPEG_ro_bs_4[9] : JPEG_bs_4[9];
318 
                JPEG_bs_5[8] <= (rollover_6 & orc_7 > 23) ? JPEG_ro_bs_4[8] : JPEG_bs_4[8];
319 
                JPEG_bs_5[7] <= (rollover_6 & orc_7 > 24) ? JPEG_ro_bs_4[7] : JPEG_bs_4[7];
320 
                JPEG_bs_5[6] <= (rollover_6 & orc_7 > 25) ? JPEG_ro_bs_4[6] : JPEG_bs_4[6];
321 
                JPEG_bs_5[5] <= (rollover_6 & orc_7 > 26) ? JPEG_ro_bs_4[5] : JPEG_bs_4[5];
322 
                JPEG_bs_5[4] <= (rollover_6 & orc_7 > 27) ? JPEG_ro_bs_4[4] : JPEG_bs_4[4];
323 
                JPEG_bs_5[3] <= (rollover_6 & orc_7 > 28) ? JPEG_ro_bs_4[3] : JPEG_bs_4[3];
324 
                JPEG_bs_5[2] <= (rollover_6 & orc_7 > 29) ? JPEG_ro_bs_4[2] : JPEG_bs_4[2];
325 
                JPEG_bs_5[1] <= (rollover_6 & orc_7 > 30) ? JPEG_ro_bs_4[1] : JPEG_bs_4[1];
326 
                JPEG_bs_5[0] <= JPEG_bs_4[0];
327 
                end
328 
end
329 
 
330 
always @(posedge clk)
331 
begin
332 
        if (rst) begin
333 
                JPEG_bs_4 <= 0; JPEG_ro_bs_4 <= 0;
334 
                end
335 
        else if (enable_module) begin
336 
                JPEG_bs_4 <= (old_orc_6 == 1) ? JPEG_bs_3 >> 1 : JPEG_bs_3;
337 
                JPEG_ro_bs_4 <= (Y12_edge_4 <= 1) ? JPEG_ro_bs_3 << 1 : JPEG_ro_bs_3;
338 
                end
339 
end
340 
 
341 
always @(posedge clk)
342 
begin
343 
        if (rst) begin
344 
                JPEG_bs_3 <= 0; old_orc_6 <= 0; JPEG_ro_bs_3 <= 0;
345 
                Y12_edge_4 <= 0;
346 
                end
347 
        else if (enable_module) begin
348 
                JPEG_bs_3 <= (old_orc_5 >= 2) ? JPEG_bs_2 >> 2 : JPEG_bs_2;
349 
                old_orc_6 <= (old_orc_5 >= 2) ? old_orc_5 - 2 : old_orc_5;
350 
                JPEG_ro_bs_3 <= (Y12_edge_3 <= 2) ? JPEG_ro_bs_2 << 2 : JPEG_ro_bs_2;
351 
                Y12_edge_4 <= (Y12_edge_3 <= 2) ? Y12_edge_3 : Y12_edge_3 - 2;
352 
                end
353 
end
354 
 
355 
always @(posedge clk)
356 
begin
357 
        if (rst) begin
358 
                JPEG_bs_2 <= 0; old_orc_5 <= 0; JPEG_ro_bs_2 <= 0;
359 
                Y12_edge_3 <= 0;
360 
                end
361 
        else if (enable_module) begin
362 
                JPEG_bs_2 <= (old_orc_4 >= 4) ? JPEG_bs_1 >> 4 : JPEG_bs_1;
363 
                old_orc_5 <= (old_orc_4 >= 4) ? old_orc_4 - 4 : old_orc_4;
364 
                JPEG_ro_bs_2 <= (Y12_edge_2 <= 4) ? JPEG_ro_bs_1 << 4 : JPEG_ro_bs_1;
365 
                Y12_edge_3 <= (Y12_edge_2 <= 4) ? Y12_edge_2 : Y12_edge_2 - 4;
366 
                end
367 
end
368 
 
369 
always @(posedge clk)
370 
begin
371 
        if (rst) begin
372 
                JPEG_bs_1 <= 0; old_orc_4 <= 0; JPEG_ro_bs_1 <= 0;
373 
                Y12_edge_2 <= 0;
374 
                end
375 
        else if (enable_module) begin
376 
                JPEG_bs_1 <= (old_orc_3 >= 8) ? JPEG_bs >> 8 : JPEG_bs;
377 
                old_orc_4 <= (old_orc_3 >= 8) ? old_orc_3 - 8 : old_orc_3;
378 
                JPEG_ro_bs_1 <= (Y12_edge_1 <= 8) ? JPEG_ro_bs << 8 : JPEG_ro_bs;
379 
                Y12_edge_2 <= (Y12_edge_1 <= 8) ? Y12_edge_1 : Y12_edge_1 - 8;
380 
                end
381 
end
382 
 
383 
always @(posedge clk)
384 
begin
385 
        if (rst) begin
386 
                JPEG_bs <= 0; old_orc_3 <= 0; JPEG_ro_bs <= 0;
387 
                Y12_edge_1 <= 0; Y11_JPEG_bits_1 <= 0;
388 
                end
389 
        else if (enable_module) begin
390 
                JPEG_bs <= (old_orc_2 >= 16) ? Y11_JPEG_bits >> 10 : Y11_JPEG_bits << 6;
391 
                old_orc_3 <= (old_orc_2 >= 16) ? old_orc_2 - 16 : old_orc_2;
392 
                JPEG_ro_bs <= (Y12_edge <= 16) ? Y11_JPEG_bits_1 << 16 : Y11_JPEG_bits_1;
393 
                Y12_edge_1 <= (Y12_edge <= 16) ? Y12_edge : Y12_edge - 16;
394 
                Y11_JPEG_bits_1 <= Y11_JPEG_bits;
395 
                end
396 
end
397 
 
398 
always @(posedge clk)
399 
begin
400 
        if (rst) begin
401 
                Y12_JPEG_bits <= 0; Y12_edge <= 0;
402 
                end
403 
        else if (enable_module) begin
404 
                Y12_JPEG_bits[25] <= (Y12_Huff_shift_1 >= 16) ? Y12_JPEG_LSBs_4[25] : Y12_Huff_2[15];
405 
                Y12_JPEG_bits[24] <= (Y12_Huff_shift_1 >= 15) ? Y12_JPEG_LSBs_4[24] : Y12_Huff_2[14];
406 
                Y12_JPEG_bits[23] <= (Y12_Huff_shift_1 >= 14) ? Y12_JPEG_LSBs_4[23] : Y12_Huff_2[13];
407 
                Y12_JPEG_bits[22] <= (Y12_Huff_shift_1 >= 13) ? Y12_JPEG_LSBs_4[22] : Y12_Huff_2[12];
408 
                Y12_JPEG_bits[21] <= (Y12_Huff_shift_1 >= 12) ? Y12_JPEG_LSBs_4[21] : Y12_Huff_2[11];
409 
                Y12_JPEG_bits[20] <= (Y12_Huff_shift_1 >= 11) ? Y12_JPEG_LSBs_4[20] : Y12_Huff_2[10];
410 
                Y12_JPEG_bits[19] <= (Y12_Huff_shift_1 >= 10) ? Y12_JPEG_LSBs_4[19] : Y12_Huff_2[9];
411 
                Y12_JPEG_bits[18] <= (Y12_Huff_shift_1 >= 9) ? Y12_JPEG_LSBs_4[18] : Y12_Huff_2[8];
412 
                Y12_JPEG_bits[17] <= (Y12_Huff_shift_1 >= 8) ? Y12_JPEG_LSBs_4[17] : Y12_Huff_2[7];
413 
                Y12_JPEG_bits[16] <= (Y12_Huff_shift_1 >= 7) ? Y12_JPEG_LSBs_4[16] : Y12_Huff_2[6];
414 
                Y12_JPEG_bits[15] <= (Y12_Huff_shift_1 >= 6) ? Y12_JPEG_LSBs_4[15] : Y12_Huff_2[5];
415 
                Y12_JPEG_bits[14] <= (Y12_Huff_shift_1 >= 5) ? Y12_JPEG_LSBs_4[14] : Y12_Huff_2[4];
416 
                Y12_JPEG_bits[13] <= (Y12_Huff_shift_1 >= 4) ? Y12_JPEG_LSBs_4[13] : Y12_Huff_2[3];
417 
                Y12_JPEG_bits[12] <= (Y12_Huff_shift_1 >= 3) ? Y12_JPEG_LSBs_4[12] : Y12_Huff_2[2];
418 
                Y12_JPEG_bits[11] <= (Y12_Huff_shift_1 >= 2) ? Y12_JPEG_LSBs_4[11] : Y12_Huff_2[1];
419 
                Y12_JPEG_bits[10] <= (Y12_Huff_shift_1 >= 1) ? Y12_JPEG_LSBs_4[10] : Y12_Huff_2[0];
420 
                Y12_JPEG_bits[9:0] <= Y12_JPEG_LSBs_4[9:0];
421 
                Y12_edge <= old_orc_2 + 26; // 26 is the size of Y11_JPEG_bits
422 
                end
423 
end
424 
 
425 
always @(posedge clk)
426 
begin
427 
        if (rst) begin
428 
                Y11_JPEG_bits <= 0;
429 
                end
430 
        else if (enable_7) begin
431 
                Y11_JPEG_bits[25] <= (Y11_Huff_shift_1 >= 11) ? Y11_JPEG_LSBs_3[21] : Y11_Huff_2[10];
432 
                Y11_JPEG_bits[24] <= (Y11_Huff_shift_1 >= 10) ? Y11_JPEG_LSBs_3[20] : Y11_Huff_2[9];
433 
                Y11_JPEG_bits[23] <= (Y11_Huff_shift_1 >= 9) ? Y11_JPEG_LSBs_3[19] : Y11_Huff_2[8];
434 
                Y11_JPEG_bits[22] <= (Y11_Huff_shift_1 >= 8) ? Y11_JPEG_LSBs_3[18] : Y11_Huff_2[7];
435 
                Y11_JPEG_bits[21] <= (Y11_Huff_shift_1 >= 7) ? Y11_JPEG_LSBs_3[17] : Y11_Huff_2[6];
436 
                Y11_JPEG_bits[20] <= (Y11_Huff_shift_1 >= 6) ? Y11_JPEG_LSBs_3[16] : Y11_Huff_2[5];
437 
                Y11_JPEG_bits[19] <= (Y11_Huff_shift_1 >= 5) ? Y11_JPEG_LSBs_3[15] : Y11_Huff_2[4];
438 
                Y11_JPEG_bits[18] <= (Y11_Huff_shift_1 >= 4) ? Y11_JPEG_LSBs_3[14] : Y11_Huff_2[3];
439 
                Y11_JPEG_bits[17] <= (Y11_Huff_shift_1 >= 3) ? Y11_JPEG_LSBs_3[13] : Y11_Huff_2[2];
440 
                Y11_JPEG_bits[16] <= (Y11_Huff_shift_1 >= 2) ? Y11_JPEG_LSBs_3[12] : Y11_Huff_2[1];
441 
                Y11_JPEG_bits[15] <= (Y11_Huff_shift_1 >= 1) ? Y11_JPEG_LSBs_3[11] : Y11_Huff_2[0];
442 
                Y11_JPEG_bits[14:4] <= Y11_JPEG_LSBs_3[10:0];
443 
                end
444 
        else if (enable_latch_8) begin
445 
                Y11_JPEG_bits <= Y12_JPEG_bits;
446 
                end
447 
end
448 
 
449 
 
450 
always @(posedge clk)
451 
begin
452 
        if (rst) begin
453 
                Y12_oc_1 <= 0; Y12_JPEG_LSBs_4 <= 0;
454 
                Y12_Huff_2 <= 0; Y12_Huff_shift_1 <= 0;
455 
                end
456 
        else if (enable_module) begin
457 
                Y12_oc_1 <= (Y12_et_zero_5 & !code_15_0 & block_counter != 67) ? 0 :
458 
                        Y12_bits_3 + Y12_Huff_count_1;
459 
                Y12_JPEG_LSBs_4 <= Y12_JPEG_LSBs_3 << Y12_Huff_shift;
460 
                Y12_Huff_2 <= Y12_Huff_1;
461 
                Y12_Huff_shift_1 <= Y12_Huff_shift;
462 
                end
463 
end
464 
 
465 
always @(posedge clk)
466 
begin
467 
        if (rst) begin
468 
                Y11_JPEG_LSBs_3 <= 0; Y11_Huff_2 <= 0;
469 
                Y11_Huff_shift_1 <= 0;
470 
                end
471 
        else if (enable_6) begin
472 
                Y11_JPEG_LSBs_3 <= Y11_JPEG_LSBs_2 << Y11_Huff_shift;
473 
                Y11_Huff_2 <= Y11_Huff_1;
474 
                Y11_Huff_shift_1 <= Y11_Huff_shift;
475 
                end
476 
end
477 
 
478 
 
479 
always @(posedge clk)
480 
begin
481 
        if (rst) begin
482 
                Y12_Huff_shift <= 0;
483 
                Y12_Huff_1 <= 0; Y12_JPEG_LSBs_3 <= 0; Y12_bits_3 <= 0;
484 
                Y12_Huff_count_1 <= 0; Y12_et_zero_5 <= 0; code_15_0 <= 0;
485 
                end
486 
        else if (enable_module) begin
487 
                Y12_Huff_shift <= 16 - Y12_Huff_count;
488 
                Y12_Huff_1 <= Y12_Huff;
489 
                Y12_JPEG_LSBs_3 <= Y12_JPEG_LSBs_2;
490 
                Y12_bits_3 <= Y12_bits_2;
491 
                Y12_Huff_count_1 <= Y12_Huff_count;
492 
                Y12_et_zero_5 <= Y12_et_zero_4;
493 
                code_15_0 <= zrl_et_15 & !end_of_block;
494 
                end
495 
end
496 
 
497 
always @(posedge clk)
498 
begin
499 
        if (rst) begin
500 
                Y11_output_count <= 0; Y11_JPEG_LSBs_2 <= 0; Y11_Huff_shift <= 0;
501 
                Y11_Huff_1 <= 0;
502 
                end
503 
        else if (enable_5) begin
504 
                Y11_output_count <= Y11_bits_1 + Y11_Huff_count;
505 
                Y11_JPEG_LSBs_2 <= Y11_JPEG_LSBs_1 << Y11_amp_shift;
506 
                Y11_Huff_shift <= 11 - Y11_Huff_count;
507 
                Y11_Huff_1 <= Y11_Huff;
508 
                end
509 
end
510 
 
511 
 
512 
always @(posedge clk)
513 
begin
514 
        if (rst) begin
515 
                Y12_JPEG_LSBs_2 <= 0;
516 
                Y12_Huff <= 0; Y12_Huff_count <= 0; Y12_bits_2 <= 0;
517 
                Y12_et_zero_4 <= 0; zrl_et_15 <= 0; zrl_3 <= 0;
518 
                end
519 
        else if (enable_module) begin
520 
                Y12_JPEG_LSBs_2 <= Y12_JPEG_LSBs_1 << Y12_amp_shift;
521 
                Y12_Huff <= Y_AC[Y12_code_entry];
522 
                Y12_Huff_count <= Y_AC_code_length[Y12_code_entry];
523 
                Y12_bits_2 <= Y12_bits_1;
524 
                Y12_et_zero_4 <= Y12_et_zero_3;
525 
                zrl_et_15 <= zrl_3 == 15;
526 
                zrl_3 <= zrl_2;
527 
                end
528 
end
529 
 
530 
always @(posedge clk)
531 
begin
532 
        if (rst) begin
533 
                Y11_Huff <= 0; Y11_Huff_count <= 0; Y11_amp_shift <= 0;
534 
                Y11_JPEG_LSBs_1 <= 0; Y11_bits_1 <= 0;
535 
                end
536 
        else if (enable_4) begin
537 
                Y11_Huff[10:0] <= Y_DC[Y11_bits];
538 
                Y11_Huff_count <= Y_DC_code_length[Y11_bits];
539 
                Y11_amp_shift <= 11 - Y11_bits;
540 
                Y11_JPEG_LSBs_1 <= Y11_JPEG_LSBs;
541 
                Y11_bits_1 <= Y11_bits;
542 
                end
543 
end
544 
 
545 
always @(posedge clk)
546 
begin
547 
        if (rst) begin
548 
                Y12_code_entry <= 0; Y12_JPEG_LSBs_1 <= 0; Y12_amp_shift <= 0;
549 
                Y12_bits_1 <= 0; Y12_et_zero_3 <= 0; zrl_2 <= 0;
550 
                end
551 
        else if (enable_module) begin
552 
                Y12_code_entry <= Y_AC_run_code[code_index];
553 
                Y12_JPEG_LSBs_1 <= Y12_JPEG_LSBs;
554 
                Y12_amp_shift <= 10 - Y12_bits;
555 
                Y12_bits_1 <= Y12_bits;
556 
                Y12_et_zero_3 <= Y12_et_zero_2;
557 
                zrl_2 <= zrl_1;
558 
                end
559 
end
560 
 
561 
always @(posedge clk)
562 
begin
563 
        if (rst) begin
564 
                Y11_bits <= 0; Y11_JPEG_LSBs <= 0;
565 
                end
566 
        else if (enable_3) begin
567 
                Y11_bits <= Y11_msb ? Y11_bits_neg : Y11_bits_pos;
568 
                Y11_JPEG_LSBs <= Y11_amp[10:0]; // The top bit of Y11_amp is the sign bit
569 
                end
570 
end
571 
 
572 
always @(posedge clk)
573 
begin
574 
        if (rst) begin
575 
                Y12_bits <= 0; Y12_JPEG_LSBs <= 0; zrl_1 <= 0;
576 
                Y12_et_zero_2 <= 0;
577 
                end
578 
        else if (enable_module) begin
579 
                Y12_bits <= Y12_msb_1 ? Y12_bits_neg : Y12_bits_pos;
580 
                Y12_JPEG_LSBs <= Y12_amp[9:0]; // The top bit of Y12_amp is the sign bit
581 
                zrl_1 <= block_counter == 62 & Y12_et_zero ? 0 : zero_run_length;
582 
                Y12_et_zero_2 <= Y12_et_zero_1;
583 
                end
584 
end
585 
 
586 
// Y11_amp is the amplitude that will be represented in bits in the
587 
// JPEG code, following the run length code
588 
always @(posedge clk)
589 
begin
590 
        if (rst) begin
591 
                Y11_amp <= 0;
592 
                end
593 
        else if (enable_2) begin
594 
                Y11_amp <= Y11_msb ? Y11_1_neg : Y11_1_pos;
595 
                end
596 
end
597 
 
598 
 
599 
always @(posedge clk)
600 
begin
601 
        if (rst)
602 
                zero_run_length <= 0;
603 
        else if (enable)
604 
                zero_run_length <= 0;
605 
        else if (enable_module)
606 
                zero_run_length <= Y12_et_zero ? zero_run_length + 1: 0;
607 
end
608 
 
609 
always @(posedge clk)
610 
begin
611 
        if (rst) begin
612 
                Y12_amp <= 0;
613 
                Y12_et_zero_1 <= 0; Y12_msb_1 <= 0;
614 
                end
615 
        else if (enable_module) begin
616 
                Y12_amp <= Y12_msb ? Y12_neg : Y12_pos;
617 
                Y12_et_zero_1 <= Y12_et_zero;
618 
                Y12_msb_1 <= Y12_msb;
619 
                end
620 
end
621 
 
622 
always @(posedge clk)
623 
begin
624 
        if (rst) begin
625 
                Y11_1_pos <= 0; Y11_1_neg <= 0; Y11_msb <= 0;
626 
                Y11_previous <= 0;
627 
                end
628 
        else if (enable_1) begin
629 
                Y11_1_pos <= Y11_diff;
630 
                Y11_1_neg <= Y11_diff - 1;
631 
                Y11_msb <= Y11_diff[11];
632 
                Y11_previous <= Y11_1;
633 
                end
634 
end
635 
 
636 
always @(posedge clk)
637 
begin
638 
        if (rst) begin
639 
                Y12_pos <= 0; Y12_neg <= 0; Y12_msb <= 0; Y12_et_zero <= 0;
640 
                Y13_pos <= 0; Y13_neg <= 0; Y13_msb <= 0; Y13_et_zero <= 0;
641 
                Y14_pos <= 0; Y14_neg <= 0; Y14_msb <= 0; Y14_et_zero <= 0;
642 
                Y15_pos <= 0; Y15_neg <= 0; Y15_msb <= 0; Y15_et_zero <= 0;
643 
                Y16_pos <= 0; Y16_neg <= 0; Y16_msb <= 0; Y16_et_zero <= 0;
644 
                Y17_pos <= 0; Y17_neg <= 0; Y17_msb <= 0; Y17_et_zero <= 0;
645 
                Y18_pos <= 0; Y18_neg <= 0; Y18_msb <= 0; Y18_et_zero <= 0;
646 
                Y21_pos <= 0; Y21_neg <= 0; Y21_msb <= 0; Y21_et_zero <= 0;
647 
                Y22_pos <= 0; Y22_neg <= 0; Y22_msb <= 0; Y22_et_zero <= 0;
648 
                Y23_pos <= 0; Y23_neg <= 0; Y23_msb <= 0; Y23_et_zero <= 0;
649 
                Y24_pos <= 0; Y24_neg <= 0; Y24_msb <= 0; Y24_et_zero <= 0;
650 
                Y25_pos <= 0; Y25_neg <= 0; Y25_msb <= 0; Y25_et_zero <= 0;
651 
                Y26_pos <= 0; Y26_neg <= 0; Y26_msb <= 0; Y26_et_zero <= 0;
652 
                Y27_pos <= 0; Y27_neg <= 0; Y27_msb <= 0; Y27_et_zero <= 0;
653 
                Y28_pos <= 0; Y28_neg <= 0; Y28_msb <= 0; Y28_et_zero <= 0;
654 
                Y31_pos <= 0; Y31_neg <= 0; Y31_msb <= 0; Y31_et_zero <= 0;
655 
                Y32_pos <= 0; Y32_neg <= 0; Y32_msb <= 0; Y32_et_zero <= 0;
656 
                Y33_pos <= 0; Y33_neg <= 0; Y33_msb <= 0; Y33_et_zero <= 0;
657 
                Y34_pos <= 0; Y34_neg <= 0; Y34_msb <= 0; Y34_et_zero <= 0;
658 
                Y35_pos <= 0; Y35_neg <= 0; Y35_msb <= 0; Y35_et_zero <= 0;
659 
                Y36_pos <= 0; Y36_neg <= 0; Y36_msb <= 0; Y36_et_zero <= 0;
660 
                Y37_pos <= 0; Y37_neg <= 0; Y37_msb <= 0; Y37_et_zero <= 0;
661 
                Y38_pos <= 0; Y38_neg <= 0; Y38_msb <= 0; Y38_et_zero <= 0;
662 
                Y41_pos <= 0; Y41_neg <= 0; Y41_msb <= 0; Y41_et_zero <= 0;
663 
                Y42_pos <= 0; Y42_neg <= 0; Y42_msb <= 0; Y42_et_zero <= 0;
664 
                Y43_pos <= 0; Y43_neg <= 0; Y43_msb <= 0; Y43_et_zero <= 0;
665 
                Y44_pos <= 0; Y44_neg <= 0; Y44_msb <= 0; Y44_et_zero <= 0;
666 
                Y45_pos <= 0; Y45_neg <= 0; Y45_msb <= 0; Y45_et_zero <= 0;
667 
                Y46_pos <= 0; Y46_neg <= 0; Y46_msb <= 0; Y46_et_zero <= 0;
668 
                Y47_pos <= 0; Y47_neg <= 0; Y47_msb <= 0; Y47_et_zero <= 0;
669 
                Y48_pos <= 0; Y48_neg <= 0; Y48_msb <= 0; Y48_et_zero <= 0;
670 
                Y51_pos <= 0; Y51_neg <= 0; Y51_msb <= 0; Y51_et_zero <= 0;
671 
                Y52_pos <= 0; Y52_neg <= 0; Y52_msb <= 0; Y52_et_zero <= 0;
672 
                Y53_pos <= 0; Y53_neg <= 0; Y53_msb <= 0; Y53_et_zero <= 0;
673 
                Y54_pos <= 0; Y54_neg <= 0; Y54_msb <= 0; Y54_et_zero <= 0;
674 
                Y55_pos <= 0; Y55_neg <= 0; Y55_msb <= 0; Y55_et_zero <= 0;
675 
                Y56_pos <= 0; Y56_neg <= 0; Y56_msb <= 0; Y56_et_zero <= 0;
676 
                Y57_pos <= 0; Y57_neg <= 0; Y57_msb <= 0; Y57_et_zero <= 0;
677 
                Y58_pos <= 0; Y58_neg <= 0; Y58_msb <= 0; Y58_et_zero <= 0;
678 
                Y61_pos <= 0; Y61_neg <= 0; Y61_msb <= 0; Y61_et_zero <= 0;
679 
                Y62_pos <= 0; Y62_neg <= 0; Y62_msb <= 0; Y62_et_zero <= 0;
680 
                Y63_pos <= 0; Y63_neg <= 0; Y63_msb <= 0; Y63_et_zero <= 0;
681 
                Y64_pos <= 0; Y64_neg <= 0; Y64_msb <= 0; Y64_et_zero <= 0;
682 
                Y65_pos <= 0; Y65_neg <= 0; Y65_msb <= 0; Y65_et_zero <= 0;
683 
                Y66_pos <= 0; Y66_neg <= 0; Y66_msb <= 0; Y66_et_zero <= 0;
684 
                Y67_pos <= 0; Y67_neg <= 0; Y67_msb <= 0; Y67_et_zero <= 0;
685 
                Y68_pos <= 0; Y68_neg <= 0; Y68_msb <= 0; Y68_et_zero <= 0;
686 
                Y71_pos <= 0; Y71_neg <= 0; Y71_msb <= 0; Y71_et_zero <= 0;
687 
                Y72_pos <= 0; Y72_neg <= 0; Y72_msb <= 0; Y72_et_zero <= 0;
688 
                Y73_pos <= 0; Y73_neg <= 0; Y73_msb <= 0; Y73_et_zero <= 0;
689 
                Y74_pos <= 0; Y74_neg <= 0; Y74_msb <= 0; Y74_et_zero <= 0;
690 
                Y75_pos <= 0; Y75_neg <= 0; Y75_msb <= 0; Y75_et_zero <= 0;
691 
                Y76_pos <= 0; Y76_neg <= 0; Y76_msb <= 0; Y76_et_zero <= 0;
692 
                Y77_pos <= 0; Y77_neg <= 0; Y77_msb <= 0; Y77_et_zero <= 0;
693 
                Y78_pos <= 0; Y78_neg <= 0; Y78_msb <= 0; Y78_et_zero <= 0;
694 
                Y81_pos <= 0; Y81_neg <= 0; Y81_msb <= 0; Y81_et_zero <= 0;
695 
                Y82_pos <= 0; Y82_neg <= 0; Y82_msb <= 0; Y82_et_zero <= 0;
696 
                Y83_pos <= 0; Y83_neg <= 0; Y83_msb <= 0; Y83_et_zero <= 0;
697 
                Y84_pos <= 0; Y84_neg <= 0; Y84_msb <= 0; Y84_et_zero <= 0;
698 
                Y85_pos <= 0; Y85_neg <= 0; Y85_msb <= 0; Y85_et_zero <= 0;
699 
                Y86_pos <= 0; Y86_neg <= 0; Y86_msb <= 0; Y86_et_zero <= 0;
700 
                Y87_pos <= 0; Y87_neg <= 0; Y87_msb <= 0; Y87_et_zero <= 0;
701 
                Y88_pos <= 0; Y88_neg <= 0; Y88_msb <= 0; Y88_et_zero <= 0;
702 
                end
703 
        else if (enable) begin
704 
                Y12_pos <= Y12;
705 
                Y12_neg <= Y12 - 1;
706 
                Y12_msb <= Y12[10];
707 
                Y12_et_zero <= !(|Y12);
708 
                Y13_pos <= Y13;
709 
                Y13_neg <= Y13 - 1;
710 
                Y13_msb <= Y13[10];
711 
                Y13_et_zero <= !(|Y13);
712 
                Y14_pos <= Y14;
713 
                Y14_neg <= Y14 - 1;
714 
                Y14_msb <= Y14[10];
715 
                Y14_et_zero <= !(|Y14);
716 
                Y15_pos <= Y15;
717 
                Y15_neg <= Y15 - 1;
718 
                Y15_msb <= Y15[10];
719 
                Y15_et_zero <= !(|Y15);
720 
                Y16_pos <= Y16;
721 
                Y16_neg <= Y16 - 1;
722 
                Y16_msb <= Y16[10];
723 
                Y16_et_zero <= !(|Y16);
724 
                Y17_pos <= Y17;
725 
                Y17_neg <= Y17 - 1;
726 
                Y17_msb <= Y17[10];
727 
                Y17_et_zero <= !(|Y17);
728 
                Y18_pos <= Y18;
729 
                Y18_neg <= Y18 - 1;
730 
                Y18_msb <= Y18[10];
731 
                Y18_et_zero <= !(|Y18);
732 
                Y21_pos <= Y21;
733 
                Y21_neg <= Y21 - 1;
734 
                Y21_msb <= Y21[10];
735 
                Y21_et_zero <= !(|Y21);
736 
                Y22_pos <= Y22;
737 
                Y22_neg <= Y22 - 1;
738 
                Y22_msb <= Y22[10];
739 
                Y22_et_zero <= !(|Y22);
740 
                Y23_pos <= Y23;
741 
                Y23_neg <= Y23 - 1;
742 
                Y23_msb <= Y23[10];
743 
                Y23_et_zero <= !(|Y23);
744 
                Y24_pos <= Y24;
745 
                Y24_neg <= Y24 - 1;
746 
                Y24_msb <= Y24[10];
747 
                Y24_et_zero <= !(|Y24);
748 
                Y25_pos <= Y25;
749 
                Y25_neg <= Y25 - 1;
750 
                Y25_msb <= Y25[10];
751 
                Y25_et_zero <= !(|Y25);
752 
                Y26_pos <= Y26;
753 
                Y26_neg <= Y26 - 1;
754 
                Y26_msb <= Y26[10];
755 
                Y26_et_zero <= !(|Y26);
756 
                Y27_pos <= Y27;
757 
                Y27_neg <= Y27 - 1;
758 
                Y27_msb <= Y27[10];
759 
                Y27_et_zero <= !(|Y27);
760 
                Y28_pos <= Y28;
761 
                Y28_neg <= Y28 - 1;
762 
                Y28_msb <= Y28[10];
763 
                Y28_et_zero <= !(|Y28);
764 
                Y31_pos <= Y31;
765 
                Y31_neg <= Y31 - 1;
766 
                Y31_msb <= Y31[10];
767 
                Y31_et_zero <= !(|Y31);
768 
                Y32_pos <= Y32;
769 
                Y32_neg <= Y32 - 1;
770 
                Y32_msb <= Y32[10];
771 
                Y32_et_zero <= !(|Y32);
772 
                Y33_pos <= Y33;
773 
                Y33_neg <= Y33 - 1;
774 
                Y33_msb <= Y33[10];
775 
                Y33_et_zero <= !(|Y33);
776 
                Y34_pos <= Y34;
777 
                Y34_neg <= Y34 - 1;
778 
                Y34_msb <= Y34[10];
779 
                Y34_et_zero <= !(|Y34);
780 
                Y35_pos <= Y35;
781 
                Y35_neg <= Y35 - 1;
782 
                Y35_msb <= Y35[10];
783 
                Y35_et_zero <= !(|Y35);
784 
                Y36_pos <= Y36;
785 
                Y36_neg <= Y36 - 1;
786 
                Y36_msb <= Y36[10];
787 
                Y36_et_zero <= !(|Y36);
788 
                Y37_pos <= Y37;
789 
                Y37_neg <= Y37 - 1;
790 
                Y37_msb <= Y37[10];
791 
                Y37_et_zero <= !(|Y37);
792 
                Y38_pos <= Y38;
793 
                Y38_neg <= Y38 - 1;
794 
                Y38_msb <= Y38[10];
795 
                Y38_et_zero <= !(|Y38);
796 
                Y41_pos <= Y41;
797 
                Y41_neg <= Y41 - 1;
798 
                Y41_msb <= Y41[10];
799 
                Y41_et_zero <= !(|Y41);
800 
                Y42_pos <= Y42;
801 
                Y42_neg <= Y42 - 1;
802 
                Y42_msb <= Y42[10];
803 
                Y42_et_zero <= !(|Y42);
804 
                Y43_pos <= Y43;
805 
                Y43_neg <= Y43 - 1;
806 
                Y43_msb <= Y43[10];
807 
                Y43_et_zero <= !(|Y43);
808 
                Y44_pos <= Y44;
809 
                Y44_neg <= Y44 - 1;
810 
                Y44_msb <= Y44[10];
811 
                Y44_et_zero <= !(|Y44);
812 
                Y45_pos <= Y45;
813 
                Y45_neg <= Y45 - 1;
814 
                Y45_msb <= Y45[10];
815 
                Y45_et_zero <= !(|Y45);
816 
                Y46_pos <= Y46;
817 
                Y46_neg <= Y46 - 1;
818 
                Y46_msb <= Y46[10];
819 
                Y46_et_zero <= !(|Y46);
820 
                Y47_pos <= Y47;
821 
                Y47_neg <= Y47 - 1;
822 
                Y47_msb <= Y47[10];
823 
                Y47_et_zero <= !(|Y47);
824 
                Y48_pos <= Y48;
825 
                Y48_neg <= Y48 - 1;
826 
                Y48_msb <= Y48[10];
827 
                Y48_et_zero <= !(|Y48);
828 
                Y51_pos <= Y51;
829 
                Y51_neg <= Y51 - 1;
830 
                Y51_msb <= Y51[10];
831 
                Y51_et_zero <= !(|Y51);
832 
                Y52_pos <= Y52;
833 
                Y52_neg <= Y52 - 1;
834 
                Y52_msb <= Y52[10];
835 
                Y52_et_zero <= !(|Y52);
836 
                Y53_pos <= Y53;
837 
                Y53_neg <= Y53 - 1;
838 
                Y53_msb <= Y53[10];
839 
                Y53_et_zero <= !(|Y53);
840 
                Y54_pos <= Y54;
841 
                Y54_neg <= Y54 - 1;
842 
                Y54_msb <= Y54[10];
843 
                Y54_et_zero <= !(|Y54);
844 
                Y55_pos <= Y55;
845 
                Y55_neg <= Y55 - 1;
846 
                Y55_msb <= Y55[10];
847 
                Y55_et_zero <= !(|Y55);
848 
                Y56_pos <= Y56;
849 
                Y56_neg <= Y56 - 1;
850 
                Y56_msb <= Y56[10];
851 
                Y56_et_zero <= !(|Y56);
852 
                Y57_pos <= Y57;
853 
                Y57_neg <= Y57 - 1;
854 
                Y57_msb <= Y57[10];
855 
                Y57_et_zero <= !(|Y57);
856 
                Y58_pos <= Y58;
857 
                Y58_neg <= Y58 - 1;
858 
                Y58_msb <= Y58[10];
859 
                Y58_et_zero <= !(|Y58);
860 
                Y61_pos <= Y61;
861 
                Y61_neg <= Y61 - 1;
862 
                Y61_msb <= Y61[10];
863 
                Y61_et_zero <= !(|Y61);
864 
                Y62_pos <= Y62;
865 
                Y62_neg <= Y62 - 1;
866 
                Y62_msb <= Y62[10];
867 
                Y62_et_zero <= !(|Y62);
868 
                Y63_pos <= Y63;
869 
                Y63_neg <= Y63 - 1;
870 
                Y63_msb <= Y63[10];
871 
                Y63_et_zero <= !(|Y63);
872 
                Y64_pos <= Y64;
873 
                Y64_neg <= Y64 - 1;
874 
                Y64_msb <= Y64[10];
875 
                Y64_et_zero <= !(|Y64);
876 
                Y65_pos <= Y65;
877 
                Y65_neg <= Y65 - 1;
878 
                Y65_msb <= Y65[10];
879 
                Y65_et_zero <= !(|Y65);
880 
                Y66_pos <= Y66;
881 
                Y66_neg <= Y66 - 1;
882 
                Y66_msb <= Y66[10];
883 
                Y66_et_zero <= !(|Y66);
884 
                Y67_pos <= Y67;
885 
                Y67_neg <= Y67 - 1;
886 
                Y67_msb <= Y67[10];
887 
                Y67_et_zero <= !(|Y67);
888 
                Y68_pos <= Y68;
889 
                Y68_neg <= Y68 - 1;
890 
                Y68_msb <= Y68[10];
891 
                Y68_et_zero <= !(|Y68);
892 
                Y71_pos <= Y71;
893 
                Y71_neg <= Y71 - 1;
894 
                Y71_msb <= Y71[10];
895 
                Y71_et_zero <= !(|Y71);
896 
                Y72_pos <= Y72;
897 
                Y72_neg <= Y72 - 1;
898 
                Y72_msb <= Y72[10];
899 
                Y72_et_zero <= !(|Y72);
900 
                Y73_pos <= Y73;
901 
                Y73_neg <= Y73 - 1;
902 
                Y73_msb <= Y73[10];
903 
                Y73_et_zero <= !(|Y73);
904 
                Y74_pos <= Y74;
905 
                Y74_neg <= Y74 - 1;
906 
                Y74_msb <= Y74[10];
907 
                Y74_et_zero <= !(|Y74);
908 
                Y75_pos <= Y75;
909 
                Y75_neg <= Y75 - 1;
910 
                Y75_msb <= Y75[10];
911 
                Y75_et_zero <= !(|Y75);
912 
                Y76_pos <= Y76;
913 
                Y76_neg <= Y76 - 1;
914 
                Y76_msb <= Y76[10];
915 
                Y76_et_zero <= !(|Y76);
916 
                Y77_pos <= Y77;
917 
                Y77_neg <= Y77 - 1;
918 
                Y77_msb <= Y77[10];
919 
                Y77_et_zero <= !(|Y77);
920 
                Y78_pos <= Y78;
921 
                Y78_neg <= Y78 - 1;
922 
                Y78_msb <= Y78[10];
923 
                Y78_et_zero <= !(|Y78);
924 
                Y81_pos <= Y81;
925 
                Y81_neg <= Y81 - 1;
926 
                Y81_msb <= Y81[10];
927 
                Y81_et_zero <= !(|Y81);
928 
                Y82_pos <= Y82;
929 
                Y82_neg <= Y82 - 1;
930 
                Y82_msb <= Y82[10];
931 
                Y82_et_zero <= !(|Y82);
932 
                Y83_pos <= Y83;
933 
                Y83_neg <= Y83 - 1;
934 
                Y83_msb <= Y83[10];
935 
                Y83_et_zero <= !(|Y83);
936 
                Y84_pos <= Y84;
937 
                Y84_neg <= Y84 - 1;
938 
                Y84_msb <= Y84[10];
939 
                Y84_et_zero <= !(|Y84);
940 
                Y85_pos <= Y85;
941 
                Y85_neg <= Y85 - 1;
942 
                Y85_msb <= Y85[10];
943 
                Y85_et_zero <= !(|Y85);
944 
                Y86_pos <= Y86;
945 
                Y86_neg <= Y86 - 1;
946 
                Y86_msb <= Y86[10];
947 
                Y86_et_zero <= !(|Y86);
948 
                Y87_pos <= Y87;
949 
                Y87_neg <= Y87 - 1;
950 
                Y87_msb <= Y87[10];
951 
                Y87_et_zero <= !(|Y87);
952 
                Y88_pos <= Y88;
953 
                Y88_neg <= Y88 - 1;
954 
                Y88_msb <= Y88[10];
955 
                Y88_et_zero <= !(|Y88);
956 
                end
957 
        else if (enable_module) begin
958 
                Y12_pos <= Y21_pos;
959 
                Y12_neg <= Y21_neg;
960 
                Y12_msb <= Y21_msb;
961 
                Y12_et_zero <= Y21_et_zero;
962 
                Y21_pos <= Y31_pos;
963 
                Y21_neg <= Y31_neg;
964 
                Y21_msb <= Y31_msb;
965 
                Y21_et_zero <= Y31_et_zero;
966 
                Y31_pos <= Y22_pos;
967 
                Y31_neg <= Y22_neg;
968 
                Y31_msb <= Y22_msb;
969 
                Y31_et_zero <= Y22_et_zero;
970 
                Y22_pos <= Y13_pos;
971 
                Y22_neg <= Y13_neg;
972 
                Y22_msb <= Y13_msb;
973 
                Y22_et_zero <= Y13_et_zero;
974 
                Y13_pos <= Y14_pos;
975 
                Y13_neg <= Y14_neg;
976 
                Y13_msb <= Y14_msb;
977 
                Y13_et_zero <= Y14_et_zero;
978 
                Y14_pos <= Y23_pos;
979 
                Y14_neg <= Y23_neg;
980 
                Y14_msb <= Y23_msb;
981 
                Y14_et_zero <= Y23_et_zero;
982 
                Y23_pos <= Y32_pos;
983 
                Y23_neg <= Y32_neg;
984 
                Y23_msb <= Y32_msb;
985 
                Y23_et_zero <= Y32_et_zero;
986 
                Y32_pos <= Y41_pos;
987 
                Y32_neg <= Y41_neg;
988 
                Y32_msb <= Y41_msb;
989 
                Y32_et_zero <= Y41_et_zero;
990 
                Y41_pos <= Y51_pos;
991 
                Y41_neg <= Y51_neg;
992 
                Y41_msb <= Y51_msb;
993 
                Y41_et_zero <= Y51_et_zero;
994 
                Y51_pos <= Y42_pos;
995 
                Y51_neg <= Y42_neg;
996 
                Y51_msb <= Y42_msb;
997 
                Y51_et_zero <= Y42_et_zero;
998 
                Y42_pos <= Y33_pos;
999 
                Y42_neg <= Y33_neg;
1000 
                Y42_msb <= Y33_msb;
1001 
                Y42_et_zero <= Y33_et_zero;
1002 
                Y33_pos <= Y24_pos;
1003 
                Y33_neg <= Y24_neg;
1004 
                Y33_msb <= Y24_msb;
1005 
                Y33_et_zero <= Y24_et_zero;
1006 
                Y24_pos <= Y15_pos;
1007 
                Y24_neg <= Y15_neg;
1008 
                Y24_msb <= Y15_msb;
1009 
                Y24_et_zero <= Y15_et_zero;
1010 
                Y15_pos <= Y16_pos;
1011 
                Y15_neg <= Y16_neg;
1012 
                Y15_msb <= Y16_msb;
1013 
                Y15_et_zero <= Y16_et_zero;
1014 
                Y16_pos <= Y25_pos;
1015 
                Y16_neg <= Y25_neg;
1016 
                Y16_msb <= Y25_msb;
1017 
                Y16_et_zero <= Y25_et_zero;
1018 
                Y25_pos <= Y34_pos;
1019 
                Y25_neg <= Y34_neg;
1020 
                Y25_msb <= Y34_msb;
1021 
                Y25_et_zero <= Y34_et_zero;
1022 
                Y34_pos <= Y43_pos;
1023 
                Y34_neg <= Y43_neg;
1024 
                Y34_msb <= Y43_msb;
1025 
                Y34_et_zero <= Y43_et_zero;
1026 
                Y43_pos <= Y52_pos;
1027 
                Y43_neg <= Y52_neg;
1028 
                Y43_msb <= Y52_msb;
1029 
                Y43_et_zero <= Y52_et_zero;
1030 
                Y52_pos <= Y61_pos;
1031 
                Y52_neg <= Y61_neg;
1032 
                Y52_msb <= Y61_msb;
1033 
                Y52_et_zero <= Y61_et_zero;
1034 
                Y61_pos <= Y71_pos;
1035 
                Y61_neg <= Y71_neg;
1036 
                Y61_msb <= Y71_msb;
1037 
                Y61_et_zero <= Y71_et_zero;
1038 
                Y71_pos <= Y62_pos;
1039 
                Y71_neg <= Y62_neg;
1040 
                Y71_msb <= Y62_msb;
1041 
                Y71_et_zero <= Y62_et_zero;
1042 
                Y62_pos <= Y53_pos;
1043 
                Y62_neg <= Y53_neg;
1044 
                Y62_msb <= Y53_msb;
1045 
                Y62_et_zero <= Y53_et_zero;
1046 
                Y53_pos <= Y44_pos;
1047 
                Y53_neg <= Y44_neg;
1048 
                Y53_msb <= Y44_msb;
1049 
                Y53_et_zero <= Y44_et_zero;
1050 
                Y44_pos <= Y35_pos;
1051 
                Y44_neg <= Y35_neg;
1052 
                Y44_msb <= Y35_msb;
1053 
                Y44_et_zero <= Y35_et_zero;
1054 
                Y35_pos <= Y26_pos;
1055 
                Y35_neg <= Y26_neg;
1056 
                Y35_msb <= Y26_msb;
1057 
                Y35_et_zero <= Y26_et_zero;
1058 
                Y26_pos <= Y17_pos;
1059 
                Y26_neg <= Y17_neg;
1060 
                Y26_msb <= Y17_msb;
1061 
                Y26_et_zero <= Y17_et_zero;
1062 
                Y17_pos <= Y18_pos;
1063 
                Y17_neg <= Y18_neg;
1064 
                Y17_msb <= Y18_msb;
1065 
                Y17_et_zero <= Y18_et_zero;
1066 
                Y18_pos <= Y27_pos;
1067 
                Y18_neg <= Y27_neg;
1068 
                Y18_msb <= Y27_msb;
1069 
                Y18_et_zero <= Y27_et_zero;
1070 
                Y27_pos <= Y36_pos;
1071 
                Y27_neg <= Y36_neg;
1072 
                Y27_msb <= Y36_msb;
1073 
                Y27_et_zero <= Y36_et_zero;
1074 
                Y36_pos <= Y45_pos;
1075 
                Y36_neg <= Y45_neg;
1076 
                Y36_msb <= Y45_msb;
1077 
                Y36_et_zero <= Y45_et_zero;
1078 
                Y45_pos <= Y54_pos;
1079 
                Y45_neg <= Y54_neg;
1080 
                Y45_msb <= Y54_msb;
1081 
                Y45_et_zero <= Y54_et_zero;
1082 
                Y54_pos <= Y63_pos;
1083 
                Y54_neg <= Y63_neg;
1084 
                Y54_msb <= Y63_msb;
1085 
                Y54_et_zero <= Y63_et_zero;
1086 
                Y63_pos <= Y72_pos;
1087 
                Y63_neg <= Y72_neg;
1088 
                Y63_msb <= Y72_msb;
1089 
                Y63_et_zero <= Y72_et_zero;
1090 
                Y72_pos <= Y81_pos;
1091 
                Y72_neg <= Y81_neg;
1092 
                Y72_msb <= Y81_msb;
1093 
                Y72_et_zero <= Y81_et_zero;
1094 
                Y81_pos <= Y82_pos;
1095 
                Y81_neg <= Y82_neg;
1096 
                Y81_msb <= Y82_msb;
1097 
                Y81_et_zero <= Y82_et_zero;
1098 
                Y82_pos <= Y73_pos;
1099 
                Y82_neg <= Y73_neg;
1100 
                Y82_msb <= Y73_msb;
1101 
                Y82_et_zero <= Y73_et_zero;
1102 
                Y73_pos <= Y64_pos;
1103 
                Y73_neg <= Y64_neg;
1104 
                Y73_msb <= Y64_msb;
1105 
                Y73_et_zero <= Y64_et_zero;
1106 
                Y64_pos <= Y55_pos;
1107 
                Y64_neg <= Y55_neg;
1108 
                Y64_msb <= Y55_msb;
1109 
                Y64_et_zero <= Y55_et_zero;
1110 
                Y55_pos <= Y46_pos;
1111 
                Y55_neg <= Y46_neg;
1112 
                Y55_msb <= Y46_msb;
1113 
                Y55_et_zero <= Y46_et_zero;
1114 
                Y46_pos <= Y37_pos;
1115 
                Y46_neg <= Y37_neg;
1116 
                Y46_msb <= Y37_msb;
1117 
                Y46_et_zero <= Y37_et_zero;
1118 
                Y37_pos <= Y28_pos;
1119 
                Y37_neg <= Y28_neg;
1120 
                Y37_msb <= Y28_msb;
1121 
                Y37_et_zero <= Y28_et_zero;
1122 
                Y28_pos <= Y38_pos;
1123 
                Y28_neg <= Y38_neg;
1124 
                Y28_msb <= Y38_msb;
1125 
                Y28_et_zero <= Y38_et_zero;
1126 
                Y38_pos <= Y47_pos;
1127 
                Y38_neg <= Y47_neg;
1128 
                Y38_msb <= Y47_msb;
1129 
                Y38_et_zero <= Y47_et_zero;
1130 
                Y47_pos <= Y56_pos;
1131 
                Y47_neg <= Y56_neg;
1132 
                Y47_msb <= Y56_msb;
1133 
                Y47_et_zero <= Y56_et_zero;
1134 
                Y56_pos <= Y65_pos;
1135 
                Y56_neg <= Y65_neg;
1136 
                Y56_msb <= Y65_msb;
1137 
                Y56_et_zero <= Y65_et_zero;
1138 
                Y65_pos <= Y74_pos;
1139 
                Y65_neg <= Y74_neg;
1140 
                Y65_msb <= Y74_msb;
1141 
                Y65_et_zero <= Y74_et_zero;
1142 
                Y74_pos <= Y83_pos;
1143 
                Y74_neg <= Y83_neg;
1144 
                Y74_msb <= Y83_msb;
1145 
                Y74_et_zero <= Y83_et_zero;
1146 
                Y83_pos <= Y84_pos;
1147 
                Y83_neg <= Y84_neg;
1148 
                Y83_msb <= Y84_msb;
1149 
                Y83_et_zero <= Y84_et_zero;
1150 
                Y84_pos <= Y75_pos;
1151 
                Y84_neg <= Y75_neg;
1152 
                Y84_msb <= Y75_msb;
1153 
                Y84_et_zero <= Y75_et_zero;
1154 
                Y75_pos <= Y66_pos;
1155 
                Y75_neg <= Y66_neg;
1156 
                Y75_msb <= Y66_msb;
1157 
                Y75_et_zero <= Y66_et_zero;
1158 
                Y66_pos <= Y57_pos;
1159 
                Y66_neg <= Y57_neg;
1160 
                Y66_msb <= Y57_msb;
1161 
                Y66_et_zero <= Y57_et_zero;
1162 
                Y57_pos <= Y48_pos;
1163 
                Y57_neg <= Y48_neg;
1164 
                Y57_msb <= Y48_msb;
1165 
                Y57_et_zero <= Y48_et_zero;
1166 
                Y48_pos <= Y58_pos;
1167 
                Y48_neg <= Y58_neg;
1168 
                Y48_msb <= Y58_msb;
1169 
                Y48_et_zero <= Y58_et_zero;
1170 
                Y58_pos <= Y67_pos;
1171 
                Y58_neg <= Y67_neg;
1172 
                Y58_msb <= Y67_msb;
1173 
                Y58_et_zero <= Y67_et_zero;
1174 
                Y67_pos <= Y76_pos;
1175 
                Y67_neg <= Y76_neg;
1176 
                Y67_msb <= Y76_msb;
1177 
                Y67_et_zero <= Y76_et_zero;
1178 
                Y76_pos <= Y85_pos;
1179 
                Y76_neg <= Y85_neg;
1180 
                Y76_msb <= Y85_msb;
1181 
                Y76_et_zero <= Y85_et_zero;
1182 
                Y85_pos <= Y86_pos;
1183 
                Y85_neg <= Y86_neg;
1184 
                Y85_msb <= Y86_msb;
1185 
                Y85_et_zero <= Y86_et_zero;
1186 
                Y86_pos <= Y77_pos;
1187 
                Y86_neg <= Y77_neg;
1188 
                Y86_msb <= Y77_msb;
1189 
                Y86_et_zero <= Y77_et_zero;
1190 
                Y77_pos <= Y68_pos;
1191 
                Y77_neg <= Y68_neg;
1192 
                Y77_msb <= Y68_msb;
1193 
                Y77_et_zero <= Y68_et_zero;
1194 
                Y68_pos <= Y78_pos;
1195 
                Y68_neg <= Y78_neg;
1196 
                Y68_msb <= Y78_msb;
1197 
                Y68_et_zero <= Y78_et_zero;
1198 
                Y78_pos <= Y87_pos;
1199 
                Y78_neg <= Y87_neg;
1200 
                Y78_msb <= Y87_msb;
1201 
                Y78_et_zero <= Y87_et_zero;
1202 
                Y87_pos <= Y88_pos;
1203 
                Y87_neg <= Y88_neg;
1204 
                Y87_msb <= Y88_msb;
1205 
                Y87_et_zero <= Y88_et_zero;
1206 
                Y88_pos <= 0;
1207 
                Y88_neg <= 0;
1208 
                Y88_msb <= 0;
1209 
                Y88_et_zero <= 1;
1210 
                end
1211 
end
1212 
 
1213 
always @(posedge clk)
1214 
begin
1215 
        if (rst) begin
1216 
                Y11_diff <= 0; Y11_1 <= 0;
1217 
                end
1218 
        else if (enable) begin // Need to sign extend Y11 to 12 bits
1219 
                Y11_diff <= {Y11[10], Y11} - Y11_previous;
1220 
                Y11_1 <= Y11[10] ? { 1'b1, Y11 } : { 1'b0, Y11 };
1221 
                end
1222 
end
1223 
 
1224 
always @(posedge clk)
1225 
begin
1226 
        if (rst)
1227 
                Y11_bits_pos <= 0;
1228 
        else if (Y11_1_pos[10] == 1)
1229 
                Y11_bits_pos <= 11;
1230 
        else if (Y11_1_pos[9] == 1)
1231 
                Y11_bits_pos <= 10;
1232 
        else if (Y11_1_pos[8] == 1)
1233 
                Y11_bits_pos <= 9;
1234 
        else if (Y11_1_pos[7] == 1)
1235 
                Y11_bits_pos <= 8;
1236 
        else if (Y11_1_pos[6] == 1)
1237 
                Y11_bits_pos <= 7;
1238 
        else if (Y11_1_pos[5] == 1)
1239 
                Y11_bits_pos <= 6;
1240 
        else if (Y11_1_pos[4] == 1)
1241 
                Y11_bits_pos <= 5;
1242 
        else if (Y11_1_pos[3] == 1)
1243 
                Y11_bits_pos <= 4;
1244 
        else if (Y11_1_pos[2] == 1)
1245 
                Y11_bits_pos <= 3;
1246 
        else if (Y11_1_pos[1] == 1)
1247 
                Y11_bits_pos <= 2;
1248 
        else if (Y11_1_pos[0] == 1)
1249 
                Y11_bits_pos <= 1;
1250 
        else
1251 
                Y11_bits_pos <= 0;
1252 
end
1253 
 
1254 
always @(posedge clk)
1255 
begin
1256 
        if (rst)
1257 
                Y11_bits_neg <= 0;
1258 
        else if (Y11_1_neg[10] == 0)
1259 
                Y11_bits_neg <= 11;
1260 
        else if (Y11_1_neg[9] == 0)
1261 
                Y11_bits_neg <= 10;
1262 
        else if (Y11_1_neg[8] == 0)
1263 
                Y11_bits_neg <= 9;
1264 
        else if (Y11_1_neg[7] == 0)
1265 
                Y11_bits_neg <= 8;
1266 
        else if (Y11_1_neg[6] == 0)
1267 
                Y11_bits_neg <= 7;
1268 
        else if (Y11_1_neg[5] == 0)
1269 
                Y11_bits_neg <= 6;
1270 
        else if (Y11_1_neg[4] == 0)
1271 
                Y11_bits_neg <= 5;
1272 
        else if (Y11_1_neg[3] == 0)
1273 
                Y11_bits_neg <= 4;
1274 
        else if (Y11_1_neg[2] == 0)
1275 
                Y11_bits_neg <= 3;
1276 
        else if (Y11_1_neg[1] == 0)
1277 
                Y11_bits_neg <= 2;
1278 
        else if (Y11_1_neg[0] == 0)
1279 
                Y11_bits_neg <= 1;
1280 
        else
1281 
                Y11_bits_neg <= 0;
1282 
end
1283 
 
1284 
 
1285 
always @(posedge clk)
1286 
begin
1287 
        if (rst)
1288 
                Y12_bits_pos <= 0;
1289 
        else if (Y12_pos[9] == 1)
1290 
                Y12_bits_pos <= 10;
1291 
        else if (Y12_pos[8] == 1)
1292 
                Y12_bits_pos <= 9;
1293 
        else if (Y12_pos[7] == 1)
1294 
                Y12_bits_pos <= 8;
1295 
        else if (Y12_pos[6] == 1)
1296 
                Y12_bits_pos <= 7;
1297 
        else if (Y12_pos[5] == 1)
1298 
                Y12_bits_pos <= 6;
1299 
        else if (Y12_pos[4] == 1)
1300 
                Y12_bits_pos <= 5;
1301 
        else if (Y12_pos[3] == 1)
1302 
                Y12_bits_pos <= 4;
1303 
        else if (Y12_pos[2] == 1)
1304 
                Y12_bits_pos <= 3;
1305 
        else if (Y12_pos[1] == 1)
1306 
                Y12_bits_pos <= 2;
1307 
        else if (Y12_pos[0] == 1)
1308 
                Y12_bits_pos <= 1;
1309 
        else
1310 
                Y12_bits_pos <= 0;
1311 
end
1312 
 
1313 
always @(posedge clk)
1314 
begin
1315 
        if (rst)
1316 
                Y12_bits_neg <= 0;
1317 
        else if (Y12_neg[9] == 0)
1318 
                Y12_bits_neg <= 10;
1319 
        else if (Y12_neg[8] == 0)
1320 
                Y12_bits_neg <= 9;
1321 
        else if (Y12_neg[7] == 0)
1322 
                Y12_bits_neg <= 8;
1323 
        else if (Y12_neg[6] == 0)
1324 
                Y12_bits_neg <= 7;
1325 
        else if (Y12_neg[5] == 0)
1326 
                Y12_bits_neg <= 6;
1327 
        else if (Y12_neg[4] == 0)
1328 
                Y12_bits_neg <= 5;
1329 
        else if (Y12_neg[3] == 0)
1330 
                Y12_bits_neg <= 4;
1331 
        else if (Y12_neg[2] == 0)
1332 
                Y12_bits_neg <= 3;
1333 
        else if (Y12_neg[1] == 0)
1334 
                Y12_bits_neg <= 2;
1335 
        else if (Y12_neg[0] == 0)
1336 
                Y12_bits_neg <= 1;
1337 
        else
1338 
                Y12_bits_neg <= 0;
1339 
end
1340 
 
1341 
always @(posedge clk)
1342 
begin
1343 
        if (rst) begin
1344 
                enable_module <= 0;
1345 
                end
1346 
        else if (enable) begin
1347 
                enable_module <= 1;
1348 
                end
1349 
end
1350 
 
1351 
always @(posedge clk)
1352 
begin
1353 
        if (rst) begin
1354 
                enable_latch_7 <= 0;
1355 
                end
1356 
        else if (block_counter == 68)  begin
1357 
                enable_latch_7 <= 0;
1358 
                end
1359 
        else if (enable_6) begin
1360 
                enable_latch_7 <= 1;
1361 
                end
1362 
end
1363 
 
1364 
always @(posedge clk)
1365 
begin
1366 
        if (rst) begin
1367 
                enable_latch_8 <= 0;
1368 
                end
1369 
        else if (enable_7) begin
1370 
                enable_latch_8 <= 1;
1371 
                end
1372 
end
1373 
 
1374 
always @(posedge clk)
1375 
begin
1376 
        if (rst) begin
1377 
                enable_1 <= 0; enable_2 <= 0; enable_3 <= 0;
1378 
                enable_4 <= 0; enable_5 <= 0; enable_6 <= 0;
1379 
                enable_7 <= 0; enable_8 <= 0; enable_9 <= 0;
1380 
                enable_10 <= 0; enable_11 <= 0; enable_12 <= 0;
1381 
                enable_13 <= 0;
1382 
                end
1383 
        else begin
1384 
                enable_1 <= enable; enable_2 <= enable_1; enable_3 <= enable_2;
1385 
                enable_4 <= enable_3; enable_5 <= enable_4; enable_6 <= enable_5;
1386 
                enable_7 <= enable_6; enable_8 <= enable_7; enable_9 <= enable_8;
1387 
                enable_10 <= enable_9; enable_11 <= enable_10; enable_12 <= enable_11;
1388 
                enable_13 <= enable_12;
1389 
                end
1390 
end
1391 
 
1392 
/* These Y DC and AC code lengths, run lengths, and bit codes
1393 
were created from the Huffman table entries in the JPEG file header.
1394 
For different Huffman tables for different images, these values
1395 
below will need to be changed.  I created a matlab file to automatically
1396 
create these entries from the already encoded JPEG image. This matlab program
1397 
won't be any help if you're starting from scratch with a .tif or other
1398 
raw image file format.  The values below come from a Huffman table, they
1399 
do not actually create the Huffman table based on the probabilities of
1400 
each code created from the image data.  You will need another program to
1401 
create the optimal Huffman table, or you can go with a generic Huffman table,
1402 
which will have slightly less than the best compression.*/
1403 
 
1404 
 
1405 
always @(posedge clk)
1406 
begin
1407 
        Y_DC_code_length[0] <= 2;
1408 
Y_DC_code_length[1] <= 2;
1409 
Y_DC_code_length[2] <= 2;
1410 
Y_DC_code_length[3] <= 3;
1411 
Y_DC_code_length[4] <= 4;
1412 
Y_DC_code_length[5] <= 5;
1413 
Y_DC_code_length[6] <= 6;
1414 
Y_DC_code_length[7] <= 7;
1415 
Y_DC_code_length[8] <= 8;
1416 
Y_DC_code_length[9] <= 9;
1417 
Y_DC_code_length[10] <= 10;
1418 
Y_DC_code_length[11] <= 11;
1419 
Y_DC[0] <= 11'b00000000000;
1420 
Y_DC[1] <= 11'b01000000000;
1421 
Y_DC[2] <= 11'b10000000000;
1422 
Y_DC[3] <= 11'b11000000000;
1423 
Y_DC[4] <= 11'b11100000000;
1424 
Y_DC[5] <= 11'b11110000000;
1425 
Y_DC[6] <= 11'b11111000000;
1426 
Y_DC[7] <= 11'b11111100000;
1427 
Y_DC[8] <= 11'b11111110000;
1428 
Y_DC[9] <= 11'b11111111000;
1429 
Y_DC[10] <= 11'b11111111100;
1430 
Y_DC[11] <= 11'b11111111110;
1431 
Y_AC_code_length[0] <= 2;
1432 
Y_AC_code_length[1] <= 2;
1433 
Y_AC_code_length[2] <= 3;
1434 
Y_AC_code_length[3] <= 4;
1435 
Y_AC_code_length[4] <= 4;
1436 
Y_AC_code_length[5] <= 4;
1437 
Y_AC_code_length[6] <= 5;
1438 
Y_AC_code_length[7] <= 5;
1439 
Y_AC_code_length[8] <= 5;
1440 
Y_AC_code_length[9] <= 6;
1441 
Y_AC_code_length[10] <= 6;
1442 
Y_AC_code_length[11] <= 7;
1443 
Y_AC_code_length[12] <= 7;
1444 
Y_AC_code_length[13] <= 7;
1445 
Y_AC_code_length[14] <= 7;
1446 
Y_AC_code_length[15] <= 8;
1447 
Y_AC_code_length[16] <= 8;
1448 
Y_AC_code_length[17] <= 8;
1449 
Y_AC_code_length[18] <= 9;
1450 
Y_AC_code_length[19] <= 9;
1451 
Y_AC_code_length[20] <= 9;
1452 
Y_AC_code_length[21] <= 9;
1453 
Y_AC_code_length[22] <= 9;
1454 
Y_AC_code_length[23] <= 10;
1455 
Y_AC_code_length[24] <= 10;
1456 
Y_AC_code_length[25] <= 10;
1457 
Y_AC_code_length[26] <= 10;
1458 
Y_AC_code_length[27] <= 10;
1459 
Y_AC_code_length[28] <= 11;
1460 
Y_AC_code_length[29] <= 11;
1461 
Y_AC_code_length[30] <= 11;
1462 
Y_AC_code_length[31] <= 11;
1463 
Y_AC_code_length[32] <= 12;
1464 
Y_AC_code_length[33] <= 12;
1465 
Y_AC_code_length[34] <= 12;
1466 
Y_AC_code_length[35] <= 12;
1467 
Y_AC_code_length[36] <= 15;
1468 
Y_AC_code_length[37] <= 16;
1469 
Y_AC_code_length[38] <= 16;
1470 
Y_AC_code_length[39] <= 16;
1471 
Y_AC_code_length[40] <= 16;
1472 
Y_AC_code_length[41] <= 16;
1473 
Y_AC_code_length[42] <= 16;
1474 
Y_AC_code_length[43] <= 16;
1475 
Y_AC_code_length[44] <= 16;
1476 
Y_AC_code_length[45] <= 16;
1477 
Y_AC_code_length[46] <= 16;
1478 
Y_AC_code_length[47] <= 16;
1479 
Y_AC_code_length[48] <= 16;
1480 
Y_AC_code_length[49] <= 16;
1481 
Y_AC_code_length[50] <= 16;
1482 
Y_AC_code_length[51] <= 16;
1483 
Y_AC_code_length[52] <= 16;
1484 
Y_AC_code_length[53] <= 16;
1485 
Y_AC_code_length[54] <= 16;
1486 
Y_AC_code_length[55] <= 16;
1487 
Y_AC_code_length[56] <= 16;
1488 
Y_AC_code_length[57] <= 16;
1489 
Y_AC_code_length[58] <= 16;
1490 
Y_AC_code_length[59] <= 16;
1491 
Y_AC_code_length[60] <= 16;
1492 
Y_AC_code_length[61] <= 16;
1493 
Y_AC_code_length[62] <= 16;
1494 
Y_AC_code_length[63] <= 16;
1495 
Y_AC_code_length[64] <= 16;
1496 
Y_AC_code_length[65] <= 16;
1497 
Y_AC_code_length[66] <= 16;
1498 
Y_AC_code_length[67] <= 16;
1499 
Y_AC_code_length[68] <= 16;
1500 
Y_AC_code_length[69] <= 16;
1501 
Y_AC_code_length[70] <= 16;
1502 
Y_AC_code_length[71] <= 16;
1503 
Y_AC_code_length[72] <= 16;
1504 
Y_AC_code_length[73] <= 16;
1505 
Y_AC_code_length[74] <= 16;
1506 
Y_AC_code_length[75] <= 16;
1507 
Y_AC_code_length[76] <= 16;
1508 
Y_AC_code_length[77] <= 16;
1509 
Y_AC_code_length[78] <= 16;
1510 
Y_AC_code_length[79] <= 16;
1511 
Y_AC_code_length[80] <= 16;
1512 
Y_AC_code_length[81] <= 16;
1513 
Y_AC_code_length[82] <= 16;
1514 
Y_AC_code_length[83] <= 16;
1515 
Y_AC_code_length[84] <= 16;
1516 
Y_AC_code_length[85] <= 16;
1517 
Y_AC_code_length[86] <= 16;
1518 
Y_AC_code_length[87] <= 16;
1519 
Y_AC_code_length[88] <= 16;
1520 
Y_AC_code_length[89] <= 16;
1521 
Y_AC_code_length[90] <= 16;
1522 
Y_AC_code_length[91] <= 16;
1523 
Y_AC_code_length[92] <= 16;
1524 
Y_AC_code_length[93] <= 16;
1525 
Y_AC_code_length[94] <= 16;
1526 
Y_AC_code_length[95] <= 16;
1527 
Y_AC_code_length[96] <= 16;
1528 
Y_AC_code_length[97] <= 16;
1529 
Y_AC_code_length[98] <= 16;
1530 
Y_AC_code_length[99] <= 16;
1531 
Y_AC_code_length[100] <= 16;
1532 
Y_AC_code_length[101] <= 16;
1533 
Y_AC_code_length[102] <= 16;
1534 
Y_AC_code_length[103] <= 16;
1535 
Y_AC_code_length[104] <= 16;
1536 
Y_AC_code_length[105] <= 16;
1537 
Y_AC_code_length[106] <= 16;
1538 
Y_AC_code_length[107] <= 16;
1539 
Y_AC_code_length[108] <= 16;
1540 
Y_AC_code_length[109] <= 16;
1541 
Y_AC_code_length[110] <= 16;
1542 
Y_AC_code_length[111] <= 16;
1543 
Y_AC_code_length[112] <= 16;
1544 
Y_AC_code_length[113] <= 16;
1545 
Y_AC_code_length[114] <= 16;
1546 
Y_AC_code_length[115] <= 16;
1547 
Y_AC_code_length[116] <= 16;
1548 
Y_AC_code_length[117] <= 16;
1549 
Y_AC_code_length[118] <= 16;
1550 
Y_AC_code_length[119] <= 16;
1551 
Y_AC_code_length[120] <= 16;
1552 
Y_AC_code_length[121] <= 16;
1553 
Y_AC_code_length[122] <= 16;
1554 
Y_AC_code_length[123] <= 16;
1555 
Y_AC_code_length[124] <= 16;
1556 
Y_AC_code_length[125] <= 16;
1557 
Y_AC_code_length[126] <= 16;
1558 
Y_AC_code_length[127] <= 16;
1559 
Y_AC_code_length[128] <= 16;
1560 
Y_AC_code_length[129] <= 16;
1561 
Y_AC_code_length[130] <= 16;
1562 
Y_AC_code_length[131] <= 16;
1563 
Y_AC_code_length[132] <= 16;
1564 
Y_AC_code_length[133] <= 16;
1565 
Y_AC_code_length[134] <= 16;
1566 
Y_AC_code_length[135] <= 16;
1567 
Y_AC_code_length[136] <= 16;
1568 
Y_AC_code_length[137] <= 16;
1569 
Y_AC_code_length[138] <= 16;
1570 
Y_AC_code_length[139] <= 16;
1571 
Y_AC_code_length[140] <= 16;
1572 
Y_AC_code_length[141] <= 16;
1573 
Y_AC_code_length[142] <= 16;
1574 
Y_AC_code_length[143] <= 16;
1575 
Y_AC_code_length[144] <= 16;
1576 
Y_AC_code_length[145] <= 16;
1577 
Y_AC_code_length[146] <= 16;
1578 
Y_AC_code_length[147] <= 16;
1579 
Y_AC_code_length[148] <= 16;
1580 
Y_AC_code_length[149] <= 16;
1581 
Y_AC_code_length[150] <= 16;
1582 
Y_AC_code_length[151] <= 16;
1583 
Y_AC_code_length[152] <= 16;
1584 
Y_AC_code_length[153] <= 16;
1585 
Y_AC_code_length[154] <= 16;
1586 
Y_AC_code_length[155] <= 16;
1587 
Y_AC_code_length[156] <= 16;
1588 
Y_AC_code_length[157] <= 16;
1589 
Y_AC_code_length[158] <= 16;
1590 
Y_AC_code_length[159] <= 16;
1591 
Y_AC_code_length[160] <= 16;
1592 
Y_AC_code_length[161] <= 16;
1593 
Y_AC[0] <= 16'b0000000000000000;
1594 
Y_AC[1] <= 16'b0100000000000000;
1595 
Y_AC[2] <= 16'b1000000000000000;
1596 
Y_AC[3] <= 16'b1010000000000000;
1597 
Y_AC[4] <= 16'b1011000000000000;
1598 
Y_AC[5] <= 16'b1100000000000000;
1599 
Y_AC[6] <= 16'b1101000000000000;
1600 
Y_AC[7] <= 16'b1101100000000000;
1601 
Y_AC[8] <= 16'b1110000000000000;
1602 
Y_AC[9] <= 16'b1110100000000000;
1603 
Y_AC[10] <= 16'b1110110000000000;
1604 
Y_AC[11] <= 16'b1111000000000000;
1605 
Y_AC[12] <= 16'b1111001000000000;
1606 
Y_AC[13] <= 16'b1111010000000000;
1607 
Y_AC[14] <= 16'b1111011000000000;
1608 
Y_AC[15] <= 16'b1111100000000000;
1609 
Y_AC[16] <= 16'b1111100100000000;
1610 
Y_AC[17] <= 16'b1111101000000000;
1611 
Y_AC[18] <= 16'b1111101100000000;
1612 
Y_AC[19] <= 16'b1111101110000000;
1613 
Y_AC[20] <= 16'b1111110000000000;
1614 
Y_AC[21] <= 16'b1111110010000000;
1615 
Y_AC[22] <= 16'b1111110100000000;
1616 
Y_AC[23] <= 16'b1111110110000000;
1617 
Y_AC[24] <= 16'b1111110111000000;
1618 
Y_AC[25] <= 16'b1111111000000000;
1619 
Y_AC[26] <= 16'b1111111001000000;
1620 
Y_AC[27] <= 16'b1111111010000000;
1621 
Y_AC[28] <= 16'b1111111011000000;
1622 
Y_AC[29] <= 16'b1111111011100000;
1623 
Y_AC[30] <= 16'b1111111100000000;
1624 
Y_AC[31] <= 16'b1111111100100000;
1625 
Y_AC[32] <= 16'b1111111101000000;
1626 
Y_AC[33] <= 16'b1111111101010000;
1627 
Y_AC[34] <= 16'b1111111101100000;
1628 
Y_AC[35] <= 16'b1111111101110000;
1629 
Y_AC[36] <= 16'b1111111110000000;
1630 
Y_AC[37] <= 16'b1111111110000010;
1631 
Y_AC[38] <= 16'b1111111110000011;
1632 
Y_AC[39] <= 16'b1111111110000100;
1633 
Y_AC[40] <= 16'b1111111110000101;
1634 
Y_AC[41] <= 16'b1111111110000110;
1635 
Y_AC[42] <= 16'b1111111110000111;
1636 
Y_AC[43] <= 16'b1111111110001000;
1637 
Y_AC[44] <= 16'b1111111110001001;
1638 
Y_AC[45] <= 16'b1111111110001010;
1639 
Y_AC[46] <= 16'b1111111110001011;
1640 
Y_AC[47] <= 16'b1111111110001100;
1641 
Y_AC[48] <= 16'b1111111110001101;
1642 
Y_AC[49] <= 16'b1111111110001110;
1643 
Y_AC[50] <= 16'b1111111110001111;
1644 
Y_AC[51] <= 16'b1111111110010000;
1645 
Y_AC[52] <= 16'b1111111110010001;
1646 
Y_AC[53] <= 16'b1111111110010010;
1647 
Y_AC[54] <= 16'b1111111110010011;
1648 
Y_AC[55] <= 16'b1111111110010100;
1649 
Y_AC[56] <= 16'b1111111110010101;
1650 
Y_AC[57] <= 16'b1111111110010110;
1651 
Y_AC[58] <= 16'b1111111110010111;
1652 
Y_AC[59] <= 16'b1111111110011000;
1653 
Y_AC[60] <= 16'b1111111110011001;
1654 
Y_AC[61] <= 16'b1111111110011010;
1655 
Y_AC[62] <= 16'b1111111110011011;
1656 
Y_AC[63] <= 16'b1111111110011100;
1657 
Y_AC[64] <= 16'b1111111110011101;
1658 
Y_AC[65] <= 16'b1111111110011110;
1659 
Y_AC[66] <= 16'b1111111110011111;
1660 
Y_AC[67] <= 16'b1111111110100000;
1661 
Y_AC[68] <= 16'b1111111110100001;
1662 
Y_AC[69] <= 16'b1111111110100010;
1663 
Y_AC[70] <= 16'b1111111110100011;
1664 
Y_AC[71] <= 16'b1111111110100100;
1665 
Y_AC[72] <= 16'b1111111110100101;
1666 
Y_AC[73] <= 16'b1111111110100110;
1667 
Y_AC[74] <= 16'b1111111110100111;
1668 
Y_AC[75] <= 16'b1111111110101000;
1669 
Y_AC[76] <= 16'b1111111110101001;
1670 
Y_AC[77] <= 16'b1111111110101010;
1671 
Y_AC[78] <= 16'b1111111110101011;
1672 
Y_AC[79] <= 16'b1111111110101100;
1673 
Y_AC[80] <= 16'b1111111110101101;
1674 
Y_AC[81] <= 16'b1111111110101110;
1675 
Y_AC[82] <= 16'b1111111110101111;
1676 
Y_AC[83] <= 16'b1111111110110000;
1677 
Y_AC[84] <= 16'b1111111110110001;
1678 
Y_AC[85] <= 16'b1111111110110010;
1679 
Y_AC[86] <= 16'b1111111110110011;
1680 
Y_AC[87] <= 16'b1111111110110100;
1681 
Y_AC[88] <= 16'b1111111110110101;
1682 
Y_AC[89] <= 16'b1111111110110110;
1683 
Y_AC[90] <= 16'b1111111110110111;
1684 
Y_AC[91] <= 16'b1111111110111000;
1685 
Y_AC[92] <= 16'b1111111110111001;
1686 
Y_AC[93] <= 16'b1111111110111010;
1687 
Y_AC[94] <= 16'b1111111110111011;
1688 
Y_AC[95] <= 16'b1111111110111100;
1689 
Y_AC[96] <= 16'b1111111110111101;
1690 
Y_AC[97] <= 16'b1111111110111110;
1691 
Y_AC[98] <= 16'b1111111110111111;
1692 
Y_AC[99] <= 16'b1111111111000000;
1693 
Y_AC[100] <= 16'b1111111111000001;
1694 
Y_AC[101] <= 16'b1111111111000010;
1695 
Y_AC[102] <= 16'b1111111111000011;
1696 
Y_AC[103] <= 16'b1111111111000100;
1697 
Y_AC[104] <= 16'b1111111111000101;
1698 
Y_AC[105] <= 16'b1111111111000110;
1699 
Y_AC[106] <= 16'b1111111111000111;
1700 
Y_AC[107] <= 16'b1111111111001000;
1701 
Y_AC[108] <= 16'b1111111111001001;
1702 
Y_AC[109] <= 16'b1111111111001010;
1703 
Y_AC[110] <= 16'b1111111111001011;
1704 
Y_AC[111] <= 16'b1111111111001100;
1705 
Y_AC[112] <= 16'b1111111111001101;
1706 
Y_AC[113] <= 16'b1111111111001110;
1707 
Y_AC[114] <= 16'b1111111111001111;
1708 
Y_AC[115] <= 16'b1111111111010000;
1709 
Y_AC[116] <= 16'b1111111111010001;
1710 
Y_AC[117] <= 16'b1111111111010010;
1711 
Y_AC[118] <= 16'b1111111111010011;
1712 
Y_AC[119] <= 16'b1111111111010100;
1713 
Y_AC[120] <= 16'b1111111111010101;
1714 
Y_AC[121] <= 16'b1111111111010110;
1715 
Y_AC[122] <= 16'b1111111111010111;
1716 
Y_AC[123] <= 16'b1111111111011000;
1717 
Y_AC[124] <= 16'b1111111111011001;
1718 
Y_AC[125] <= 16'b1111111111011010;
1719 
Y_AC[126] <= 16'b1111111111011011;
1720 
Y_AC[127] <= 16'b1111111111011100;
1721 
Y_AC[128] <= 16'b1111111111011101;
1722 
Y_AC[129] <= 16'b1111111111011110;
1723 
Y_AC[130] <= 16'b1111111111011111;
1724 
Y_AC[131] <= 16'b1111111111100000;
1725 
Y_AC[132] <= 16'b1111111111100001;
1726 
Y_AC[133] <= 16'b1111111111100010;
1727 
Y_AC[134] <= 16'b1111111111100011;
1728 
Y_AC[135] <= 16'b1111111111100100;
1729 
Y_AC[136] <= 16'b1111111111100101;
1730 
Y_AC[137] <= 16'b1111111111100110;
1731 
Y_AC[138] <= 16'b1111111111100111;
1732 
Y_AC[139] <= 16'b1111111111101000;
1733 
Y_AC[140] <= 16'b1111111111101001;
1734 
Y_AC[141] <= 16'b1111111111101010;
1735 
Y_AC[142] <= 16'b1111111111101011;
1736 
Y_AC[143] <= 16'b1111111111101100;
1737 
Y_AC[144] <= 16'b1111111111101101;
1738 
Y_AC[145] <= 16'b1111111111101110;
1739 
Y_AC[146] <= 16'b1111111111101111;
1740 
Y_AC[147] <= 16'b1111111111110000;
1741 
Y_AC[148] <= 16'b1111111111110001;
1742 
Y_AC[149] <= 16'b1111111111110010;
1743 
Y_AC[150] <= 16'b1111111111110011;
1744 
Y_AC[151] <= 16'b1111111111110100;
1745 
Y_AC[152] <= 16'b1111111111110101;
1746 
Y_AC[153] <= 16'b1111111111110110;
1747 
Y_AC[154] <= 16'b1111111111110111;
1748 
Y_AC[155] <= 16'b1111111111111000;
1749 
Y_AC[156] <= 16'b1111111111111001;
1750 
Y_AC[157] <= 16'b1111111111111010;
1751 
Y_AC[158] <= 16'b1111111111111011;
1752 
Y_AC[159] <= 16'b1111111111111100;
1753 
Y_AC[160] <= 16'b1111111111111101;
1754 
Y_AC[161] <= 16'b1111111111111110;
1755 
Y_AC_run_code[1] <= 0;
1756 
Y_AC_run_code[2] <= 1;
1757 
Y_AC_run_code[3] <= 2;
1758 
Y_AC_run_code[0] <= 3;
1759 
Y_AC_run_code[4] <= 4;
1760 
Y_AC_run_code[17] <= 5;
1761 
Y_AC_run_code[5] <= 6;
1762 
Y_AC_run_code[18] <= 7;
1763 
Y_AC_run_code[33] <= 8;
1764 
Y_AC_run_code[49] <= 9;
1765 
Y_AC_run_code[65] <= 10;
1766 
Y_AC_run_code[6] <= 11;
1767 
Y_AC_run_code[19] <= 12;
1768 
Y_AC_run_code[81] <= 13;
1769 
Y_AC_run_code[97] <= 14;
1770 
Y_AC_run_code[7] <= 15;
1771 
Y_AC_run_code[34] <= 16;
1772 
Y_AC_run_code[113] <= 17;
1773 
Y_AC_run_code[20] <= 18;
1774 
Y_AC_run_code[50] <= 19;
1775 
Y_AC_run_code[129] <= 20;
1776 
Y_AC_run_code[145] <= 21;
1777 
Y_AC_run_code[161] <= 22;
1778 
Y_AC_run_code[8] <= 23;
1779 
Y_AC_run_code[35] <= 24;
1780 
Y_AC_run_code[66] <= 25;
1781 
Y_AC_run_code[177] <= 26;
1782 
Y_AC_run_code[193] <= 27;
1783 
Y_AC_run_code[21] <= 28;
1784 
Y_AC_run_code[82] <= 29;
1785 
Y_AC_run_code[209] <= 30;
1786 
Y_AC_run_code[240] <= 31;
1787 
Y_AC_run_code[36] <= 32;
1788 
Y_AC_run_code[51] <= 33;
1789 
Y_AC_run_code[98] <= 34;
1790 
Y_AC_run_code[114] <= 35;
1791 
Y_AC_run_code[130] <= 36;
1792 
Y_AC_run_code[9] <= 37;
1793 
Y_AC_run_code[10] <= 38;
1794 
Y_AC_run_code[22] <= 39;
1795 
Y_AC_run_code[23] <= 40;
1796 
Y_AC_run_code[24] <= 41;
1797 
Y_AC_run_code[25] <= 42;
1798 
Y_AC_run_code[26] <= 43;
1799 
Y_AC_run_code[37] <= 44;
1800 
Y_AC_run_code[38] <= 45;
1801 
Y_AC_run_code[39] <= 46;
1802 
Y_AC_run_code[40] <= 47;
1803 
Y_AC_run_code[41] <= 48;
1804 
Y_AC_run_code[42] <= 49;
1805 
Y_AC_run_code[52] <= 50;
1806 
Y_AC_run_code[53] <= 51;
1807 
Y_AC_run_code[54] <= 52;
1808 
Y_AC_run_code[55] <= 53;
1809 
Y_AC_run_code[56] <= 54;
1810 
Y_AC_run_code[57] <= 55;
1811 
Y_AC_run_code[58] <= 56;
1812 
Y_AC_run_code[67] <= 57;
1813 
Y_AC_run_code[68] <= 58;
1814 
Y_AC_run_code[69] <= 59;
1815 
Y_AC_run_code[70] <= 60;
1816 
Y_AC_run_code[71] <= 61;
1817 
Y_AC_run_code[72] <= 62;
1818 
Y_AC_run_code[73] <= 63;
1819 
Y_AC_run_code[74] <= 64;
1820 
Y_AC_run_code[83] <= 65;
1821 
Y_AC_run_code[84] <= 66;
1822 
Y_AC_run_code[85] <= 67;
1823 
Y_AC_run_code[86] <= 68;
1824 
Y_AC_run_code[87] <= 69;
1825 
Y_AC_run_code[88] <= 70;
1826 
Y_AC_run_code[89] <= 71;
1827 
Y_AC_run_code[90] <= 72;
1828 
Y_AC_run_code[99] <= 73;
1829 
Y_AC_run_code[100] <= 74;
1830 
Y_AC_run_code[101] <= 75;
1831 
Y_AC_run_code[102] <= 76;
1832 
Y_AC_run_code[103] <= 77;
1833 
Y_AC_run_code[104] <= 78;
1834 
Y_AC_run_code[105] <= 79;
1835 
Y_AC_run_code[106] <= 80;
1836 
Y_AC_run_code[115] <= 81;
1837 
Y_AC_run_code[116] <= 82;
1838 
Y_AC_run_code[117] <= 83;
1839 
Y_AC_run_code[118] <= 84;
1840 
Y_AC_run_code[119] <= 85;
1841 
Y_AC_run_code[120] <= 86;
1842 
Y_AC_run_code[121] <= 87;
1843 
Y_AC_run_code[122] <= 88;
1844 
Y_AC_run_code[131] <= 89;
1845 
Y_AC_run_code[132] <= 90;
1846 
Y_AC_run_code[133] <= 91;
1847 
Y_AC_run_code[134] <= 92;
1848 
Y_AC_run_code[135] <= 93;
1849 
Y_AC_run_code[136] <= 94;
1850 
Y_AC_run_code[137] <= 95;
1851 
Y_AC_run_code[138] <= 96;
1852 
Y_AC_run_code[146] <= 97;
1853 
Y_AC_run_code[147] <= 98;
1854 
Y_AC_run_code[148] <= 99;
1855 
Y_AC_run_code[149] <= 100;
1856 
Y_AC_run_code[150] <= 101;
1857 
Y_AC_run_code[151] <= 102;
1858 
Y_AC_run_code[152] <= 103;
1859 
Y_AC_run_code[153] <= 104;
1860 
Y_AC_run_code[154] <= 105;
1861 
Y_AC_run_code[162] <= 106;
1862 
Y_AC_run_code[163] <= 107;
1863 
Y_AC_run_code[164] <= 108;
1864 
Y_AC_run_code[165] <= 109;
1865 
Y_AC_run_code[166] <= 110;
1866 
Y_AC_run_code[167] <= 111;
1867 
Y_AC_run_code[168] <= 112;
1868 
Y_AC_run_code[169] <= 113;
1869 
Y_AC_run_code[170] <= 114;
1870 
Y_AC_run_code[178] <= 115;
1871 
Y_AC_run_code[179] <= 116;
1872 
Y_AC_run_code[180] <= 117;
1873 
Y_AC_run_code[181] <= 118;
1874 
Y_AC_run_code[182] <= 119;
1875 
Y_AC_run_code[183] <= 120;
1876 
Y_AC_run_code[184] <= 121;
1877 
Y_AC_run_code[185] <= 122;
1878 
Y_AC_run_code[186] <= 123;
1879 
Y_AC_run_code[194] <= 124;
1880 
Y_AC_run_code[195] <= 125;
1881 
Y_AC_run_code[196] <= 126;
1882 
Y_AC_run_code[197] <= 127;
1883 
Y_AC_run_code[198] <= 128;
1884 
Y_AC_run_code[199] <= 129;
1885 
Y_AC_run_code[200] <= 130;
1886 
Y_AC_run_code[201] <= 131;
1887 
Y_AC_run_code[202] <= 132;
1888 
Y_AC_run_code[210] <= 133;
1889 
Y_AC_run_code[211] <= 134;
1890 
Y_AC_run_code[212] <= 135;
1891 
Y_AC_run_code[213] <= 136;
1892 
Y_AC_run_code[214] <= 137;
1893 
Y_AC_run_code[215] <= 138;
1894 
Y_AC_run_code[216] <= 139;
1895 
Y_AC_run_code[217] <= 140;
1896 
Y_AC_run_code[218] <= 141;
1897 
Y_AC_run_code[225] <= 142;
1898 
Y_AC_run_code[226] <= 143;
1899 
Y_AC_run_code[227] <= 144;
1900 
Y_AC_run_code[228] <= 145;
1901 
Y_AC_run_code[229] <= 146;
1902 
Y_AC_run_code[230] <= 147;
1903 
Y_AC_run_code[231] <= 148;
1904 
Y_AC_run_code[232] <= 149;
1905 
Y_AC_run_code[233] <= 150;
1906 
Y_AC_run_code[234] <= 151;
1907 
Y_AC_run_code[241] <= 152;
1908 
Y_AC_run_code[242] <= 153;
1909 
Y_AC_run_code[243] <= 154;
1910 
Y_AC_run_code[244] <= 155;
1911 
Y_AC_run_code[245] <= 156;
1912 
Y_AC_run_code[246] <= 157;
1913 
Y_AC_run_code[247] <= 158;
1914 
Y_AC_run_code[248] <= 159;
1915 
Y_AC_run_code[249] <= 160;
1916 
Y_AC_run_code[250] <= 161;
1917 
        Y_AC_run_code[16] <= 0;
1918 
        Y_AC_run_code[32] <= 0;
1919 
        Y_AC_run_code[48] <= 0;
1920 
        Y_AC_run_code[64] <= 0;
1921 
        Y_AC_run_code[80] <= 0;
1922 
        Y_AC_run_code[96] <= 0;
1923 
        Y_AC_run_code[112] <= 0;
1924 
        Y_AC_run_code[128] <= 0;
1925 
        Y_AC_run_code[144] <= 0;
1926 
        Y_AC_run_code[160] <= 0;
1927 
        Y_AC_run_code[176] <= 0;
1928 
        Y_AC_run_code[192] <= 0;
1929 
        Y_AC_run_code[208] <= 0;
1930 
        Y_AC_run_code[224] <= 0;
1931 
end
1932 
 
1933 
 
1934 
always @(posedge clk)
1935 
begin
1936 
        if (rst)
1937 
                JPEG_bitstream[31] <= 0;
1938 
        else if (enable_module && rollover_7)
1939 
                JPEG_bitstream[31] <= JPEG_bs_5[31];
1940 
        else if (enable_module && orc_8 == 0)
1941 
                JPEG_bitstream[31] <= JPEG_bs_5[31];
1942 
end
1943 
 
1944 
always @(posedge clk)
1945 
begin
1946 
        if (rst)
1947 
                JPEG_bitstream[30] <= 0;
1948 
        else if (enable_module && rollover_7)
1949 
                JPEG_bitstream[30] <= JPEG_bs_5[30];
1950 
        else if (enable_module && orc_8 <= 1)
1951 
                JPEG_bitstream[30] <= JPEG_bs_5[30];
1952 
end
1953 
 
1954 
always @(posedge clk)
1955 
begin
1956 
        if (rst)
1957 
                JPEG_bitstream[29] <= 0;
1958 
        else if (enable_module && rollover_7)
1959 
                JPEG_bitstream[29] <= JPEG_bs_5[29];
1960 
        else if (enable_module && orc_8 <= 2)
1961 
                JPEG_bitstream[29] <= JPEG_bs_5[29];
1962 
end
1963 
 
1964 
always @(posedge clk)
1965 
begin
1966 
        if (rst)
1967 
                JPEG_bitstream[28] <= 0;
1968 
        else if (enable_module && rollover_7)
1969 
                JPEG_bitstream[28] <= JPEG_bs_5[28];
1970 
        else if (enable_module && orc_8 <= 3)
1971 
                JPEG_bitstream[28] <= JPEG_bs_5[28];
1972 
end
1973 
 
1974 
always @(posedge clk)
1975 
begin
1976 
        if (rst)
1977 
                JPEG_bitstream[27] <= 0;
1978 
        else if (enable_module && rollover_7)
1979 
                JPEG_bitstream[27] <= JPEG_bs_5[27];
1980 
        else if (enable_module && orc_8 <= 4)
1981 
                JPEG_bitstream[27] <= JPEG_bs_5[27];
1982 
end
1983 
 
1984 
always @(posedge clk)
1985 
begin
1986 
        if (rst)
1987 
                JPEG_bitstream[26] <= 0;
1988 
        else if (enable_module && rollover_7)
1989 
                JPEG_bitstream[26] <= JPEG_bs_5[26];
1990 
        else if (enable_module && orc_8 <= 5)
1991 
                JPEG_bitstream[26] <= JPEG_bs_5[26];
1992 
end
1993 
 
1994 
always @(posedge clk)
1995 
begin
1996 
        if (rst)
1997 
                JPEG_bitstream[25] <= 0;
1998 
        else if (enable_module && rollover_7)
1999 
                JPEG_bitstream[25] <= JPEG_bs_5[25];
2000 
        else if (enable_module && orc_8 <= 6)
2001 
                JPEG_bitstream[25] <= JPEG_bs_5[25];
2002 
end
2003 
 
2004 
always @(posedge clk)
2005 
begin
2006 
        if (rst)
2007 
                JPEG_bitstream[24] <= 0;
2008 
        else if (enable_module && rollover_7)
2009 
                JPEG_bitstream[24] <= JPEG_bs_5[24];
2010 
        else if (enable_module && orc_8 <= 7)
2011 
                JPEG_bitstream[24] <= JPEG_bs_5[24];
2012 
end
2013 
 
2014 
always @(posedge clk)
2015 
begin
2016 
        if (rst)
2017 
                JPEG_bitstream[23] <= 0;
2018 
        else if (enable_module && rollover_7)
2019 
                JPEG_bitstream[23] <= JPEG_bs_5[23];
2020 
        else if (enable_module && orc_8 <= 8)
2021 
                JPEG_bitstream[23] <= JPEG_bs_5[23];
2022 
end
2023 
 
2024 
always @(posedge clk)
2025 
begin
2026 
        if (rst)
2027 
                JPEG_bitstream[22] <= 0;
2028 
        else if (enable_module && rollover_7)
2029 
                JPEG_bitstream[22] <= JPEG_bs_5[22];
2030 
        else if (enable_module && orc_8 <= 9)
2031 
                JPEG_bitstream[22] <= JPEG_bs_5[22];
2032 
end
2033 
 
2034 
always @(posedge clk)
2035 
begin
2036 
        if (rst)
2037 
                JPEG_bitstream[21] <= 0;
2038 
        else if (enable_module && rollover_7)
2039 
                JPEG_bitstream[21] <= JPEG_bs_5[21];
2040 
        else if (enable_module && orc_8 <= 10)
2041 
                JPEG_bitstream[21] <= JPEG_bs_5[21];
2042 
end
2043 
 
2044 
always @(posedge clk)
2045 
begin
2046 
        if (rst)
2047 
                JPEG_bitstream[20] <= 0;
2048 
        else if (enable_module && rollover_7)
2049 
                JPEG_bitstream[20] <= JPEG_bs_5[20];
2050 
        else if (enable_module && orc_8 <= 11)
2051 
                JPEG_bitstream[20] <= JPEG_bs_5[20];
2052 
end
2053 
 
2054 
always @(posedge clk)
2055 
begin
2056 
        if (rst)
2057 
                JPEG_bitstream[19] <= 0;
2058 
        else if (enable_module && rollover_7)
2059 
                JPEG_bitstream[19] <= JPEG_bs_5[19];
2060 
        else if (enable_module && orc_8 <= 12)
2061 
                JPEG_bitstream[19] <= JPEG_bs_5[19];
2062 
end
2063 
 
2064 
always @(posedge clk)
2065 
begin
2066 
        if (rst)
2067 
                JPEG_bitstream[18] <= 0;
2068 
        else if (enable_module && rollover_7)
2069 
                JPEG_bitstream[18] <= JPEG_bs_5[18];
2070 
        else if (enable_module && orc_8 <= 13)
2071 
                JPEG_bitstream[18] <= JPEG_bs_5[18];
2072 
end
2073 
 
2074 
always @(posedge clk)
2075 
begin
2076 
        if (rst)
2077 
                JPEG_bitstream[17] <= 0;
2078 
        else if (enable_module && rollover_7)
2079 
                JPEG_bitstream[17] <= JPEG_bs_5[17];
2080 
        else if (enable_module && orc_8 <= 14)
2081 
                JPEG_bitstream[17] <= JPEG_bs_5[17];
2082 
end
2083 
 
2084 
always @(posedge clk)
2085 
begin
2086 
        if (rst)
2087 
                JPEG_bitstream[16] <= 0;
2088 
        else if (enable_module && rollover_7)
2089 
                JPEG_bitstream[16] <= JPEG_bs_5[16];
2090 
        else if (enable_module && orc_8 <= 15)
2091 
                JPEG_bitstream[16] <= JPEG_bs_5[16];
2092 
end
2093 
 
2094 
always @(posedge clk)
2095 
begin
2096 
        if (rst)
2097 
                JPEG_bitstream[15] <= 0;
2098 
        else if (enable_module && rollover_7)
2099 
                JPEG_bitstream[15] <= JPEG_bs_5[15];
2100 
        else if (enable_module && orc_8 <= 16)
2101 
                JPEG_bitstream[15] <= JPEG_bs_5[15];
2102 
end
2103 
 
2104 
always @(posedge clk)
2105 
begin
2106 
        if (rst)
2107 
                JPEG_bitstream[14] <= 0;
2108 
        else if (enable_module && rollover_7)
2109 
                JPEG_bitstream[14] <= JPEG_bs_5[14];
2110 
        else if (enable_module && orc_8 <= 17)
2111 
                JPEG_bitstream[14] <= JPEG_bs_5[14];
2112 
end
2113 
 
2114 
always @(posedge clk)
2115 
begin
2116 
        if (rst)
2117 
                JPEG_bitstream[13] <= 0;
2118 
        else if (enable_module && rollover_7)
2119 
                JPEG_bitstream[13] <= JPEG_bs_5[13];
2120 
        else if (enable_module && orc_8 <= 18)
2121 
                JPEG_bitstream[13] <= JPEG_bs_5[13];
2122 
end
2123 
 
2124 
always @(posedge clk)
2125 
begin
2126 
        if (rst)
2127 
                JPEG_bitstream[12] <= 0;
2128 
        else if (enable_module && rollover_7)
2129 
                JPEG_bitstream[12] <= JPEG_bs_5[12];
2130 
        else if (enable_module && orc_8 <= 19)
2131 
                JPEG_bitstream[12] <= JPEG_bs_5[12];
2132 
end
2133 
 
2134 
always @(posedge clk)
2135 
begin
2136 
        if (rst)
2137 
                JPEG_bitstream[11] <= 0;
2138 
        else if (enable_module && rollover_7)
2139 
                JPEG_bitstream[11] <= JPEG_bs_5[11];
2140 
        else if (enable_module && orc_8 <= 20)
2141 
                JPEG_bitstream[11] <= JPEG_bs_5[11];
2142 
end
2143 
 
2144 
always @(posedge clk)
2145 
begin
2146 
        if (rst)
2147 
                JPEG_bitstream[10] <= 0;
2148 
        else if (enable_module && rollover_7)
2149 
                JPEG_bitstream[10] <= JPEG_bs_5[10];
2150 
        else if (enable_module && orc_8 <= 21)
2151 
                JPEG_bitstream[10] <= JPEG_bs_5[10];
2152 
end
2153 
 
2154 
always @(posedge clk)
2155 
begin
2156 
        if (rst)
2157 
                JPEG_bitstream[9] <= 0;
2158 
        else if (enable_module && rollover_7)
2159 
                JPEG_bitstream[9] <= JPEG_bs_5[9];
2160 
        else if (enable_module && orc_8 <= 22)
2161 
                JPEG_bitstream[9] <= JPEG_bs_5[9];
2162 
end
2163 
 
2164 
always @(posedge clk)
2165 
begin
2166 
        if (rst)
2167 
                JPEG_bitstream[8] <= 0;
2168 
        else if (enable_module && rollover_7)
2169 
                JPEG_bitstream[8] <= JPEG_bs_5[8];
2170 
        else if (enable_module && orc_8 <= 23)
2171 
                JPEG_bitstream[8] <= JPEG_bs_5[8];
2172 
end
2173 
 
2174 
always @(posedge clk)
2175 
begin
2176 
        if (rst)
2177 
                JPEG_bitstream[7] <= 0;
2178 
        else if (enable_module && rollover_7)
2179 
                JPEG_bitstream[7] <= JPEG_bs_5[7];
2180 
        else if (enable_module && orc_8 <= 24)
2181 
                JPEG_bitstream[7] <= JPEG_bs_5[7];
2182 
end
2183 
 
2184 
always @(posedge clk)
2185 
begin
2186 
        if (rst)
2187 
                JPEG_bitstream[6] <= 0;
2188 
        else if (enable_module && rollover_7)
2189 
                JPEG_bitstream[6] <= JPEG_bs_5[6];
2190 
        else if (enable_module && orc_8 <= 25)
2191 
                JPEG_bitstream[6] <= JPEG_bs_5[6];
2192 
end
2193 
 
2194 
always @(posedge clk)
2195 
begin
2196 
        if (rst)
2197 
                JPEG_bitstream[5] <= 0;
2198 
        else if (enable_module && rollover_7)
2199 
                JPEG_bitstream[5] <= JPEG_bs_5[5];
2200 
        else if (enable_module && orc_8 <= 26)
2201 
                JPEG_bitstream[5] <= JPEG_bs_5[5];
2202 
end
2203 
 
2204 
always @(posedge clk)
2205 
begin
2206 
        if (rst)
2207 
                JPEG_bitstream[4] <= 0;
2208 
        else if (enable_module && rollover_7)
2209 
                JPEG_bitstream[4] <= JPEG_bs_5[4];
2210 
        else if (enable_module && orc_8 <= 27)
2211 
                JPEG_bitstream[4] <= JPEG_bs_5[4];
2212 
end
2213 
 
2214 
always @(posedge clk)
2215 
begin
2216 
        if (rst)
2217 
                JPEG_bitstream[3] <= 0;
2218 
        else if (enable_module && rollover_7)
2219 
                JPEG_bitstream[3] <= JPEG_bs_5[3];
2220 
        else if (enable_module && orc_8 <= 28)
2221 
                JPEG_bitstream[3] <= JPEG_bs_5[3];
2222 
end
2223 
 
2224 
always @(posedge clk)
2225 
begin
2226 
        if (rst)
2227 
                JPEG_bitstream[2] <= 0;
2228 
        else if (enable_module && rollover_7)
2229 
                JPEG_bitstream[2] <= JPEG_bs_5[2];
2230 
        else if (enable_module && orc_8 <= 29)
2231 
                JPEG_bitstream[2] <= JPEG_bs_5[2];
2232 
end
2233 
 
2234 
always @(posedge clk)
2235 
begin
2236 
        if (rst)
2237 
                JPEG_bitstream[1] <= 0;
2238 
        else if (enable_module && rollover_7)
2239 
                JPEG_bitstream[1] <= JPEG_bs_5[1];
2240 
        else if (enable_module && orc_8 <= 30)
2241 
                JPEG_bitstream[1] <= JPEG_bs_5[1];
2242 
end
2243 
 
2244 
always @(posedge clk)
2245 
begin
2246 
        if (rst)
2247 
                JPEG_bitstream[0] <= 0;
2248 
        else if (enable_module && rollover_7)
2249 
                JPEG_bitstream[0] <= JPEG_bs_5[0];
2250 
        else if (enable_module && orc_8 <= 31)
2251 
                JPEG_bitstream[0] <= JPEG_bs_5[0];
2252 
end
2253 
endmodule

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