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[/] [jt51/] [trunk/] [jt51/] [jt51.v] - Blame information for rev 2

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/*  This file is part of JT51.
 
    JT51 is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
 
    JT51 is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with JT51.  If not, see <http://www.gnu.org/licenses/>.
 
        Author: Jose Tejada Gomez. Twitter: @topapate
        Version: 1.0
        Date: 27-10-2016
        */
 
`timescale 1ns / 1ps
 
module jt51(
        input                           clk,    // main clock
        input                           rst,    // reset
        input                           cs_n,   // chip select
        input                           wr_n,   // write
        input                           a0,
        input           [7:0]    d_in, // data in
        output          [7:0]    d_out, // data out
        output                          ct1,
        output                          ct2,
        output                          irq_n,  // I do not synchronize this signal
        output  reg             p1,
        // Low resolution output (same as real chip)
        output                          sample, // marks new output sample
        output  signed  [15:0] left,
        output  signed  [15:0] right,
        // Full resolution output
        output  signed  [15:0] xleft,
        output  signed  [15:0] xright,
        // unsigned outputs for sigma delta converters, full resolution
        output  [15:0] dacleft,
        output  [15:0] dacright
);
 
reg rst_p1, rst_p1_aux;
 
assign dacleft  = { ~xleft [15],  xleft[14:0] };
assign dacright = { ~xright[15], xright[14:0] };
 
 
// Generate internal clock and synchronous reset for it.
always @(posedge clk or posedge rst)
        if( rst )
                p1              <= 1'b0;
        else
                p1              <= ~p1;
 
always @(posedge p1 or posedge rst)
        if( rst ) begin
                rst_p1_aux      <= 1'b1;
                rst_p1          <= 1'b1;
        end
        else begin
                rst_p1_aux      <= 1'b0;
                rst_p1          <= rst_p1_aux;
        end
 
// Timers
wire [9:0]       value_A;
wire [7:0]       value_B;
wire            load_A, load_B;
wire            enable_irq_A, enable_irq_B;
wire            clr_flag_A, clr_flag_B;
wire            flag_A, flag_B, overflow_A;
wire            set_run_A, set_run_B;
wire            clr_run_A, clr_run_B;
 
jt51_timers timers(
        .clk            ( clk                   ),
        .rst            ( rst_p1                ),
        .value_A        ( value_A               ),
        .value_B        ( value_B               ),
        .load_A         ( load_A                ),
        .load_B         ( load_B                ),
        .enable_irq_A( enable_irq_A ),
        .enable_irq_B( enable_irq_B ),
        .clr_flag_A     ( clr_flag_A    ),
        .clr_flag_B     ( clr_flag_B    ),
        .set_run_A      ( set_run_A             ),
        .set_run_B      ( set_run_B             ),
        .clr_run_A      ( clr_run_A             ),
        .clr_run_B      ( clr_run_B             ),
        .flag_A         ( flag_A                ),
        .flag_B         ( flag_B                ),
        .overflow_A     ( overflow_A    ),
        .irq_n          ( irq_n                 )
);
 
`define YM_TIMER_CTRL 8'h14
 
wire    [1:0]    rl_out;
wire    [2:0]    fb_out;
wire    [2:0]    con_out;
wire    [6:0]    kc_out;
wire    [5:0]    kf_out;
wire    [2:0]    pms_out;
wire    [1:0]    ams_out;
wire    [2:0]    dt1_out;
wire    [3:0]    mul_out;
wire    [6:0]    tl_out;
wire    [1:0]    ks_out;
wire    [4:0]    ar_out;
wire                    amsen_out;
wire    [4:0]    d1r_out;
wire    [1:0]    dt2_out;
wire    [4:0]    d2r_out;
wire    [3:0]    d1l_out;
wire    [3:0]    rr_out;
 
wire    [1:0]    cur_op;
wire                    zero;
assign  sample =zero;
wire                    koff_out, kon_out;
 
wire    [7:0]    lfo_freq;
wire    [1:0]    lfo_w;
wire                    lfo_rst;
wire    [6:0]    am;
wire    [7:0]    pm;
wire    [6:0]    amd, pmd;
 
jt51_lfo u_lfo(
        .rst    ( rst_p1),
        .clk    ( clk   ),
        .zero   ( zero  ),
        .lfo_rst( lfo_rst ),
        .lfo_freq(lfo_freq),
        .lfo_w  ( lfo_w ),
        .lfo_amd( amd   ),
        .lfo_pmd( pmd   ),
        .am             ( am    ),
        .pm_u   ( pm    )
);
 
wire    [ 4:0]   keycode_III;
wire    [19:0]   phase_now;
 
jt51_phasegen u_pg(
        .clk    ( p1            ),                              // P1
        // Channel frequency
        .kc             ( kc_out        ),
        .kf             ( kf_out        ),
        // Operator multiplying
        .mul    ( mul_out       ),
        // Operator detuning
        .dt1    ( dt1_out       ),
        .dt2    ( dt2_out       ),
        // phase modulation from LFO
        .pms    ( pms_out       ),
        .pm             ( pm            ),
        // phase operation
        .keyon  ( kon_out       ),
        .keycode_III(keycode_III), // produced in stage II
        .phase_now(phase_now)
);
 
`ifdef TEST_SUPPORT
wire            test_eg, test_op0;
`endif
wire [9:0]       eg;
 
jt51_envelope u_eg(
        `ifdef TEST_SUPPORT
        .test_eg        ( test_eg       ),
        `endif
        .rst            ( rst_p1        ),
        .clk            ( p1            ),
        .zero           ( zero          ),
        // envelope configuration
        .keycode_III(keycode_III),      // used in stage III
        .arate          ( ar_out        ),
        .rate1          ( d1r_out       ),
        .rate2          ( d2r_out       ),
        .rrate          ( rr_out        ),
        .d1l            ( d1l_out       ),
        .ks                     ( ks_out        ),
        // envelope operation
        .keyon          ( kon_out       ),
        .keyoff         ( koff_out      ),
        // envelope number
        .tl                     ( tl_out        ),
        .am                     ( am            ),
        .ams            ( ams_out       ),
        .amsen          ( amsen_out     ),
        .eg                     ( eg            )
);
 
wire signed [13:0] op_out;
 
jt51_op u_op(
        `ifdef TEST_SUPPORT
        .test_eg ( test_eg      ),
        .test_op0( test_op0     ),
        `endif
        .clk    ( p1            ),
        .con    ( con_out       ),
        .fb             ( fb_out        ),
        .phase_cnt(phase_now),
        .cur_op ( cur_op        ),
        // volume
        .eg             ( eg            ),
        // output data
        .out    ( op_out        )
);
 
wire    [4:0] nfrq;
wire    [9:0] noise_out;
wire              ne, op31_acc;
 
jt51_noise u_noise(
        .rst    ( rst_p1        ),
        .clk    ( p1            ),
        .zero   ( zero          ),
        .ne             ( ne            ),
        .nfrq   ( nfrq          ),
        .eg             ( eg            ),
        .out    ( noise_out     ),
        .op31_acc(op31_acc      )
);
 
jt51_acc u_acc(
        .clk    ( p1            ),
        .zero   ( zero          ),
        .ne             ( ne            ),
        .noise  ( noise_out     ),
        .op31_acc(op31_acc      ),
        .rl             ( rl_out        ),
        .op_out ( op_out        ),
        .left   ( left          ),
        .right  ( right         ),
        .xleft  ( xleft         ),
        .xright ( xright        )
);
 
reg             busy;
wire    busy_mmr;
reg     [1:0] busy_mmr_sh;
 
reg             flag_B_s, flag_A_s;
assign  d_out = { busy, 5'h0, flag_B_s, flag_A_s };
 
always @(posedge clk )
        { flag_B_s, flag_A_s } <= { flag_B, flag_A };
 
 
wire            write = !cs_n && !wr_n;
 
reg     [7:0]    d_in_copy;
reg                     a0_copy;
reg                     write_copy;
 
always @(posedge clk) begin : cpu_interface
        if( rst ) begin
                busy            <= 1'b0;
                a0_copy         <= 1'b0;
                d_in_copy       <= 8'd0;
                write_copy      <= 1'b0;
        end
        else begin
                busy_mmr_sh <= { busy_mmr_sh[0], busy_mmr };
                if( write && !busy ) begin
                        busy            <= 1'b1;
                        write_copy      <= 1'b1;
                        a0_copy         <= a0;
                        d_in_copy       <= d_in;
                end
                else begin
                        if( busy_mmr ) write_copy       <= 1'b0;
                        if( busy && busy_mmr_sh==2'b10 ) busy <= 1'b0;
                end
        end
end
 
reg                     write_s, a0_s;
reg     [7:0]    d_in_s;
 
always @(posedge p1 )
        { write_s, a0_s, d_in_s } <= { write_copy, a0_copy, d_in_copy };
 
 
jt51_mmr u_mmr(
        .clk    ( p1            ),
        .rst    ( rst_p1        ),
        .a0             ( a0_s          ),
        .write  ( write_s       ),
        .d_in   ( d_in_s        ),
        .busy   ( busy_mmr      ),
 
        // CT
        .ct1    ( ct1           ),
        .ct2    ( ct2           ),
        // LFO
        .lfo_freq(lfo_freq),
        .lfo_w  ( lfo_w ),
        .lfo_amd( amd   ),
        .lfo_pmd( pmd   ),
        .lfo_rst( lfo_rst ),
 
        // Noise
        .ne                     ( ne                    ),
        .nfrq           ( nfrq                  ),
 
        // Timers
        .value_A        ( value_A               ),
        .value_B        ( value_B               ),
        .load_A         ( load_A                ),
        .load_B         ( load_B                ),
        .enable_irq_A( enable_irq_A ),
        .enable_irq_B( enable_irq_B ),
        .clr_flag_A     ( clr_flag_A    ),
        .clr_flag_B     ( clr_flag_B    ),
        .clr_run_A      ( clr_run_A             ),
        .clr_run_B      ( clr_run_B             ),
        .set_run_A      ( set_run_A             ),
        .set_run_B      ( set_run_B             ),
        .flag_A         ( overflow_A    ),
        `ifdef TEST_SUPPORT
        // Test
        .test_eg        ( test_eg               ),
        .test_op0       ( test_op0              ),
        `endif
        // REG
        .rl_out( rl_out ),
        .fb_out( fb_out ),
        .con_out( con_out ),
        .kc_out( kc_out ),
        .kf_out( kf_out ),
        .pms_out( pms_out ),
        .ams_out( ams_out ),
        .dt1_out( dt1_out ),
        .mul_out( mul_out ),
        .tl_out( tl_out ),
        .ks_out( ks_out ),
        .ar_out( ar_out ),
        .amsen_out( amsen_out ),
        .d1r_out( d1r_out ),
        .dt2_out( dt2_out ),
        .d2r_out( d2r_out ),
        .d1l_out( d1l_out ),
        .rr_out( rr_out ),
        .kon_out(kon_out),
        .koff_out(koff_out),
 
        .cur_op(cur_op),
        .zero(zero)
);
 
endmodule
 

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[/] [jt51/] [trunk/] [jt51/] [jt51.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	gryzor	`/* This file is part of JT51.`
2
3			`JT51 is free software: you can redistribute it and/or modify`
4			`it under the terms of the GNU General Public License as published by`
5			`the Free Software Foundation, either version 3 of the License, or`
6			`(at your option) any later version.`
7
8			`JT51 is distributed in the hope that it will be useful,`
9			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
10			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
11			`GNU General Public License for more details.`
12
13			`You should have received a copy of the GNU General Public License`
14			`along with JT51. If not, see <http://www.gnu.org/licenses/>.`
15
16			`Author: Jose Tejada Gomez. Twitter: @topapate`
17			`Version: 1.0`
18			`Date: 27-10-2016`
19			`*/`
20
21			`timescale 1ns / 1ps
22
23			`module jt51(`
24			`input clk, // main clock`
25			`input rst, // reset`
26			`input cs_n, // chip select`
27			`input wr_n, // write`
28			`input a0,`
29			`input [7:0] d_in, // data in`
30			`output [7:0] d_out, // data out`
31			`output ct1,`
32			`output ct2,`
33			`output irq_n, // I do not synchronize this signal`
34			`output reg p1,`
35			`// Low resolution output (same as real chip)`
36			`output sample, // marks new output sample`
37			`output signed [15:0] left,`
38			`output signed [15:0] right,`
39			`// Full resolution output`
40			`output signed [15:0] xleft,`
41			`output signed [15:0] xright,`
42			`// unsigned outputs for sigma delta converters, full resolution`
43			`output [15:0] dacleft,`
44			`output [15:0] dacright`
45			`);`
46
47			`reg rst_p1, rst_p1_aux;`
48
49			`assign dacleft = { ~xleft [15], xleft[14:0] };`
50			`assign dacright = { ~xright[15], xright[14:0] };`
51
52
53			`// Generate internal clock and synchronous reset for it.`
54			`always @(posedge clk or posedge rst)`
55			`if( rst )`
56			`p1 <= 1'b0;`
57			`else`
58			`p1 <= ~p1;`
59
60			`always @(posedge p1 or posedge rst)`
61			`if( rst ) begin`
62			`rst_p1_aux <= 1'b1;`
63			`rst_p1 <= 1'b1;`
64			`end`
65			`else begin`
66			`rst_p1_aux <= 1'b0;`
67			`rst_p1 <= rst_p1_aux;`
68			`end`
69
70			`// Timers`
71			`wire [9:0] value_A;`
72			`wire [7:0] value_B;`
73			`wire load_A, load_B;`
74			`wire enable_irq_A, enable_irq_B;`
75			`wire clr_flag_A, clr_flag_B;`
76			`wire flag_A, flag_B, overflow_A;`
77			`wire set_run_A, set_run_B;`
78			`wire clr_run_A, clr_run_B;`
79
80			`jt51_timers timers(`
81			`.clk ( clk ),`
82			`.rst ( rst_p1 ),`
83			`.value_A ( value_A ),`
84			`.value_B ( value_B ),`
85			`.load_A ( load_A ),`
86			`.load_B ( load_B ),`
87			`.enable_irq_A( enable_irq_A ),`
88			`.enable_irq_B( enable_irq_B ),`
89			`.clr_flag_A ( clr_flag_A ),`
90			`.clr_flag_B ( clr_flag_B ),`
91			`.set_run_A ( set_run_A ),`
92			`.set_run_B ( set_run_B ),`
93			`.clr_run_A ( clr_run_A ),`
94			`.clr_run_B ( clr_run_B ),`
95			`.flag_A ( flag_A ),`
96			`.flag_B ( flag_B ),`
97			`.overflow_A ( overflow_A ),`
98			`.irq_n ( irq_n )`
99			`);`
100
101			`define YM_TIMER_CTRL 8'h14
102
103			`wire [1:0] rl_out;`
104			`wire [2:0] fb_out;`
105			`wire [2:0] con_out;`
106			`wire [6:0] kc_out;`
107			`wire [5:0] kf_out;`
108			`wire [2:0] pms_out;`
109			`wire [1:0] ams_out;`
110			`wire [2:0] dt1_out;`
111			`wire [3:0] mul_out;`
112			`wire [6:0] tl_out;`
113			`wire [1:0] ks_out;`
114			`wire [4:0] ar_out;`
115			`wire amsen_out;`
116			`wire [4:0] d1r_out;`
117			`wire [1:0] dt2_out;`
118			`wire [4:0] d2r_out;`
119			`wire [3:0] d1l_out;`
120			`wire [3:0] rr_out;`
121
122			`wire [1:0] cur_op;`
123			`wire zero;`
124			`assign sample =zero;`
125			`wire koff_out, kon_out;`
126
127			`wire [7:0] lfo_freq;`
128			`wire [1:0] lfo_w;`
129			`wire lfo_rst;`
130			`wire [6:0] am;`
131			`wire [7:0] pm;`
132			`wire [6:0] amd, pmd;`
133
134			`jt51_lfo u_lfo(`
135			`.rst ( rst_p1),`
136			`.clk ( clk ),`
137			`.zero ( zero ),`
138			`.lfo_rst( lfo_rst ),`
139			`.lfo_freq(lfo_freq),`
140			`.lfo_w ( lfo_w ),`
141			`.lfo_amd( amd ),`
142			`.lfo_pmd( pmd ),`
143			`.am ( am ),`
144			`.pm_u ( pm )`
145			`);`
146
147			`wire [ 4:0] keycode_III;`
148			`wire [19:0] phase_now;`
149
150			`jt51_phasegen u_pg(`
151			`.clk ( p1 ), // P1`
152			`// Channel frequency`
153			`.kc ( kc_out ),`
154			`.kf ( kf_out ),`
155			`// Operator multiplying`
156			`.mul ( mul_out ),`
157			`// Operator detuning`
158			`.dt1 ( dt1_out ),`
159			`.dt2 ( dt2_out ),`
160			`// phase modulation from LFO`
161			`.pms ( pms_out ),`
162			`.pm ( pm ),`
163			`// phase operation`
164			`.keyon ( kon_out ),`
165			`.keycode_III(keycode_III), // produced in stage II`
166			`.phase_now(phase_now)`
167			`);`
168
169			`ifdef TEST_SUPPORT
170			`wire test_eg, test_op0;`
171			`endif
172			`wire [9:0] eg;`
173
174			`jt51_envelope u_eg(`
175			`ifdef TEST_SUPPORT
176			`.test_eg ( test_eg ),`
177			`endif
178			`.rst ( rst_p1 ),`
179			`.clk ( p1 ),`
180			`.zero ( zero ),`
181			`// envelope configuration`
182			`.keycode_III(keycode_III), // used in stage III`
183			`.arate ( ar_out ),`
184			`.rate1 ( d1r_out ),`
185			`.rate2 ( d2r_out ),`
186			`.rrate ( rr_out ),`
187			`.d1l ( d1l_out ),`
188			`.ks ( ks_out ),`
189			`// envelope operation`
190			`.keyon ( kon_out ),`
191			`.keyoff ( koff_out ),`
192			`// envelope number`
193			`.tl ( tl_out ),`
194			`.am ( am ),`
195			`.ams ( ams_out ),`
196			`.amsen ( amsen_out ),`
197			`.eg ( eg )`
198			`);`
199
200			`wire signed [13:0] op_out;`
201
202			`jt51_op u_op(`
203			`ifdef TEST_SUPPORT
204			`.test_eg ( test_eg ),`
205			`.test_op0( test_op0 ),`
206			`endif
207			`.clk ( p1 ),`
208			`.con ( con_out ),`
209			`.fb ( fb_out ),`
210			`.phase_cnt(phase_now),`
211			`.cur_op ( cur_op ),`
212			`// volume`
213			`.eg ( eg ),`
214			`// output data`
215			`.out ( op_out )`
216			`);`
217
218			`wire [4:0] nfrq;`
219			`wire [9:0] noise_out;`
220			`wire ne, op31_acc;`
221
222			`jt51_noise u_noise(`
223			`.rst ( rst_p1 ),`
224			`.clk ( p1 ),`
225			`.zero ( zero ),`
226			`.ne ( ne ),`
227			`.nfrq ( nfrq ),`
228			`.eg ( eg ),`
229			`.out ( noise_out ),`
230			`.op31_acc(op31_acc )`
231			`);`
232
233			`jt51_acc u_acc(`
234			`.clk ( p1 ),`
235			`.zero ( zero ),`
236			`.ne ( ne ),`
237			`.noise ( noise_out ),`
238			`.op31_acc(op31_acc ),`
239			`.rl ( rl_out ),`
240			`.op_out ( op_out ),`
241			`.left ( left ),`
242			`.right ( right ),`
243			`.xleft ( xleft ),`
244			`.xright ( xright )`
245			`);`
246
247			`reg busy;`
248			`wire busy_mmr;`
249			`reg [1:0] busy_mmr_sh;`
250
251			`reg flag_B_s, flag_A_s;`
252			`assign d_out = { busy, 5'h0, flag_B_s, flag_A_s };`
253
254			`always @(posedge clk )`
255			`{ flag_B_s, flag_A_s } <= { flag_B, flag_A };`
256
257
258			`wire write = !cs_n && !wr_n;`
259
260			`reg [7:0] d_in_copy;`
261			`reg a0_copy;`
262			`reg write_copy;`
263
264			`always @(posedge clk) begin : cpu_interface`
265			`if( rst ) begin`
266			`busy <= 1'b0;`
267			`a0_copy <= 1'b0;`
268			`d_in_copy <= 8'd0;`
269			`write_copy <= 1'b0;`
270			`end`
271			`else begin`
272			`busy_mmr_sh <= { busy_mmr_sh[0], busy_mmr };`
273			`if( write && !busy ) begin`
274			`busy <= 1'b1;`
275			`write_copy <= 1'b1;`
276			`a0_copy <= a0;`
277			`d_in_copy <= d_in;`
278			`end`
279			`else begin`
280			`if( busy_mmr ) write_copy <= 1'b0;`
281			`if( busy && busy_mmr_sh==2'b10 ) busy <= 1'b0;`
282			`end`
283			`end`
284			`end`
285
286			`reg write_s, a0_s;`
287			`reg [7:0] d_in_s;`
288
289			`always @(posedge p1 )`
290			`{ write_s, a0_s, d_in_s } <= { write_copy, a0_copy, d_in_copy };`
291
292
293			`jt51_mmr u_mmr(`
294			`.clk ( p1 ),`
295			`.rst ( rst_p1 ),`
296			`.a0 ( a0_s ),`
297			`.write ( write_s ),`
298			`.d_in ( d_in_s ),`
299			`.busy ( busy_mmr ),`
300
301			`// CT`
302			`.ct1 ( ct1 ),`
303			`.ct2 ( ct2 ),`
304			`// LFO`
305			`.lfo_freq(lfo_freq),`
306			`.lfo_w ( lfo_w ),`
307			`.lfo_amd( amd ),`
308			`.lfo_pmd( pmd ),`
309			`.lfo_rst( lfo_rst ),`
310
311			`// Noise`
312			`.ne ( ne ),`
313			`.nfrq ( nfrq ),`
314
315			`// Timers`
316			`.value_A ( value_A ),`
317			`.value_B ( value_B ),`
318			`.load_A ( load_A ),`
319			`.load_B ( load_B ),`
320			`.enable_irq_A( enable_irq_A ),`
321			`.enable_irq_B( enable_irq_B ),`
322			`.clr_flag_A ( clr_flag_A ),`
323			`.clr_flag_B ( clr_flag_B ),`
324			`.clr_run_A ( clr_run_A ),`
325			`.clr_run_B ( clr_run_B ),`
326			`.set_run_A ( set_run_A ),`
327			`.set_run_B ( set_run_B ),`
328			`.flag_A ( overflow_A ),`
329			`ifdef TEST_SUPPORT
330			`// Test`
331			`.test_eg ( test_eg ),`
332			`.test_op0 ( test_op0 ),`
333			`endif
334			`// REG`
335			`.rl_out( rl_out ),`
336			`.fb_out( fb_out ),`
337			`.con_out( con_out ),`
338			`.kc_out( kc_out ),`
339			`.kf_out( kf_out ),`
340			`.pms_out( pms_out ),`
341			`.ams_out( ams_out ),`
342			`.dt1_out( dt1_out ),`
343			`.mul_out( mul_out ),`
344			`.tl_out( tl_out ),`
345			`.ks_out( ks_out ),`
346			`.ar_out( ar_out ),`
347			`.amsen_out( amsen_out ),`
348			`.d1r_out( d1r_out ),`
349			`.dt2_out( dt2_out ),`
350			`.d2r_out( d2r_out ),`
351			`.d1l_out( d1l_out ),`
352			`.rr_out( rr_out ),`
353			`.kon_out(kon_out),`
354			`.koff_out(koff_out),`
355
356			`.cur_op(cur_op),`
357			`.zero(zero)`
358			`);`
359
360			`endmodule`
361