OpenCores
URL https://opencores.org/ocsvn/jtag/jtag/trunk

Subversion Repositories jtag

[/] [jtag/] [tags/] [rel_1/] [doc/] [or1k_10.bsd] - Blame information for rev 22

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 mohor
--////////////////////////////////////////////////////////////////////
2
--//                                                              ////
3
--//  or1k_10.bsd                                                 ////
4
--//                                                              ////
5
--//  This file is part of the IEEE 1149.1 Test Access Port (TAP) ////
6
--//  IP core project                                             ////
7
--//  http://www.opencores.org/cores/jtag/                        ////
8
--//                                                              ////
9
--//  Author(s):                                                  ////
10
--//      - Igor Mohor (igorM@opencores.org)                      ////
11
--//                                                              ////
12
--//                                                              ////
13
--////////////////////////////////////////////////////////////////////
14
--//                                                              ////
15
--// Copyright (C) 2000, 2001 Authors                             ////
16
--//                                                              ////
17
--// This source file may be used and distributed without         ////
18
--// restriction provided that this copyright statement is not    ////
19
--// removed from the file and that any derivative work contains  ////
20
--// the original copyright notice and the associated disclaimer. ////
21
--//                                                              ////
22
--// This source file is free software; you can redistribute it   ////
23
--// and/or modify it under the terms of the GNU Lesser General   ////
24
--// Public License as published by the Free Software Foundation; ////
25
--// either version 2.1 of the License, or (at your option) any   ////
26
--// later version.                                               ////
27
--//                                                              ////
28
--// This source is distributed in the hope that it will be       ////
29
--// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
30
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
31
--// PURPOSE.  See the GNU Lesser General Public License for more ////
32
--// details.                                                     ////
33
--//                                                              ////
34
--// You should have received a copy of the GNU Lesser General    ////
35
--// Public License along with this source; if not, download it   ////
36
--// from http://www.opencores.org/lgpl.shtml                     ////
37
--//                                                              ////
38
--////////////////////////////////////////////////////////////////////
39
--
40
-- CVS Revision History
41
--
42
-- $Log: not supported by cvs2svn $
43
-- Revision 1.1  2001/08/01 18:49:42  mohor
44
-- Reset signal changed. Bsdl file added to the project.
45
--
46
--
47
--
48
--
49
--
50
 
51
--
52
--  BSDL File created/edited by Igor Mohor  (igorm@opencores.org)
53
--
54
--Package: ??
55
entity or1k_10 is
56
 
57
generic (PHYSICAL_PIN_MAP : string := "vq44" );
58
 
59
port (
60
        MyInput0: in bit;
61
        MyInput1: in bit;
62
        MyOutput0: out bit;
63
        MyOutput1: out bit;
64
        MyBidirectional0: inout bit;
65
        MyBidirectional1: inout bit;
66
        TCK: in bit;
67
        TDI: in bit;
68
        TDO: out bit;
69
        TMS: in bit
70
        );
71
 
72
use STD_1149_1_1994.all;
73
 
74
attribute COMPONENT_CONFORMANCE of or1k_10 : entity is "STD_1149_1_1993";
75
attribute PIN_MAP of or1k_10 : entity is PHYSICAL_PIN_MAP;
76
 
77
constant vq44: PIN_MAP_STRING:=
78
        "TCK:1," &
79
        "TDI:2," &
80
        "TDO:3," &
81
        "TMS:4," &
82
        "MyInput0:5," &
83
        "MyInput1:6," &
84
        "MyOutput0:7," &
85
        "MyOutput1:8," &
86
        "MyBidirectional0:9," &
87
        "MyBidirectional1:10";
88
 
89
attribute TAP_SCAN_IN    of TDI : signal is true;
90
attribute TAP_SCAN_OUT   of TDO : signal is true;
91
attribute TAP_SCAN_MODE  of TMS : signal is true;
92
attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+06, BOTH);   --
93
attribute INSTRUCTION_LENGTH of or1k_10 : entity is 4;
94
 
95
attribute INSTRUCTION_OPCODE of or1k_10 : entity is             --
96
        "EXTEST ( 0000)," &
97
        "SAMPLE ( 0001)," &
98
        "IDCODE ( 0010)," &
99
        "BYPASS ( 1111)";
100
 
101
attribute INSTRUCTION_CAPTURE of or1k_10: entity is "1001";
102
 
103
attribute IDCODE_REGISTER of or1k_10: entity is --
104
        "1100" &               -- version
105
        "0011110000111100" &    -- part number
106
        "00111100001" &         -- manufacturer's id
107
        "1";                    -- required by standard
108
 
109
--attribute USERCODE_REGISTER of or1k_10: entity is
110
--        "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
111
 
112
 
113
-- attribute INSTRUCTION_DISABLE of or1k_10 : entity is "HIGHZ";
114
 
115
attribute REGISTER_ACCESS of or1k_10 : entity is
116
        "BYPASS (BYPASS)," &
117
                                "DEVICE_ID (IDCODE)," &
118
                                "BOUNDARY (SAMPLE,EXTEST)";
119
 
120
attribute BOUNDARY_LENGTH of or1k_10 : entity is 12;
121
--attribute BOUNDARY_LENGTH of or1k_10 : entity is 6;
122
 
123
attribute BOUNDARY_REGISTER of or1k_10 : entity is
124
-- num      cell   port                  function        safe  [ccell disval   rslt]
125
   "0     ( BC_1,  MyInput0             ,input   ,        X),   " &
126
   "1     ( BC_1,  MyInput1             ,input   ,        X),   " &
127
   "2     ( BC_1,  MyOutput0            ,output3 ,        0,     3,     0,      Z),   " &
128
   "3     ( BC_1,  *                    ,controlr,        1),   " &
129
   "4     ( BC_1,  MyOutput1            ,output3 ,        0,     5,     0,      Z),   " &
130
   "5     ( BC_1,  *                    ,controlr,        1),   " &
131
   "6     ( BC_1,  MyBidirectional0     ,input   ,        X),   " &
132
   "7     ( BC_1,  MyBidirectional0     ,output3 ,        0,     8,     0,      Z),   " &
133
   "8     ( BC_1,  *                    ,controlr,        1),   " &
134
   "9     ( BC_1,  MyBidirectional1     ,input   ,        X),   " &
135
   "10    ( BC_1,  MyBidirectional1     ,output3 ,        0,     11,    0,      Z),   " &
136
   "11    ( BC_1,  *                    ,controlr,        1)   " ;
137
end or1k_10;
138
 
139
end or1k_10;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.