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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the JTAG Test Access Port (TAP)        ////
////  http://www.opencores.org/projects/jtag/                     ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2004/01/17 17:37:44  mohor
// capture_dr_o added to ports.
//
// Revision 1.3  2004/01/14 13:50:56  mohor
// 5 consecutive TMS=1 causes reset of TAP.
//
// Revision 1.2  2004/01/08 10:29:44  mohor
// Control signals for tdo_pad_o mux are changed to negedge.
//
// Revision 1.1  2003/12/23 14:52:14  mohor
// Directory structure changed. New version of TAP.
//
// Revision 1.10  2003/10/23 18:08:01  mohor
// MBIST chain connection fixed.
//
// Revision 1.9  2003/10/23 16:17:02  mohor
// CRC logic changed.
//
// Revision 1.8  2003/10/21 09:48:31  simons
// Mbist support added.
//
// Revision 1.7  2002/11/06 14:30:10  mohor
// Trst active high. Inverted on higher layer.
//
// Revision 1.6  2002/04/22 12:55:56  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
//
// Revision 1.5  2002/03/26 14:23:38  mohor
// Signal tdo_padoe_o changed back to tdo_padoen_o.
//
// Revision 1.4  2002/03/25 13:16:15  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
// not named correctly.
//
// Revision 1.3  2002/03/12 14:30:05  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.2  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "tap_defines.v"
 
// Top module
module tap_top(
                // JTAG pads
                tms_pad_i,
                tck_pad_i,
                trst_pad_i,
                tdi_pad_i,
                tdo_pad_o,
                tdo_padoe_o,
 
                // TAP states
                shift_dr_o,
                pause_dr_o,
                update_dr_o,
                capture_dr_o,
 
                // Select signals for boundary scan or mbist
                extest_select_o,
                sample_preload_select_o,
                mbist_select_o,
                debug_select_o,
 
                // TDO signal that is connected to TDI of sub-modules.
                tdo_o,
 
                // TDI signals from sub-modules
                debug_tdi_i,    // from debug module
                bs_chain_tdi_i, // from Boundary Scan Chain
                mbist_tdi_i     // from Mbist Chain
              );
 
 
// JTAG pins
input   tms_pad_i;      // JTAG test mode select pad
input   tck_pad_i;      // JTAG test clock pad
input   trst_pad_i;     // JTAG test reset pad
input   tdi_pad_i;      // JTAG test data input pad
output  tdo_pad_o;      // JTAG test data output pad
output  tdo_padoe_o;    // Output enable for JTAG test data output pad 
 
// TAP states
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
output  capture_dr_o;
 
// Select signals for boundary scan or mbist
output  extest_select_o;
output  sample_preload_select_o;
output  mbist_select_o;
output  debug_select_o;
 
// TDO signal that is connected to TDI of sub-modules.
output  tdo_o;
 
// TDI signals from sub-modules
input   debug_tdi_i;    // from debug module
input   bs_chain_tdi_i; // from Boundary Scan Chain
input   mbist_tdi_i;    // from Mbist Chain
 
// Registers
reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir, shift_ir_neg;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
reg     extest_select;
reg     sample_preload_select;
reg     idcode_select;
reg     mbist_select;
reg     debug_select;
reg     bypass_select;
reg     tdo_pad_o;
reg     tdo_padoe_o;
reg     tms_q1, tms_q2, tms_q3, tms_q4;
wire    tms_reset;
 
assign tdo_o = tdi_pad_i;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
 
assign extest_select_o = extest_select;
assign sample_preload_select_o = sample_preload_select;
assign mbist_select_o = mbist_select;
assign debug_select_o = debug_select;
 
 
always @ (posedge tck_pad_i)
begin
  tms_q1 <= #1 tms_pad_i;
  tms_q2 <= #1 tms_q1;
  tms_q3 <= #1 tms_q2;
  tms_q4 <= #1 tms_q3;
end
 
 
assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i;    // 5 consecutive TMS=1 causes reset
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// test_logic_reset state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    test_logic_reset<=#1 1'b1;
  else if (tms_reset)
    test_logic_reset<=#1 1'b1;
  else
    begin
      if(tms_pad_i & (test_logic_reset | select_ir_scan))
        test_logic_reset<=#1 1'b1;
      else
        test_logic_reset<=#1 1'b0;
    end
end
 
// run_test_idle state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    run_test_idle<=#1 1'b0;
  else if (tms_reset)
    run_test_idle<=#1 1'b0;
  else
  if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
    run_test_idle<=#1 1'b1;
  else
    run_test_idle<=#1 1'b0;
end
 
// select_dr_scan state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_dr_scan<=#1 1'b0;
  else if (tms_reset)
    select_dr_scan<=#1 1'b0;
  else
  if(tms_pad_i & (run_test_idle | update_dr | update_ir))
    select_dr_scan<=#1 1'b1;
  else
    select_dr_scan<=#1 1'b0;
end
 
// capture_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_dr<=#1 1'b0;
  else if (tms_reset)
    capture_dr<=#1 1'b0;
  else
  if(~tms_pad_i & select_dr_scan)
    capture_dr<=#1 1'b1;
  else
    capture_dr<=#1 1'b0;
end
 
// shift_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_dr<=#1 1'b0;
  else if (tms_reset)
    shift_dr<=#1 1'b0;
  else
  if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
    shift_dr<=#1 1'b1;
  else
    shift_dr<=#1 1'b0;
end
 
// exit1_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_dr<=#1 1'b0;
  else if (tms_reset)
    exit1_dr<=#1 1'b0;
  else
  if(tms_pad_i & (capture_dr | shift_dr))
    exit1_dr<=#1 1'b1;
  else
    exit1_dr<=#1 1'b0;
end
 
// pause_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_dr<=#1 1'b0;
  else if (tms_reset)
    pause_dr<=#1 1'b0;
  else
  if(~tms_pad_i & (exit1_dr | pause_dr))
    pause_dr<=#1 1'b1;
  else
    pause_dr<=#1 1'b0;
end
 
// exit2_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_dr<=#1 1'b0;
  else if (tms_reset)
    exit2_dr<=#1 1'b0;
  else
  if(tms_pad_i & pause_dr)
    exit2_dr<=#1 1'b1;
  else
    exit2_dr<=#1 1'b0;
end
 
// update_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_dr<=#1 1'b0;
  else if (tms_reset)
    update_dr<=#1 1'b0;
  else
  if(tms_pad_i & (exit1_dr | exit2_dr))
    update_dr<=#1 1'b1;
  else
    update_dr<=#1 1'b0;
end
 
// select_ir_scan state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_ir_scan<=#1 1'b0;
  else if (tms_reset)
    select_ir_scan<=#1 1'b0;
  else
  if(tms_pad_i & select_dr_scan)
    select_ir_scan<=#1 1'b1;
  else
    select_ir_scan<=#1 1'b0;
end
 
// capture_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_ir<=#1 1'b0;
  else if (tms_reset)
    capture_ir<=#1 1'b0;
  else
  if(~tms_pad_i & select_ir_scan)
    capture_ir<=#1 1'b1;
  else
    capture_ir<=#1 1'b0;
end
 
// shift_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_ir<=#1 1'b0;
  else if (tms_reset)
    shift_ir<=#1 1'b0;
  else
  if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
    shift_ir<=#1 1'b1;
  else
    shift_ir<=#1 1'b0;
end
 
// exit1_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_ir<=#1 1'b0;
  else if (tms_reset)
    exit1_ir<=#1 1'b0;
  else
  if(tms_pad_i & (capture_ir | shift_ir))
    exit1_ir<=#1 1'b1;
  else
    exit1_ir<=#1 1'b0;
end
 
// pause_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_ir<=#1 1'b0;
  else if (tms_reset)
    pause_ir<=#1 1'b0;
  else
  if(~tms_pad_i & (exit1_ir | pause_ir))
    pause_ir<=#1 1'b1;
  else
    pause_ir<=#1 1'b0;
end
 
// exit2_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_ir<=#1 1'b0;
  else if (tms_reset)
    exit2_ir<=#1 1'b0;
  else
  if(tms_pad_i & pause_ir)
    exit2_ir<=#1 1'b1;
  else
    exit2_ir<=#1 1'b0;
end
 
// update_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_ir<=#1 1'b0;
  else if (tms_reset)
    update_ir<=#1 1'b0;
  else
  if(tms_pad_i & (exit1_ir | exit2_ir))
    update_ir<=#1 1'b1;
  else
    update_ir<=#1 1'b0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   jtag_ir:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
reg [`IR_LENGTH-1:0]  jtag_ir;          // Instruction register
reg [`IR_LENGTH-1:0]  latched_jtag_ir, latched_jtag_ir_neg;
reg                   instruction_tdo;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
  else if(capture_ir)
    jtag_ir <= #1 4'b0101;          // This value is fixed for easier fault detection
  else if(shift_ir)
    jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
 
always @ (negedge tck_pad_i)
begin
  instruction_tdo <= #1 jtag_ir[0];
end
/**********************************************************************************
*                                                                                 *
*   End: jtag_ir                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   jtag_dr:  JTAG Data Register                                                  *
*                                                                                 *
**********************************************************************************/
reg [`DR_LENGTH-1:0]  jtag_dr;          // Data register
reg [`DR_LENGTH-1:0]  latched_jtag_dr;
reg                   data_tdo;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    jtag_dr[`DR_LENGTH-1:0] <= #1 `DR_LENGTH'b0;
  else
  if(capture_dr)
    jtag_dr <= #1 4'b0101;          // This value is fixed for easier fault detection
  else
  if(shift_dr)
    jtag_dr[`DR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_dr[`DR_LENGTH-1:1]};
end
 
always @ (negedge tck_pad_i)
begin
  data_tdo <= #1 jtag_dr[0];
end
/**********************************************************************************
*                                                                                 *
*   End: jtag_dr                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   idcode logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg [31:0] idcode_reg;
reg        idcode_tdo;
 
always @ (posedge tck_pad_i)
begin
  if(idcode_select & shift_dr)
    idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
  else
    idcode_reg <= #1 `IDCODE_VALUE;
end
 
always @ (negedge tck_pad_i)
begin
    idcode_tdo <= #1 idcode_reg;
end
/**********************************************************************************
*                                                                                 *
*   End: idcode logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg  bypassed_tdo;
reg  bypass_reg;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if (trst_pad_i)
    bypass_reg<=#1 1'b0;
  else if(shift_dr)
    bypass_reg<=#1 tdi_pad_i;
end
 
always @ (negedge tck_pad_i)
begin
  bypassed_tdo <=#1 bypass_reg;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
// Updating jtag_ir (Instruction Register)
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else if (tms_reset)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else if(update_ir)
    latched_jtag_ir <=#1 jtag_ir;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating jtag_ir (Instruction Register)
always @ (latched_jtag_ir)
begin
  extest_select           = 1'b0;
  sample_preload_select   = 1'b0;
  idcode_select           = 1'b0;
  mbist_select            = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
 
  case(latched_jtag_ir)    /* synthesis parallel_case */
    `EXTEST:            extest_select           = 1'b1;    // External test
    `SAMPLE_PRELOAD:    sample_preload_select   = 1'b1;    // Sample preload
    `IDCODE:            idcode_select           = 1'b1;    // ID Code
    `MBIST:             mbist_select            = 1'b1;    // Mbist test
    `DEBUG:             debug_select            = 1'b1;    // Debug
    `BYPASS:            bypass_select           = 1'b1;    // BYPASS
    default:            bypass_select           = 1'b1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
          debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
          bypassed_tdo)
begin
  if(shift_ir_neg)
    tdo_pad_o = instruction_tdo;
  else
    begin
      case(latched_jtag_ir_neg)    // synthesis parallel_case
        `IDCODE:            tdo_pad_o = idcode_tdo;       // Reading ID code
        `DEBUG:             tdo_pad_o = debug_tdi_i;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o = bs_chain_tdi_i;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o = bs_chain_tdi_i;   // External test
        `MBIST:             tdo_pad_o = mbist_tdi_i;      // Mbist test
        default:            tdo_pad_o = bypassed_tdo;     // BYPASS instruction
      endcase
    end
end
 
 
// Tristate control for tdo_pad_o pin
always @ (negedge tck_pad_i)
begin
  tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
end
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
 
always @ (negedge tck_pad_i)
begin
  shift_ir_neg <= #1 shift_ir;
  latched_jtag_ir_neg <= #1 latched_jtag_ir;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	7	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the JTAG Test Access Port (TAP) ////`
7			`//// http://www.opencores.org/projects/jtag/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	13	simons	`// Revision 1.4 2004/01/17 17:37:44 mohor`
47			`// capture_dr_o added to ports.`
48			`//`
49	11	mohor	`// Revision 1.3 2004/01/14 13:50:56 mohor`
50			`// 5 consecutive TMS=1 causes reset of TAP.`
51			`//`
52	9	mohor	`// Revision 1.2 2004/01/08 10:29:44 mohor`
53			`// Control signals for tdo_pad_o mux are changed to negedge.`
54			`//`
55	8	mohor	`// Revision 1.1 2003/12/23 14:52:14 mohor`
56			`// Directory structure changed. New version of TAP.`
57			`//`
58	7	mohor	`// Revision 1.10 2003/10/23 18:08:01 mohor`
59			`// MBIST chain connection fixed.`
60			`//`
61			`// Revision 1.9 2003/10/23 16:17:02 mohor`
62			`// CRC logic changed.`
63			`//`
64			`// Revision 1.8 2003/10/21 09:48:31 simons`
65			`// Mbist support added.`
66			`//`
67			`// Revision 1.7 2002/11/06 14:30:10 mohor`
68			`// Trst active high. Inverted on higher layer.`
69			`//`
70			`// Revision 1.6 2002/04/22 12:55:56 mohor`
71			`// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.`
72			`//`
73			`// Revision 1.5 2002/03/26 14:23:38 mohor`
74			`// Signal tdo_padoe_o changed back to tdo_padoen_o.`
75			`//`
76			`// Revision 1.4 2002/03/25 13:16:15 mohor`
77			`// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just`
78			`// not named correctly.`
79			`//`
80			`// Revision 1.3 2002/03/12 14:30:05 mohor`
81			`// Few outputs for boundary scan chain added.`
82			`//`
83			`// Revision 1.2 2002/03/12 10:31:53 mohor`
84			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
85			`// contains only tap state machine and related logic. dbg_top contains all`
86			`// logic necessery for debugging.`
87			`//`
88			`// Revision 1.1 2002/03/08 15:28:16 mohor`
89			`// Structure changed. Hooks for jtag chain added.`
90			`//`
91			`//`
92			`//`
93			`//`
94
95			`// synopsys translate_off`
96			`include "timescale.v"
97			`// synopsys translate_on`
98			`include "tap_defines.v"
99
100			`// Top module`
101			`module tap_top(`
102			`// JTAG pads`
103			`tms_pad_i,`
104			`tck_pad_i,`
105			`trst_pad_i,`
106			`tdi_pad_i,`
107			`tdo_pad_o,`
108			`tdo_padoe_o,`
109
110			`// TAP states`
111			`shift_dr_o,`
112			`pause_dr_o,`
113			`update_dr_o,`
114	11	mohor	`capture_dr_o,`
115	7	mohor
116			`// Select signals for boundary scan or mbist`
117			`extest_select_o,`
118			`sample_preload_select_o,`
119			`mbist_select_o,`
120			`debug_select_o,`
121
122			`// TDO signal that is connected to TDI of sub-modules.`
123			`tdo_o,`
124
125			`// TDI signals from sub-modules`
126			`debug_tdi_i, // from debug module`
127			`bs_chain_tdi_i, // from Boundary Scan Chain`
128			`mbist_tdi_i // from Mbist Chain`
129			`);`
130
131
132			`// JTAG pins`
133			`input tms_pad_i; // JTAG test mode select pad`
134			`input tck_pad_i; // JTAG test clock pad`
135			`input trst_pad_i; // JTAG test reset pad`
136			`input tdi_pad_i; // JTAG test data input pad`
137			`output tdo_pad_o; // JTAG test data output pad`
138			`output tdo_padoe_o; // Output enable for JTAG test data output pad`
139
140			`// TAP states`
141			`output shift_dr_o;`
142			`output pause_dr_o;`
143			`output update_dr_o;`
144	11	mohor	`output capture_dr_o;`
145	7	mohor
146			`// Select signals for boundary scan or mbist`
147			`output extest_select_o;`
148			`output sample_preload_select_o;`
149			`output mbist_select_o;`
150			`output debug_select_o;`
151
152			`// TDO signal that is connected to TDI of sub-modules.`
153			`output tdo_o;`
154
155			`// TDI signals from sub-modules`
156			`input debug_tdi_i; // from debug module`
157			`input bs_chain_tdi_i; // from Boundary Scan Chain`
158			`input mbist_tdi_i; // from Mbist Chain`
159
160			`// Registers`
161			`reg test_logic_reset;`
162			`reg run_test_idle;`
163			`reg select_dr_scan;`
164			`reg capture_dr;`
165			`reg shift_dr;`
166			`reg exit1_dr;`
167			`reg pause_dr;`
168			`reg exit2_dr;`
169			`reg update_dr;`
170			`reg select_ir_scan;`
171			`reg capture_ir;`
172	8	mohor	`reg shift_ir, shift_ir_neg;`
173	7	mohor	`reg exit1_ir;`
174			`reg pause_ir;`
175			`reg exit2_ir;`
176			`reg update_ir;`
177			`reg extest_select;`
178			`reg sample_preload_select;`
179			`reg idcode_select;`
180			`reg mbist_select;`
181			`reg debug_select;`
182			`reg bypass_select;`
183			`reg tdo_pad_o;`
184			`reg tdo_padoe_o;`
185	9	mohor	`reg tms_q1, tms_q2, tms_q3, tms_q4;`
186			`wire tms_reset;`
187	7	mohor
188			`assign tdo_o = tdi_pad_i;`
189			`assign shift_dr_o = shift_dr;`
190			`assign pause_dr_o = pause_dr;`
191			`assign update_dr_o = update_dr;`
192	11	mohor	`assign capture_dr_o = capture_dr;`
193	7	mohor
194			`assign extest_select_o = extest_select;`
195			`assign sample_preload_select_o = sample_preload_select;`
196			`assign mbist_select_o = mbist_select;`
197			`assign debug_select_o = debug_select;`
198
199	9	mohor
200			`always @ (posedge tck_pad_i)`
201			`begin`
202			`tms_q1 <= #1 tms_pad_i;`
203			`tms_q2 <= #1 tms_q1;`
204			`tms_q3 <= #1 tms_q2;`
205			`tms_q4 <= #1 tms_q3;`
206			`end`
207
208
209			`assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset`
210
211
212	7	mohor	`/**********************************************************************************`
213			`* *`
214			`* TAP State Machine: Fully JTAG compliant *`
215			`* *`
216			`**********************************************************************************/`
217
218			`// test_logic_reset state`
219			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
220			`begin`
221			`if(trst_pad_i)`
222			`test_logic_reset<=#1 1'b1;`
223	9	mohor	`else if (tms_reset)`
224			`test_logic_reset<=#1 1'b1;`
225	7	mohor	`else`
226			`begin`
227			`if(tms_pad_i & (test_logic_reset \| select_ir_scan))`
228			`test_logic_reset<=#1 1'b1;`
229			`else`
230			`test_logic_reset<=#1 1'b0;`
231			`end`
232			`end`
233
234			`// run_test_idle state`
235			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
236			`begin`
237			`if(trst_pad_i)`
238			`run_test_idle<=#1 1'b0;`
239	9	mohor	`else if (tms_reset)`
240			`run_test_idle<=#1 1'b0;`
241	7	mohor	`else`
242			`if(~tms_pad_i & (test_logic_reset \| run_test_idle \| update_dr \| update_ir))`
243			`run_test_idle<=#1 1'b1;`
244			`else`
245			`run_test_idle<=#1 1'b0;`
246			`end`
247
248			`// select_dr_scan state`
249			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
250			`begin`
251			`if(trst_pad_i)`
252			`select_dr_scan<=#1 1'b0;`
253	9	mohor	`else if (tms_reset)`
254			`select_dr_scan<=#1 1'b0;`
255	7	mohor	`else`
256			`if(tms_pad_i & (run_test_idle \| update_dr \| update_ir))`
257			`select_dr_scan<=#1 1'b1;`
258			`else`
259			`select_dr_scan<=#1 1'b0;`
260			`end`
261
262			`// capture_dr state`
263			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
264			`begin`
265			`if(trst_pad_i)`
266			`capture_dr<=#1 1'b0;`
267	9	mohor	`else if (tms_reset)`
268			`capture_dr<=#1 1'b0;`
269	7	mohor	`else`
270			`if(~tms_pad_i & select_dr_scan)`
271			`capture_dr<=#1 1'b1;`
272			`else`
273			`capture_dr<=#1 1'b0;`
274			`end`
275
276			`// shift_dr state`
277			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
278			`begin`
279			`if(trst_pad_i)`
280			`shift_dr<=#1 1'b0;`
281	9	mohor	`else if (tms_reset)`
282			`shift_dr<=#1 1'b0;`
283	7	mohor	`else`
284			`if(~tms_pad_i & (capture_dr \| shift_dr \| exit2_dr))`
285			`shift_dr<=#1 1'b1;`
286			`else`
287			`shift_dr<=#1 1'b0;`
288			`end`
289
290			`// exit1_dr state`
291			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
292			`begin`
293			`if(trst_pad_i)`
294			`exit1_dr<=#1 1'b0;`
295	9	mohor	`else if (tms_reset)`
296			`exit1_dr<=#1 1'b0;`
297	7	mohor	`else`
298			`if(tms_pad_i & (capture_dr \| shift_dr))`
299			`exit1_dr<=#1 1'b1;`
300			`else`
301			`exit1_dr<=#1 1'b0;`
302			`end`
303
304			`// pause_dr state`
305			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
306			`begin`
307			`if(trst_pad_i)`
308			`pause_dr<=#1 1'b0;`
309	9	mohor	`else if (tms_reset)`
310			`pause_dr<=#1 1'b0;`
311	7	mohor	`else`
312			`if(~tms_pad_i & (exit1_dr \| pause_dr))`
313			`pause_dr<=#1 1'b1;`
314			`else`
315			`pause_dr<=#1 1'b0;`
316			`end`
317
318			`// exit2_dr state`
319			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
320			`begin`
321			`if(trst_pad_i)`
322			`exit2_dr<=#1 1'b0;`
323	9	mohor	`else if (tms_reset)`
324			`exit2_dr<=#1 1'b0;`
325	7	mohor	`else`
326			`if(tms_pad_i & pause_dr)`
327			`exit2_dr<=#1 1'b1;`
328			`else`
329			`exit2_dr<=#1 1'b0;`
330			`end`
331
332			`// update_dr state`
333			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
334			`begin`
335			`if(trst_pad_i)`
336			`update_dr<=#1 1'b0;`
337	9	mohor	`else if (tms_reset)`
338			`update_dr<=#1 1'b0;`
339	7	mohor	`else`
340			`if(tms_pad_i & (exit1_dr \| exit2_dr))`
341			`update_dr<=#1 1'b1;`
342			`else`
343			`update_dr<=#1 1'b0;`
344			`end`
345
346			`// select_ir_scan state`
347			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
348			`begin`
349			`if(trst_pad_i)`
350			`select_ir_scan<=#1 1'b0;`
351	9	mohor	`else if (tms_reset)`
352			`select_ir_scan<=#1 1'b0;`
353	7	mohor	`else`
354			`if(tms_pad_i & select_dr_scan)`
355			`select_ir_scan<=#1 1'b1;`
356			`else`
357			`select_ir_scan<=#1 1'b0;`
358			`end`
359
360			`// capture_ir state`
361			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
362			`begin`
363			`if(trst_pad_i)`
364			`capture_ir<=#1 1'b0;`
365	9	mohor	`else if (tms_reset)`
366			`capture_ir<=#1 1'b0;`
367	7	mohor	`else`
368			`if(~tms_pad_i & select_ir_scan)`
369			`capture_ir<=#1 1'b1;`
370			`else`
371			`capture_ir<=#1 1'b0;`
372			`end`
373
374			`// shift_ir state`
375			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
376			`begin`
377			`if(trst_pad_i)`
378			`shift_ir<=#1 1'b0;`
379	9	mohor	`else if (tms_reset)`
380			`shift_ir<=#1 1'b0;`
381	7	mohor	`else`
382			`if(~tms_pad_i & (capture_ir \| shift_ir \| exit2_ir))`
383			`shift_ir<=#1 1'b1;`
384			`else`
385			`shift_ir<=#1 1'b0;`
386			`end`
387
388			`// exit1_ir state`
389			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
390			`begin`
391			`if(trst_pad_i)`
392			`exit1_ir<=#1 1'b0;`
393	9	mohor	`else if (tms_reset)`
394			`exit1_ir<=#1 1'b0;`
395	7	mohor	`else`
396			`if(tms_pad_i & (capture_ir \| shift_ir))`
397			`exit1_ir<=#1 1'b1;`
398			`else`
399			`exit1_ir<=#1 1'b0;`
400			`end`
401
402			`// pause_ir state`
403			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
404			`begin`
405			`if(trst_pad_i)`
406			`pause_ir<=#1 1'b0;`
407	9	mohor	`else if (tms_reset)`
408			`pause_ir<=#1 1'b0;`
409	7	mohor	`else`
410			`if(~tms_pad_i & (exit1_ir \| pause_ir))`
411			`pause_ir<=#1 1'b1;`
412			`else`
413			`pause_ir<=#1 1'b0;`
414			`end`
415
416			`// exit2_ir state`
417			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
418			`begin`
419			`if(trst_pad_i)`
420			`exit2_ir<=#1 1'b0;`
421	9	mohor	`else if (tms_reset)`
422			`exit2_ir<=#1 1'b0;`
423	7	mohor	`else`
424			`if(tms_pad_i & pause_ir)`
425			`exit2_ir<=#1 1'b1;`
426			`else`
427			`exit2_ir<=#1 1'b0;`
428			`end`
429
430			`// update_ir state`
431			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
432			`begin`
433			`if(trst_pad_i)`
434			`update_ir<=#1 1'b0;`
435	9	mohor	`else if (tms_reset)`
436			`update_ir<=#1 1'b0;`
437	7	mohor	`else`
438			`if(tms_pad_i & (exit1_ir \| exit2_ir))`
439			`update_ir<=#1 1'b1;`
440			`else`
441			`update_ir<=#1 1'b0;`
442			`end`
443
444			`/**********************************************************************************`
445			`* *`
446			`* End: TAP State Machine *`
447			`* *`
448			`**********************************************************************************/`
449
450
451
452			`/**********************************************************************************`
453			`* *`
454			`* jtag_ir: JTAG Instruction Register *`
455			`* *`
456			`**********************************************************************************/`
457			reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
458	8	mohor	reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
459	7	mohor	`reg instruction_tdo;`
460
461			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
462			`begin`
463			`if(trst_pad_i)`
464			jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
465	9	mohor	`else if(capture_ir)`
466	7	mohor	`jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection`
467	9	mohor	`else if(shift_ir)`
468	7	mohor	jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
469			`end`
470
471			`always @ (negedge tck_pad_i)`
472			`begin`
473			`instruction_tdo <= #1 jtag_ir[0];`
474			`end`
475			`/**********************************************************************************`
476			`* *`
477			`* End: jtag_ir *`
478			`* *`
479			`**********************************************************************************/`
480
481
482			`/**********************************************************************************`
483			`* *`
484			`* jtag_dr: JTAG Data Register *`
485			`* *`
486			`**********************************************************************************/`
487			reg [`DR_LENGTH-1:0] jtag_dr; // Data register
488			reg [`DR_LENGTH-1:0] latched_jtag_dr;
489			`reg data_tdo;`
490
491			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
492			`begin`
493			`if(trst_pad_i)`
494			jtag_dr[`DR_LENGTH-1:0] <= #1 `DR_LENGTH'b0;
495			`else`
496			`if(capture_dr)`
497			`jtag_dr <= #1 4'b0101; // This value is fixed for easier fault detection`
498			`else`
499			`if(shift_dr)`
500			jtag_dr[`DR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_dr[`DR_LENGTH-1:1]};

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