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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the JTAG Test Access Port (TAP)        ////
////  http://www.opencores.org/projects/jtag/                     ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2004/01/18 09:27:39  simons
// Blocking non blocking assignmenst fixed.
//
// Revision 1.4  2004/01/17 17:37:44  mohor
// capture_dr_o added to ports.
//
// Revision 1.3  2004/01/14 13:50:56  mohor
// 5 consecutive TMS=1 causes reset of TAP.
//
// Revision 1.2  2004/01/08 10:29:44  mohor
// Control signals for tdo_pad_o mux are changed to negedge.
//
// Revision 1.1  2003/12/23 14:52:14  mohor
// Directory structure changed. New version of TAP.
//
// Revision 1.10  2003/10/23 18:08:01  mohor
// MBIST chain connection fixed.
//
// Revision 1.9  2003/10/23 16:17:02  mohor
// CRC logic changed.
//
// Revision 1.8  2003/10/21 09:48:31  simons
// Mbist support added.
//
// Revision 1.7  2002/11/06 14:30:10  mohor
// Trst active high. Inverted on higher layer.
//
// Revision 1.6  2002/04/22 12:55:56  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
//
// Revision 1.5  2002/03/26 14:23:38  mohor
// Signal tdo_padoe_o changed back to tdo_padoen_o.
//
// Revision 1.4  2002/03/25 13:16:15  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
// not named correctly.
//
// Revision 1.3  2002/03/12 14:30:05  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.2  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "tap_defines.v"
 
// Top module
module tap_top(
                // JTAG pads
                tms_pad_i,
                tck_pad_i,
                trst_pad_i,
                tdi_pad_i,
                tdo_pad_o,
                tdo_padoe_o,
 
                // TAP states
                shift_dr_o,
                pause_dr_o,
                update_dr_o,
                capture_dr_o,
 
                // Select signals for boundary scan or mbist
                extest_select_o,
                sample_preload_select_o,
                mbist_select_o,
                debug_select_o,
 
                // TDO signal that is connected to TDI of sub-modules.
                tdo_o,
 
                // TDI signals from sub-modules
                debug_tdi_i,    // from debug module
                bs_chain_tdi_i, // from Boundary Scan Chain
                mbist_tdi_i     // from Mbist Chain
              );
 
 
// JTAG pins
input   tms_pad_i;      // JTAG test mode select pad
input   tck_pad_i;      // JTAG test clock pad
input   trst_pad_i;     // JTAG test reset pad
input   tdi_pad_i;      // JTAG test data input pad
output  tdo_pad_o;      // JTAG test data output pad
output  tdo_padoe_o;    // Output enable for JTAG test data output pad 
 
// TAP states
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
output  capture_dr_o;
 
// Select signals for boundary scan or mbist
output  extest_select_o;
output  sample_preload_select_o;
output  mbist_select_o;
output  debug_select_o;
 
// TDO signal that is connected to TDI of sub-modules.
output  tdo_o;
 
// TDI signals from sub-modules
input   debug_tdi_i;    // from debug module
input   bs_chain_tdi_i; // from Boundary Scan Chain
input   mbist_tdi_i;    // from Mbist Chain
 
// Registers
reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir, shift_ir_neg;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
reg     extest_select;
reg     sample_preload_select;
reg     idcode_select;
reg     mbist_select;
reg     debug_select;
reg     bypass_select;
reg     tdo_pad_o;
reg     tdo_padoe_o;
reg     tms_q1, tms_q2, tms_q3, tms_q4;
wire    tms_reset;
 
assign tdo_o = tdi_pad_i;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
 
assign extest_select_o = extest_select;
assign sample_preload_select_o = sample_preload_select;
assign mbist_select_o = mbist_select;
assign debug_select_o = debug_select;
 
 
always @ (posedge tck_pad_i)
begin
  tms_q1 <= #1 tms_pad_i;
  tms_q2 <= #1 tms_q1;
  tms_q3 <= #1 tms_q2;
  tms_q4 <= #1 tms_q3;
end
 
 
assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i;    // 5 consecutive TMS=1 causes reset
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// test_logic_reset state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    test_logic_reset<=#1 1'b1;
  else if (tms_reset)
    test_logic_reset<=#1 1'b1;
  else
    begin
      if(tms_pad_i & (test_logic_reset | select_ir_scan))
        test_logic_reset<=#1 1'b1;
      else
        test_logic_reset<=#1 1'b0;
    end
end
 
// run_test_idle state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    run_test_idle<=#1 1'b0;
  else if (tms_reset)
    run_test_idle<=#1 1'b0;
  else
  if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
    run_test_idle<=#1 1'b1;
  else
    run_test_idle<=#1 1'b0;
end
 
// select_dr_scan state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_dr_scan<=#1 1'b0;
  else if (tms_reset)
    select_dr_scan<=#1 1'b0;
  else
  if(tms_pad_i & (run_test_idle | update_dr | update_ir))
    select_dr_scan<=#1 1'b1;
  else
    select_dr_scan<=#1 1'b0;
end
 
// capture_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_dr<=#1 1'b0;
  else if (tms_reset)
    capture_dr<=#1 1'b0;
  else
  if(~tms_pad_i & select_dr_scan)
    capture_dr<=#1 1'b1;
  else
    capture_dr<=#1 1'b0;
end
 
// shift_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_dr<=#1 1'b0;
  else if (tms_reset)
    shift_dr<=#1 1'b0;
  else
  if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
    shift_dr<=#1 1'b1;
  else
    shift_dr<=#1 1'b0;
end
 
// exit1_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_dr<=#1 1'b0;
  else if (tms_reset)
    exit1_dr<=#1 1'b0;
  else
  if(tms_pad_i & (capture_dr | shift_dr))
    exit1_dr<=#1 1'b1;
  else
    exit1_dr<=#1 1'b0;
end
 
// pause_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_dr<=#1 1'b0;
  else if (tms_reset)
    pause_dr<=#1 1'b0;
  else
  if(~tms_pad_i & (exit1_dr | pause_dr))
    pause_dr<=#1 1'b1;
  else
    pause_dr<=#1 1'b0;
end
 
// exit2_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_dr<=#1 1'b0;
  else if (tms_reset)
    exit2_dr<=#1 1'b0;
  else
  if(tms_pad_i & pause_dr)
    exit2_dr<=#1 1'b1;
  else
    exit2_dr<=#1 1'b0;
end
 
// update_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_dr<=#1 1'b0;
  else if (tms_reset)
    update_dr<=#1 1'b0;
  else
  if(tms_pad_i & (exit1_dr | exit2_dr))
    update_dr<=#1 1'b1;
  else
    update_dr<=#1 1'b0;
end
 
// select_ir_scan state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_ir_scan<=#1 1'b0;
  else if (tms_reset)
    select_ir_scan<=#1 1'b0;
  else
  if(tms_pad_i & select_dr_scan)
    select_ir_scan<=#1 1'b1;
  else
    select_ir_scan<=#1 1'b0;
end
 
// capture_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_ir<=#1 1'b0;
  else if (tms_reset)
    capture_ir<=#1 1'b0;
  else
  if(~tms_pad_i & select_ir_scan)
    capture_ir<=#1 1'b1;
  else
    capture_ir<=#1 1'b0;
end
 
// shift_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_ir<=#1 1'b0;
  else if (tms_reset)
    shift_ir<=#1 1'b0;
  else
  if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
    shift_ir<=#1 1'b1;
  else
    shift_ir<=#1 1'b0;
end
 
// exit1_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_ir<=#1 1'b0;
  else if (tms_reset)
    exit1_ir<=#1 1'b0;
  else
  if(tms_pad_i & (capture_ir | shift_ir))
    exit1_ir<=#1 1'b1;
  else
    exit1_ir<=#1 1'b0;
end
 
// pause_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_ir<=#1 1'b0;
  else if (tms_reset)
    pause_ir<=#1 1'b0;
  else
  if(~tms_pad_i & (exit1_ir | pause_ir))
    pause_ir<=#1 1'b1;
  else
    pause_ir<=#1 1'b0;
end
 
// exit2_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_ir<=#1 1'b0;
  else if (tms_reset)
    exit2_ir<=#1 1'b0;
  else
  if(tms_pad_i & pause_ir)
    exit2_ir<=#1 1'b1;
  else
    exit2_ir<=#1 1'b0;
end
 
// update_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_ir<=#1 1'b0;
  else if (tms_reset)
    update_ir<=#1 1'b0;
  else
  if(tms_pad_i & (exit1_ir | exit2_ir))
    update_ir<=#1 1'b1;
  else
    update_ir<=#1 1'b0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   jtag_ir:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
reg [`IR_LENGTH-1:0]  jtag_ir;          // Instruction register
reg [`IR_LENGTH-1:0]  latched_jtag_ir, latched_jtag_ir_neg;
reg                   instruction_tdo;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
  else if(capture_ir)
    jtag_ir <= #1 4'b0101;          // This value is fixed for easier fault detection
  else if(shift_ir)
    jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
 
always @ (negedge tck_pad_i)
begin
  instruction_tdo <= #1 jtag_ir[0];
end
/**********************************************************************************
*                                                                                 *
*   End: jtag_ir                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   idcode logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg [31:0] idcode_reg;
reg        idcode_tdo;
 
always @ (posedge tck_pad_i)
begin
  if(idcode_select & shift_dr)
    idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
  else
    idcode_reg <= #1 `IDCODE_VALUE;
end
 
always @ (negedge tck_pad_i)
begin
    idcode_tdo <= #1 idcode_reg;
end
/**********************************************************************************
*                                                                                 *
*   End: idcode logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg  bypassed_tdo;
reg  bypass_reg;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if (trst_pad_i)
    bypass_reg<=#1 1'b0;
  else if(shift_dr)
    bypass_reg<=#1 tdi_pad_i;
end
 
always @ (negedge tck_pad_i)
begin
  bypassed_tdo <=#1 bypass_reg;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
// Updating jtag_ir (Instruction Register)
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else if (tms_reset)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else if(update_ir)
    latched_jtag_ir <=#1 jtag_ir;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating jtag_ir (Instruction Register)
always @ (latched_jtag_ir)
begin
  extest_select           = 1'b0;
  sample_preload_select   = 1'b0;
  idcode_select           = 1'b0;
  mbist_select            = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
 
  case(latched_jtag_ir)    /* synthesis parallel_case */
    `EXTEST:            extest_select           = 1'b1;    // External test
    `SAMPLE_PRELOAD:    sample_preload_select   = 1'b1;    // Sample preload
    `IDCODE:            idcode_select           = 1'b1;    // ID Code
    `MBIST:             mbist_select            = 1'b1;    // Mbist test
    `DEBUG:             debug_select            = 1'b1;    // Debug
    `BYPASS:            bypass_select           = 1'b1;    // BYPASS
    default:            bypass_select           = 1'b1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
          debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
          bypassed_tdo)
begin
  if(shift_ir_neg)
    tdo_pad_o = instruction_tdo;
  else
    begin
      case(latched_jtag_ir_neg)    // synthesis parallel_case
        `IDCODE:            tdo_pad_o = idcode_tdo;       // Reading ID code
        `DEBUG:             tdo_pad_o = debug_tdi_i;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o = bs_chain_tdi_i;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o = bs_chain_tdi_i;   // External test
        `MBIST:             tdo_pad_o = mbist_tdi_i;      // Mbist test
        default:            tdo_pad_o = bypassed_tdo;     // BYPASS instruction
      endcase
    end
end
 
 
// Tristate control for tdo_pad_o pin
always @ (negedge tck_pad_i)
begin
  tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
end
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
 
always @ (negedge tck_pad_i)
begin
  shift_ir_neg <= #1 shift_ir;
  latched_jtag_ir_neg <= #1 latched_jtag_ir;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	7	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the JTAG Test Access Port (TAP) ////`
7			`//// http://www.opencores.org/projects/jtag/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	15	mohor	`// Revision 1.5 2004/01/18 09:27:39 simons`
47			`// Blocking non blocking assignmenst fixed.`
48			`//`
49	13	simons	`// Revision 1.4 2004/01/17 17:37:44 mohor`
50			`// capture_dr_o added to ports.`
51			`//`
52	11	mohor	`// Revision 1.3 2004/01/14 13:50:56 mohor`
53			`// 5 consecutive TMS=1 causes reset of TAP.`
54			`//`
55	9	mohor	`// Revision 1.2 2004/01/08 10:29:44 mohor`
56			`// Control signals for tdo_pad_o mux are changed to negedge.`
57			`//`
58	8	mohor	`// Revision 1.1 2003/12/23 14:52:14 mohor`
59			`// Directory structure changed. New version of TAP.`
60			`//`
61	7	mohor	`// Revision 1.10 2003/10/23 18:08:01 mohor`
62			`// MBIST chain connection fixed.`
63			`//`
64			`// Revision 1.9 2003/10/23 16:17:02 mohor`
65			`// CRC logic changed.`
66			`//`
67			`// Revision 1.8 2003/10/21 09:48:31 simons`
68			`// Mbist support added.`
69			`//`
70			`// Revision 1.7 2002/11/06 14:30:10 mohor`
71			`// Trst active high. Inverted on higher layer.`
72			`//`
73			`// Revision 1.6 2002/04/22 12:55:56 mohor`
74			`// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.`
75			`//`
76			`// Revision 1.5 2002/03/26 14:23:38 mohor`
77			`// Signal tdo_padoe_o changed back to tdo_padoen_o.`
78			`//`
79			`// Revision 1.4 2002/03/25 13:16:15 mohor`
80			`// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just`
81			`// not named correctly.`
82			`//`
83			`// Revision 1.3 2002/03/12 14:30:05 mohor`
84			`// Few outputs for boundary scan chain added.`
85			`//`
86			`// Revision 1.2 2002/03/12 10:31:53 mohor`
87			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
88			`// contains only tap state machine and related logic. dbg_top contains all`
89			`// logic necessery for debugging.`
90			`//`
91			`// Revision 1.1 2002/03/08 15:28:16 mohor`
92			`// Structure changed. Hooks for jtag chain added.`
93			`//`
94			`//`
95			`//`
96			`//`
97
98			`// synopsys translate_off`
99			`include "timescale.v"
100			`// synopsys translate_on`
101			`include "tap_defines.v"
102
103			`// Top module`
104			`module tap_top(`
105			`// JTAG pads`
106			`tms_pad_i,`
107			`tck_pad_i,`
108			`trst_pad_i,`
109			`tdi_pad_i,`
110			`tdo_pad_o,`
111			`tdo_padoe_o,`
112
113			`// TAP states`
114			`shift_dr_o,`
115			`pause_dr_o,`
116			`update_dr_o,`
117	11	mohor	`capture_dr_o,`
118	7	mohor
119			`// Select signals for boundary scan or mbist`
120			`extest_select_o,`
121			`sample_preload_select_o,`
122			`mbist_select_o,`
123			`debug_select_o,`
124
125			`// TDO signal that is connected to TDI of sub-modules.`
126			`tdo_o,`
127
128			`// TDI signals from sub-modules`
129			`debug_tdi_i, // from debug module`
130			`bs_chain_tdi_i, // from Boundary Scan Chain`
131			`mbist_tdi_i // from Mbist Chain`
132			`);`
133
134
135			`// JTAG pins`
136			`input tms_pad_i; // JTAG test mode select pad`
137			`input tck_pad_i; // JTAG test clock pad`
138			`input trst_pad_i; // JTAG test reset pad`
139			`input tdi_pad_i; // JTAG test data input pad`
140			`output tdo_pad_o; // JTAG test data output pad`
141			`output tdo_padoe_o; // Output enable for JTAG test data output pad`
142
143			`// TAP states`
144			`output shift_dr_o;`
145			`output pause_dr_o;`
146			`output update_dr_o;`
147	11	mohor	`output capture_dr_o;`
148	7	mohor
149			`// Select signals for boundary scan or mbist`
150			`output extest_select_o;`
151			`output sample_preload_select_o;`
152			`output mbist_select_o;`
153			`output debug_select_o;`
154
155			`// TDO signal that is connected to TDI of sub-modules.`
156			`output tdo_o;`
157
158			`// TDI signals from sub-modules`
159			`input debug_tdi_i; // from debug module`
160			`input bs_chain_tdi_i; // from Boundary Scan Chain`
161			`input mbist_tdi_i; // from Mbist Chain`
162
163			`// Registers`
164			`reg test_logic_reset;`
165			`reg run_test_idle;`
166			`reg select_dr_scan;`
167			`reg capture_dr;`
168			`reg shift_dr;`
169			`reg exit1_dr;`
170			`reg pause_dr;`
171			`reg exit2_dr;`
172			`reg update_dr;`
173			`reg select_ir_scan;`
174			`reg capture_ir;`
175	8	mohor	`reg shift_ir, shift_ir_neg;`
176	7	mohor	`reg exit1_ir;`
177			`reg pause_ir;`
178			`reg exit2_ir;`
179			`reg update_ir;`
180			`reg extest_select;`
181			`reg sample_preload_select;`
182			`reg idcode_select;`
183			`reg mbist_select;`
184			`reg debug_select;`
185			`reg bypass_select;`
186			`reg tdo_pad_o;`
187			`reg tdo_padoe_o;`
188	9	mohor	`reg tms_q1, tms_q2, tms_q3, tms_q4;`
189			`wire tms_reset;`
190	7	mohor
191			`assign tdo_o = tdi_pad_i;`
192			`assign shift_dr_o = shift_dr;`
193			`assign pause_dr_o = pause_dr;`
194			`assign update_dr_o = update_dr;`
195	11	mohor	`assign capture_dr_o = capture_dr;`
196	7	mohor
197			`assign extest_select_o = extest_select;`
198			`assign sample_preload_select_o = sample_preload_select;`
199			`assign mbist_select_o = mbist_select;`
200			`assign debug_select_o = debug_select;`
201
202	9	mohor
203			`always @ (posedge tck_pad_i)`
204			`begin`
205			`tms_q1 <= #1 tms_pad_i;`
206			`tms_q2 <= #1 tms_q1;`
207			`tms_q3 <= #1 tms_q2;`
208			`tms_q4 <= #1 tms_q3;`
209			`end`
210
211
212			`assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset`
213
214
215	7	mohor	`/**********************************************************************************`
216			`* *`
217			`* TAP State Machine: Fully JTAG compliant *`
218			`* *`
219			`**********************************************************************************/`
220
221			`// test_logic_reset state`
222			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
223			`begin`
224			`if(trst_pad_i)`
225			`test_logic_reset<=#1 1'b1;`
226	9	mohor	`else if (tms_reset)`
227			`test_logic_reset<=#1 1'b1;`
228	7	mohor	`else`
229			`begin`
230			`if(tms_pad_i & (test_logic_reset \| select_ir_scan))`
231			`test_logic_reset<=#1 1'b1;`
232			`else`
233			`test_logic_reset<=#1 1'b0;`
234			`end`
235			`end`
236
237			`// run_test_idle state`
238			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
239			`begin`
240			`if(trst_pad_i)`
241			`run_test_idle<=#1 1'b0;`
242	9	mohor	`else if (tms_reset)`
243			`run_test_idle<=#1 1'b0;`
244	7	mohor	`else`
245			`if(~tms_pad_i & (test_logic_reset \| run_test_idle \| update_dr \| update_ir))`
246			`run_test_idle<=#1 1'b1;`
247			`else`
248			`run_test_idle<=#1 1'b0;`
249			`end`
250
251			`// select_dr_scan state`
252			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
253			`begin`
254			`if(trst_pad_i)`
255			`select_dr_scan<=#1 1'b0;`
256	9	mohor	`else if (tms_reset)`
257			`select_dr_scan<=#1 1'b0;`
258	7	mohor	`else`
259			`if(tms_pad_i & (run_test_idle \| update_dr \| update_ir))`
260			`select_dr_scan<=#1 1'b1;`
261			`else`
262			`select_dr_scan<=#1 1'b0;`
263			`end`
264
265			`// capture_dr state`
266			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
267			`begin`
268			`if(trst_pad_i)`
269			`capture_dr<=#1 1'b0;`
270	9	mohor	`else if (tms_reset)`
271			`capture_dr<=#1 1'b0;`
272	7	mohor	`else`
273			`if(~tms_pad_i & select_dr_scan)`
274			`capture_dr<=#1 1'b1;`
275			`else`
276			`capture_dr<=#1 1'b0;`
277			`end`
278
279			`// shift_dr state`
280			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
281			`begin`
282			`if(trst_pad_i)`
283			`shift_dr<=#1 1'b0;`
284	9	mohor	`else if (tms_reset)`
285			`shift_dr<=#1 1'b0;`
286	7	mohor	`else`
287			`if(~tms_pad_i & (capture_dr \| shift_dr \| exit2_dr))`
288			`shift_dr<=#1 1'b1;`
289			`else`
290			`shift_dr<=#1 1'b0;`
291			`end`
292
293			`// exit1_dr state`
294			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
295			`begin`
296			`if(trst_pad_i)`
297			`exit1_dr<=#1 1'b0;`
298	9	mohor	`else if (tms_reset)`
299			`exit1_dr<=#1 1'b0;`
300	7	mohor	`else`
301			`if(tms_pad_i & (capture_dr \| shift_dr))`
302			`exit1_dr<=#1 1'b1;`
303			`else`
304			`exit1_dr<=#1 1'b0;`
305			`end`
306
307			`// pause_dr state`
308			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
309			`begin`
310			`if(trst_pad_i)`
311			`pause_dr<=#1 1'b0;`
312	9	mohor	`else if (tms_reset)`
313			`pause_dr<=#1 1'b0;`
314	7	mohor	`else`
315			`if(~tms_pad_i & (exit1_dr \| pause_dr))`
316			`pause_dr<=#1 1'b1;`
317			`else`
318			`pause_dr<=#1 1'b0;`
319			`end`
320
321			`// exit2_dr state`
322			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
323			`begin`
324			`if(trst_pad_i)`
325			`exit2_dr<=#1 1'b0;`
326	9	mohor	`else if (tms_reset)`
327			`exit2_dr<=#1 1'b0;`
328	7	mohor	`else`
329			`if(tms_pad_i & pause_dr)`
330			`exit2_dr<=#1 1'b1;`
331			`else`
332			`exit2_dr<=#1 1'b0;`
333			`end`
334
335			`// update_dr state`
336			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
337			`begin`
338			`if(trst_pad_i)`
339			`update_dr<=#1 1'b0;`
340	9	mohor	`else if (tms_reset)`
341			`update_dr<=#1 1'b0;`
342	7	mohor	`else`
343			`if(tms_pad_i & (exit1_dr \| exit2_dr))`
344			`update_dr<=#1 1'b1;`
345			`else`
346			`update_dr<=#1 1'b0;`
347			`end`
348
349			`// select_ir_scan state`
350			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
351			`begin`
352			`if(trst_pad_i)`
353			`select_ir_scan<=#1 1'b0;`
354	9	mohor	`else if (tms_reset)`
355			`select_ir_scan<=#1 1'b0;`
356	7	mohor	`else`
357			`if(tms_pad_i & select_dr_scan)`
358			`select_ir_scan<=#1 1'b1;`
359			`else`
360			`select_ir_scan<=#1 1'b0;`
361			`end`
362
363			`// capture_ir state`
364			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
365			`begin`
366			`if(trst_pad_i)`
367			`capture_ir<=#1 1'b0;`
368	9	mohor	`else if (tms_reset)`
369			`capture_ir<=#1 1'b0;`
370	7	mohor	`else`
371			`if(~tms_pad_i & select_ir_scan)`
372			`capture_ir<=#1 1'b1;`
373			`else`
374			`capture_ir<=#1 1'b0;`
375			`end`
376
377			`// shift_ir state`
378			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
379			`begin`
380			`if(trst_pad_i)`
381			`shift_ir<=#1 1'b0;`
382	9	mohor	`else if (tms_reset)`
383			`shift_ir<=#1 1'b0;`
384	7	mohor	`else`
385			`if(~tms_pad_i & (capture_ir \| shift_ir \| exit2_ir))`
386			`shift_ir<=#1 1'b1;`
387			`else`
388			`shift_ir<=#1 1'b0;`
389			`end`
390
391			`// exit1_ir state`
392			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
393			`begin`
394			`if(trst_pad_i)`
395			`exit1_ir<=#1 1'b0;`
396	9	mohor	`else if (tms_reset)`
397			`exit1_ir<=#1 1'b0;`
398	7	mohor	`else`
399			`if(tms_pad_i & (capture_ir \| shift_ir))`
400			`exit1_ir<=#1 1'b1;`
401			`else`
402			`exit1_ir<=#1 1'b0;`
403			`end`
404
405			`// pause_ir state`
406			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
407			`begin`
408			`if(trst_pad_i)`
409			`pause_ir<=#1 1'b0;`
410	9	mohor	`else if (tms_reset)`
411			`pause_ir<=#1 1'b0;`
412	7	mohor	`else`
413			`if(~tms_pad_i & (exit1_ir \| pause_ir))`
414			`pause_ir<=#1 1'b1;`
415			`else`
416			`pause_ir<=#1 1'b0;`
417			`end`
418
419			`// exit2_ir state`
420			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
421			`begin`
422			`if(trst_pad_i)`
423			`exit2_ir<=#1 1'b0;`
424	9	mohor	`else if (tms_reset)`
425			`exit2_ir<=#1 1'b0;`
426	7	mohor	`else`
427			`if(tms_pad_i & pause_ir)`
428			`exit2_ir<=#1 1'b1;`
429			`else`
430			`exit2_ir<=#1 1'b0;`
431			`end`
432
433			`// update_ir state`
434			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
435			`begin`
436			`if(trst_pad_i)`
437			`update_ir<=#1 1'b0;`
438	9	mohor	`else if (tms_reset)`
439			`update_ir<=#1 1'b0;`
440	7	mohor	`else`
441			`if(tms_pad_i & (exit1_ir \| exit2_ir))`
442			`update_ir<=#1 1'b1;`
443			`else`
444			`update_ir<=#1 1'b0;`
445			`end`
446
447			`/**********************************************************************************`
448			`* *`
449			`* End: TAP State Machine *`
450			`* *`
451			`**********************************************************************************/`
452
453
454
455			`/**********************************************************************************`
456			`* *`
457			`* jtag_ir: JTAG Instruction Register *`
458			`* *`
459			`**********************************************************************************/`
460			reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
461	8	mohor	reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
462	7	mohor	`reg instruction_tdo;`
463
464			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
465			`begin`
466			`if(trst_pad_i)`
467			jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
468	9	mohor	`else if(capture_ir)`
469	7	mohor	`jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection`
470	9	mohor	`else if(shift_ir)`
471	7	mohor	jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
472			`end`
473
474			`always @ (negedge tck_pad_i)`
475			`begin`
476			`instruction_tdo <= #1 jtag_ir[0];`
477			`end`
478			`/**********************************************************************************`
479			`* *`
480			`* End: jtag_ir *`
481			`* *`
482			`**********************************************************************************/`
483
484
485
486			`/**********************************************************************************`
487			`* *`
488			`* idcode logic *`
489			`* *`
490			`**********************************************************************************/`
491			`reg [31:0] idcode_reg;`
492			`reg idcode_tdo;`
493
494			`always @ (posedge tck_pad_i)`
495			`begin`
496			`if(idcode_select & shift_dr)`
497			`idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};`
498			`else`
499			idcode_reg <= #1 `IDCODE_VALUE;
500			`end`

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