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[/] [jtag/] [tags/] [rel_4/] [tap/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 7

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the JTAG Test Access Port (TAP)        ////
////  http://www.opencores.org/projects/jtag/                     ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2003/10/23 18:08:01  mohor
// MBIST chain connection fixed.
//
// Revision 1.9  2003/10/23 16:17:02  mohor
// CRC logic changed.
//
// Revision 1.8  2003/10/21 09:48:31  simons
// Mbist support added.
//
// Revision 1.7  2002/11/06 14:30:10  mohor
// Trst active high. Inverted on higher layer.
//
// Revision 1.6  2002/04/22 12:55:56  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
//
// Revision 1.5  2002/03/26 14:23:38  mohor
// Signal tdo_padoe_o changed back to tdo_padoen_o.
//
// Revision 1.4  2002/03/25 13:16:15  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
// not named correctly.
//
// Revision 1.3  2002/03/12 14:30:05  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.2  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "tap_defines.v"
 
// Top module
module tap_top(
                // JTAG pads
                tms_pad_i,
                tck_pad_i,
                trst_pad_i,
                tdi_pad_i,
                tdo_pad_o,
                tdo_padoe_o,
 
                // TAP states
                shift_dr_o,
                pause_dr_o,
                update_dr_o,
 
                // Select signals for boundary scan or mbist
                extest_select_o,
                sample_preload_select_o,
                mbist_select_o,
                debug_select_o,
 
                // TDO signal that is connected to TDI of sub-modules.
                tdo_o,
 
                // TDI signals from sub-modules
                debug_tdi_i,    // from debug module
                bs_chain_tdi_i, // from Boundary Scan Chain
                mbist_tdi_i     // from Mbist Chain
              );
 
 
// JTAG pins
input   tms_pad_i;      // JTAG test mode select pad
input   tck_pad_i;      // JTAG test clock pad
input   trst_pad_i;     // JTAG test reset pad
input   tdi_pad_i;      // JTAG test data input pad
output  tdo_pad_o;      // JTAG test data output pad
output  tdo_padoe_o;    // Output enable for JTAG test data output pad 
 
// TAP states
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
 
// Select signals for boundary scan or mbist
output  extest_select_o;
output  sample_preload_select_o;
output  mbist_select_o;
output  debug_select_o;
 
// TDO signal that is connected to TDI of sub-modules.
output  tdo_o;
 
// TDI signals from sub-modules
input   debug_tdi_i;    // from debug module
input   bs_chain_tdi_i; // from Boundary Scan Chain
input   mbist_tdi_i;    // from Mbist Chain
 
// Registers
reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
reg     extest_select;
reg     sample_preload_select;
reg     idcode_select;
reg     mbist_select;
reg     debug_select;
reg     bypass_select;
reg     tdo_pad_o;
reg     tdo_padoe_o;
 
 
assign tdo_o = tdi_pad_i;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
 
assign extest_select_o = extest_select;
assign sample_preload_select_o = sample_preload_select;
assign mbist_select_o = mbist_select;
assign debug_select_o = debug_select;
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// test_logic_reset state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    test_logic_reset<=#1 1'b1;
  else
    begin
      if(tms_pad_i & (test_logic_reset | select_ir_scan))
        test_logic_reset<=#1 1'b1;
      else
        test_logic_reset<=#1 1'b0;
    end
end
 
// run_test_idle state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    run_test_idle<=#1 1'b0;
  else
  if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
    run_test_idle<=#1 1'b1;
  else
    run_test_idle<=#1 1'b0;
end
 
// select_dr_scan state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_dr_scan<=#1 1'b0;
  else
  if(tms_pad_i & (run_test_idle | update_dr | update_ir))
    select_dr_scan<=#1 1'b1;
  else
    select_dr_scan<=#1 1'b0;
end
 
// capture_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_dr<=#1 1'b0;
  else
  if(~tms_pad_i & select_dr_scan)
    capture_dr<=#1 1'b1;
  else
    capture_dr<=#1 1'b0;
end
 
// shift_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_dr<=#1 1'b0;
  else
  if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
    shift_dr<=#1 1'b1;
  else
    shift_dr<=#1 1'b0;
end
 
// exit1_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_dr<=#1 1'b0;
  else
  if(tms_pad_i & (capture_dr | shift_dr))
    exit1_dr<=#1 1'b1;
  else
    exit1_dr<=#1 1'b0;
end
 
// pause_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_dr<=#1 1'b0;
  else
  if(~tms_pad_i & (exit1_dr | pause_dr))
    pause_dr<=#1 1'b1;
  else
    pause_dr<=#1 1'b0;
end
 
// exit2_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_dr<=#1 1'b0;
  else
  if(tms_pad_i & pause_dr)
    exit2_dr<=#1 1'b1;
  else
    exit2_dr<=#1 1'b0;
end
 
// update_dr state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_dr<=#1 1'b0;
  else
  if(tms_pad_i & (exit1_dr | exit2_dr))
    update_dr<=#1 1'b1;
  else
    update_dr<=#1 1'b0;
end
 
// select_ir_scan state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    select_ir_scan<=#1 1'b0;
  else
  if(tms_pad_i & select_dr_scan)
    select_ir_scan<=#1 1'b1;
  else
    select_ir_scan<=#1 1'b0;
end
 
// capture_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    capture_ir<=#1 1'b0;
  else
  if(~tms_pad_i & select_ir_scan)
    capture_ir<=#1 1'b1;
  else
    capture_ir<=#1 1'b0;
end
 
// shift_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    shift_ir<=#1 1'b0;
  else
  if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
    shift_ir<=#1 1'b1;
  else
    shift_ir<=#1 1'b0;
end
 
// exit1_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit1_ir<=#1 1'b0;
  else
  if(tms_pad_i & (capture_ir | shift_ir))
    exit1_ir<=#1 1'b1;
  else
    exit1_ir<=#1 1'b0;
end
 
// pause_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    pause_ir<=#1 1'b0;
  else
  if(~tms_pad_i & (exit1_ir | pause_ir))
    pause_ir<=#1 1'b1;
  else
    pause_ir<=#1 1'b0;
end
 
// exit2_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    exit2_ir<=#1 1'b0;
  else
  if(tms_pad_i & pause_ir)
    exit2_ir<=#1 1'b1;
  else
    exit2_ir<=#1 1'b0;
end
 
// update_ir state
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    update_ir<=#1 1'b0;
  else
  if(tms_pad_i & (exit1_ir | exit2_ir))
    update_ir<=#1 1'b1;
  else
    update_ir<=#1 1'b0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   jtag_ir:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
reg [`IR_LENGTH-1:0]  jtag_ir;          // Instruction register
reg [`IR_LENGTH-1:0]  latched_jtag_ir;
reg                   instruction_tdo;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
  else
  if(capture_ir)
    jtag_ir <= #1 4'b0101;          // This value is fixed for easier fault detection
  else
  if(shift_ir)
    jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
 
always @ (negedge tck_pad_i)
begin
  instruction_tdo <= #1 jtag_ir[0];
end
/**********************************************************************************
*                                                                                 *
*   End: jtag_ir                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   jtag_dr:  JTAG Data Register                                                  *
*                                                                                 *
**********************************************************************************/
reg [`DR_LENGTH-1:0]  jtag_dr;          // Data register
reg [`DR_LENGTH-1:0]  latched_jtag_dr;
reg                   data_tdo;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    jtag_dr[`DR_LENGTH-1:0] <= #1 `DR_LENGTH'b0;
  else
  if(capture_dr)
    jtag_dr <= #1 4'b0101;          // This value is fixed for easier fault detection
  else
  if(shift_dr)
    jtag_dr[`DR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_dr[`DR_LENGTH-1:1]};
end
 
always @ (negedge tck_pad_i)
begin
  data_tdo <= #1 jtag_dr[0];
end
/**********************************************************************************
*                                                                                 *
*   End: jtag_dr                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   idcode logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg [31:0] idcode_reg;
reg        idcode_tdo;
 
always @ (posedge tck_pad_i)
begin
  if(idcode_select & shift_dr)
    idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
  else
    idcode_reg <= #1 `IDCODE_VALUE;
end
 
always @ (negedge tck_pad_i)
begin
    idcode_tdo <= #1 idcode_reg;
end
/**********************************************************************************
*                                                                                 *
*   End: idcode logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg  bypassed_tdo;
reg  bypass_reg;
 
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if (trst_pad_i)
    bypass_reg<=#1 1'b0;
  else if(shift_dr)
    bypass_reg<=#1 tdi_pad_i;
end
 
always @ (negedge tck_pad_i)
begin
  bypassed_tdo <=#1 bypass_reg;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
// Updating jtag_ir (Instruction Register)
always @ (posedge tck_pad_i or posedge trst_pad_i)
begin
  if(trst_pad_i)
    latched_jtag_ir <=#1 `IDCODE;   // IDCODE selected after reset
  else
  if(update_ir)
    latched_jtag_ir <=#1 jtag_ir;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating jtag_ir (Instruction Register)
always @ (latched_jtag_ir)
begin
  extest_select           = 1'b0;
  sample_preload_select   = 1'b0;
  idcode_select           = 1'b0;
  mbist_select            = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
 
  case(latched_jtag_ir)    /* synthesis parallel_case */
    `EXTEST:            extest_select           = 1'b1;    // External test
    `SAMPLE_PRELOAD:    sample_preload_select   = 1'b1;    // Sample preload
    `IDCODE:            idcode_select           = 1'b1;    // ID Code
    `MBIST:             mbist_select            = 1'b1;    // Mbist test
    `DEBUG:             debug_select            = 1'b1;    // Debug
    `BYPASS:            bypass_select           = 1'b1;    // BYPASS
    default:            bypass_select           = 1'b1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
 
always @ (shift_ir or exit1_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
          debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
          bypassed_tdo)
begin
  if(shift_ir)
    tdo_pad_o <=#1 instruction_tdo;
  else
    begin
      case(latched_jtag_ir)    // synthesis parallel_case
        `IDCODE:            tdo_pad_o = idcode_tdo;       // Reading ID code
        `DEBUG:             tdo_pad_o = debug_tdi_i;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o = bs_chain_tdi_i;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o = bs_chain_tdi_i;   // External test
        `MBIST:             tdo_pad_o = mbist_tdi_i;      // Mbist test
        default:            tdo_pad_o = bypassed_tdo;     // BYPASS instruction
      endcase
    end
end
 
 
// Tristate control for tdo_pad_o pin
always @ (negedge tck_pad_i)
begin
  tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
end
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
 
 
 
endmodule

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Subversion Repositories jtag

[/] [jtag/] [tags/] [rel_4/] [tap/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the JTAG Test Access Port (TAP) ////`
7			`//// http://www.opencores.org/projects/jtag/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`// Revision 1.10 2003/10/23 18:08:01 mohor`
47			`// MBIST chain connection fixed.`
48			`//`
49			`// Revision 1.9 2003/10/23 16:17:02 mohor`
50			`// CRC logic changed.`
51			`//`
52			`// Revision 1.8 2003/10/21 09:48:31 simons`
53			`// Mbist support added.`
54			`//`
55			`// Revision 1.7 2002/11/06 14:30:10 mohor`
56			`// Trst active high. Inverted on higher layer.`
57			`//`
58			`// Revision 1.6 2002/04/22 12:55:56 mohor`
59			`// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.`
60			`//`
61			`// Revision 1.5 2002/03/26 14:23:38 mohor`
62			`// Signal tdo_padoe_o changed back to tdo_padoen_o.`
63			`//`
64			`// Revision 1.4 2002/03/25 13:16:15 mohor`
65			`// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just`
66			`// not named correctly.`
67			`//`
68			`// Revision 1.3 2002/03/12 14:30:05 mohor`
69			`// Few outputs for boundary scan chain added.`
70			`//`
71			`// Revision 1.2 2002/03/12 10:31:53 mohor`
72			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
73			`// contains only tap state machine and related logic. dbg_top contains all`
74			`// logic necessery for debugging.`
75			`//`
76			`// Revision 1.1 2002/03/08 15:28:16 mohor`
77			`// Structure changed. Hooks for jtag chain added.`
78			`//`
79			`//`
80			`//`
81			`//`
82
83			`// synopsys translate_off`
84			`include "timescale.v"
85			`// synopsys translate_on`
86			`include "tap_defines.v"
87
88			`// Top module`
89			`module tap_top(`
90			`// JTAG pads`
91			`tms_pad_i,`
92			`tck_pad_i,`
93			`trst_pad_i,`
94			`tdi_pad_i,`
95			`tdo_pad_o,`
96			`tdo_padoe_o,`
97
98			`// TAP states`
99			`shift_dr_o,`
100			`pause_dr_o,`
101			`update_dr_o,`
102
103			`// Select signals for boundary scan or mbist`
104			`extest_select_o,`
105			`sample_preload_select_o,`
106			`mbist_select_o,`
107			`debug_select_o,`
108
109			`// TDO signal that is connected to TDI of sub-modules.`
110			`tdo_o,`
111
112			`// TDI signals from sub-modules`
113			`debug_tdi_i, // from debug module`
114			`bs_chain_tdi_i, // from Boundary Scan Chain`
115			`mbist_tdi_i // from Mbist Chain`
116			`);`
117
118
119			`// JTAG pins`
120			`input tms_pad_i; // JTAG test mode select pad`
121			`input tck_pad_i; // JTAG test clock pad`
122			`input trst_pad_i; // JTAG test reset pad`
123			`input tdi_pad_i; // JTAG test data input pad`
124			`output tdo_pad_o; // JTAG test data output pad`
125			`output tdo_padoe_o; // Output enable for JTAG test data output pad`
126
127			`// TAP states`
128			`output shift_dr_o;`
129			`output pause_dr_o;`
130			`output update_dr_o;`
131
132			`// Select signals for boundary scan or mbist`
133			`output extest_select_o;`
134			`output sample_preload_select_o;`
135			`output mbist_select_o;`
136			`output debug_select_o;`
137
138			`// TDO signal that is connected to TDI of sub-modules.`
139			`output tdo_o;`
140
141			`// TDI signals from sub-modules`
142			`input debug_tdi_i; // from debug module`
143			`input bs_chain_tdi_i; // from Boundary Scan Chain`
144			`input mbist_tdi_i; // from Mbist Chain`
145
146			`// Registers`
147			`reg test_logic_reset;`
148			`reg run_test_idle;`
149			`reg select_dr_scan;`
150			`reg capture_dr;`
151			`reg shift_dr;`
152			`reg exit1_dr;`
153			`reg pause_dr;`
154			`reg exit2_dr;`
155			`reg update_dr;`
156			`reg select_ir_scan;`
157			`reg capture_ir;`
158			`reg shift_ir;`
159			`reg exit1_ir;`
160			`reg pause_ir;`
161			`reg exit2_ir;`
162			`reg update_ir;`
163			`reg extest_select;`
164			`reg sample_preload_select;`
165			`reg idcode_select;`
166			`reg mbist_select;`
167			`reg debug_select;`
168			`reg bypass_select;`
169			`reg tdo_pad_o;`
170			`reg tdo_padoe_o;`
171
172
173			`assign tdo_o = tdi_pad_i;`
174			`assign shift_dr_o = shift_dr;`
175			`assign pause_dr_o = pause_dr;`
176			`assign update_dr_o = update_dr;`
177
178			`assign extest_select_o = extest_select;`
179			`assign sample_preload_select_o = sample_preload_select;`
180			`assign mbist_select_o = mbist_select;`
181			`assign debug_select_o = debug_select;`
182
183			`/**********************************************************************************`
184			`* *`
185			`* TAP State Machine: Fully JTAG compliant *`
186			`* *`
187			`**********************************************************************************/`
188
189			`// test_logic_reset state`
190			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
191			`begin`
192			`if(trst_pad_i)`
193			`test_logic_reset<=#1 1'b1;`
194			`else`
195			`begin`
196			`if(tms_pad_i & (test_logic_reset \| select_ir_scan))`
197			`test_logic_reset<=#1 1'b1;`
198			`else`
199			`test_logic_reset<=#1 1'b0;`
200			`end`
201			`end`
202
203			`// run_test_idle state`
204			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
205			`begin`
206			`if(trst_pad_i)`
207			`run_test_idle<=#1 1'b0;`
208			`else`
209			`if(~tms_pad_i & (test_logic_reset \| run_test_idle \| update_dr \| update_ir))`
210			`run_test_idle<=#1 1'b1;`
211			`else`
212			`run_test_idle<=#1 1'b0;`
213			`end`
214
215			`// select_dr_scan state`
216			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
217			`begin`
218			`if(trst_pad_i)`
219			`select_dr_scan<=#1 1'b0;`
220			`else`
221			`if(tms_pad_i & (run_test_idle \| update_dr \| update_ir))`
222			`select_dr_scan<=#1 1'b1;`
223			`else`
224			`select_dr_scan<=#1 1'b0;`
225			`end`
226
227			`// capture_dr state`
228			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
229			`begin`
230			`if(trst_pad_i)`
231			`capture_dr<=#1 1'b0;`
232			`else`
233			`if(~tms_pad_i & select_dr_scan)`
234			`capture_dr<=#1 1'b1;`
235			`else`
236			`capture_dr<=#1 1'b0;`
237			`end`
238
239			`// shift_dr state`
240			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
241			`begin`
242			`if(trst_pad_i)`
243			`shift_dr<=#1 1'b0;`
244			`else`
245			`if(~tms_pad_i & (capture_dr \| shift_dr \| exit2_dr))`
246			`shift_dr<=#1 1'b1;`
247			`else`
248			`shift_dr<=#1 1'b0;`
249			`end`
250
251			`// exit1_dr state`
252			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
253			`begin`
254			`if(trst_pad_i)`
255			`exit1_dr<=#1 1'b0;`
256			`else`
257			`if(tms_pad_i & (capture_dr \| shift_dr))`
258			`exit1_dr<=#1 1'b1;`
259			`else`
260			`exit1_dr<=#1 1'b0;`
261			`end`
262
263			`// pause_dr state`
264			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
265			`begin`
266			`if(trst_pad_i)`
267			`pause_dr<=#1 1'b0;`
268			`else`
269			`if(~tms_pad_i & (exit1_dr \| pause_dr))`
270			`pause_dr<=#1 1'b1;`
271			`else`
272			`pause_dr<=#1 1'b0;`
273			`end`
274
275			`// exit2_dr state`
276			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
277			`begin`
278			`if(trst_pad_i)`
279			`exit2_dr<=#1 1'b0;`
280			`else`
281			`if(tms_pad_i & pause_dr)`
282			`exit2_dr<=#1 1'b1;`
283			`else`
284			`exit2_dr<=#1 1'b0;`
285			`end`
286
287			`// update_dr state`
288			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
289			`begin`
290			`if(trst_pad_i)`
291			`update_dr<=#1 1'b0;`
292			`else`
293			`if(tms_pad_i & (exit1_dr \| exit2_dr))`
294			`update_dr<=#1 1'b1;`
295			`else`
296			`update_dr<=#1 1'b0;`
297			`end`
298
299			`// select_ir_scan state`
300			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
301			`begin`
302			`if(trst_pad_i)`
303			`select_ir_scan<=#1 1'b0;`
304			`else`
305			`if(tms_pad_i & select_dr_scan)`
306			`select_ir_scan<=#1 1'b1;`
307			`else`
308			`select_ir_scan<=#1 1'b0;`
309			`end`
310
311			`// capture_ir state`
312			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
313			`begin`
314			`if(trst_pad_i)`
315			`capture_ir<=#1 1'b0;`
316			`else`
317			`if(~tms_pad_i & select_ir_scan)`
318			`capture_ir<=#1 1'b1;`
319			`else`
320			`capture_ir<=#1 1'b0;`
321			`end`
322
323			`// shift_ir state`
324			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
325			`begin`
326			`if(trst_pad_i)`
327			`shift_ir<=#1 1'b0;`
328			`else`
329			`if(~tms_pad_i & (capture_ir \| shift_ir \| exit2_ir))`
330			`shift_ir<=#1 1'b1;`
331			`else`
332			`shift_ir<=#1 1'b0;`
333			`end`
334
335			`// exit1_ir state`
336			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
337			`begin`
338			`if(trst_pad_i)`
339			`exit1_ir<=#1 1'b0;`
340			`else`
341			`if(tms_pad_i & (capture_ir \| shift_ir))`
342			`exit1_ir<=#1 1'b1;`
343			`else`
344			`exit1_ir<=#1 1'b0;`
345			`end`
346
347			`// pause_ir state`
348			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
349			`begin`
350			`if(trst_pad_i)`
351			`pause_ir<=#1 1'b0;`
352			`else`
353			`if(~tms_pad_i & (exit1_ir \| pause_ir))`
354			`pause_ir<=#1 1'b1;`
355			`else`
356			`pause_ir<=#1 1'b0;`
357			`end`
358
359			`// exit2_ir state`
360			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
361			`begin`
362			`if(trst_pad_i)`
363			`exit2_ir<=#1 1'b0;`
364			`else`
365			`if(tms_pad_i & pause_ir)`
366			`exit2_ir<=#1 1'b1;`
367			`else`
368			`exit2_ir<=#1 1'b0;`
369			`end`
370
371			`// update_ir state`
372			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
373			`begin`
374			`if(trst_pad_i)`
375			`update_ir<=#1 1'b0;`
376			`else`
377			`if(tms_pad_i & (exit1_ir \| exit2_ir))`
378			`update_ir<=#1 1'b1;`
379			`else`
380			`update_ir<=#1 1'b0;`
381			`end`
382
383			`/**********************************************************************************`
384			`* *`
385			`* End: TAP State Machine *`
386			`* *`
387			`**********************************************************************************/`
388
389
390
391			`/**********************************************************************************`
392			`* *`
393			`* jtag_ir: JTAG Instruction Register *`
394			`* *`
395			`**********************************************************************************/`
396			reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
397			reg [`IR_LENGTH-1:0] latched_jtag_ir;
398			`reg instruction_tdo;`
399
400			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
401			`begin`
402			`if(trst_pad_i)`
403			jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0;
404			`else`
405			`if(capture_ir)`
406			`jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection`
407			`else`
408			`if(shift_ir)`
409			jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
410			`end`
411
412			`always @ (negedge tck_pad_i)`
413			`begin`
414			`instruction_tdo <= #1 jtag_ir[0];`
415			`end`
416			`/**********************************************************************************`
417			`* *`
418			`* End: jtag_ir *`
419			`* *`
420			`**********************************************************************************/`
421
422
423			`/**********************************************************************************`
424			`* *`
425			`* jtag_dr: JTAG Data Register *`
426			`* *`
427			`**********************************************************************************/`
428			reg [`DR_LENGTH-1:0] jtag_dr; // Data register
429			reg [`DR_LENGTH-1:0] latched_jtag_dr;
430			`reg data_tdo;`
431
432			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
433			`begin`
434			`if(trst_pad_i)`
435			jtag_dr[`DR_LENGTH-1:0] <= #1 `DR_LENGTH'b0;
436			`else`
437			`if(capture_dr)`
438			`jtag_dr <= #1 4'b0101; // This value is fixed for easier fault detection`
439			`else`
440			`if(shift_dr)`
441			jtag_dr[`DR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_dr[`DR_LENGTH-1:1]};
442			`end`
443
444			`always @ (negedge tck_pad_i)`
445			`begin`
446			`data_tdo <= #1 jtag_dr[0];`
447			`end`
448			`/**********************************************************************************`
449			`* *`
450			`* End: jtag_dr *`
451			`* *`
452			`**********************************************************************************/`
453
454
455			`/**********************************************************************************`
456			`* *`
457			`* idcode logic *`
458			`* *`
459			`**********************************************************************************/`
460			`reg [31:0] idcode_reg;`
461			`reg idcode_tdo;`
462
463			`always @ (posedge tck_pad_i)`
464			`begin`
465			`if(idcode_select & shift_dr)`
466			`idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};`
467			`else`
468			idcode_reg <= #1 `IDCODE_VALUE;
469			`end`
470
471			`always @ (negedge tck_pad_i)`
472			`begin`
473			`idcode_tdo <= #1 idcode_reg;`
474			`end`
475			`/**********************************************************************************`
476			`* *`
477			`* End: idcode logic *`
478			`* *`
479			`**********************************************************************************/`
480
481
482			`/**********************************************************************************`
483			`* *`
484			`* Bypass logic *`
485			`* *`
486			`**********************************************************************************/`
487			`reg bypassed_tdo;`
488			`reg bypass_reg;`
489
490			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
491			`begin`
492			`if (trst_pad_i)`
493			`bypass_reg<=#1 1'b0;`
494			`else if(shift_dr)`
495			`bypass_reg<=#1 tdi_pad_i;`
496			`end`
497
498			`always @ (negedge tck_pad_i)`
499			`begin`
500			`bypassed_tdo <=#1 bypass_reg;`
501			`end`
502			`/**********************************************************************************`
503			`* *`
504			`* End: Bypass logic *`
505			`* *`
506			`**********************************************************************************/`
507
508
509			`/**********************************************************************************`
510			`* *`
511			`* Activating Instructions *`
512			`* *`
513			`**********************************************************************************/`
514			`// Updating jtag_ir (Instruction Register)`
515			`always @ (posedge tck_pad_i or posedge trst_pad_i)`
516			`begin`
517			`if(trst_pad_i)`
518			latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset
519			`else`
520			`if(update_ir)`
521			`latched_jtag_ir <=#1 jtag_ir;`
522			`end`
523
524			`/**********************************************************************************`
525			`* *`
526			`* End: Activating Instructions *`
527			`* *`
528			`**********************************************************************************/`
529
530
531			`// Updating jtag_ir (Instruction Register)`
532			`always @ (latched_jtag_ir)`
533			`begin`
534			`extest_select = 1'b0;`
535			`sample_preload_select = 1'b0;`
536			`idcode_select = 1'b0;`
537			`mbist_select = 1'b0;`
538			`debug_select = 1'b0;`
539			`bypass_select = 1'b0;`
540
541			`case(latched_jtag_ir) /* synthesis parallel_case */`
542			`EXTEST: extest_select = 1'b1; // External test
543			`SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
544			`IDCODE: idcode_select = 1'b1; // ID Code
545			`MBIST: mbist_select = 1'b1; // Mbist test
546			`DEBUG: debug_select = 1'b1; // Debug
547			`BYPASS: bypass_select = 1'b1; // BYPASS
548			`default: bypass_select = 1'b1; // BYPASS`
549			`endcase`
550			`end`
551
552
553
554			`/**********************************************************************************`
555			`* *`
556			`* Multiplexing TDO data *`
557			`* *`
558			`**********************************************************************************/`
559
560			`always @ (shift_ir or exit1_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or`
561			`debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or`
562			`bypassed_tdo)`
563			`begin`
564			`if(shift_ir)`
565			`tdo_pad_o <=#1 instruction_tdo;`
566			`else`
567			`begin`
568			`case(latched_jtag_ir) // synthesis parallel_case`
569			`IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
570			`DEBUG: tdo_pad_o = debug_tdi_i; // Debug
571			`SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
572			`EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
573			`MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
574			`default: tdo_pad_o = bypassed_tdo; // BYPASS instruction`
575			`endcase`
576			`end`
577			`end`
578
579
580			`// Tristate control for tdo_pad_o pin`
581			`always @ (negedge tck_pad_i)`
582			`begin`
583			`tdo_padoe_o <= #1 shift_ir \| shift_dr \| (pause_dr & debug_select);`
584			`end`
585			`/**********************************************************************************`
586			`* *`
587			`* End: Multiplexing TDO data *`
588			`* *`
589			`**********************************************************************************/`
590
591
592
593
594			`endmodule`