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[/] [k68/] [trunk/] [doc/] [68REF.TXT] - Blame information for rev 4

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1 2 sybreon
Motorola 68000 Instruction Set.
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-------------------------------
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                                                               Condition Codes
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                                                               ---------------
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                                          Assembler   Data
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Instruction Description                    Syntax     Size        X N Z V C
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-----------------------                   ---------   ----        ---------
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ABCD     Add BCD with extend                Dx,Dy      B--        * U * U *
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                                         -(Ax),-(Ay)
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ADD      ADD binary                        Dn,     BWL        * * * * *
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                                           ,Dn
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ADDA     ADD binary to An                  ,An     -WL        - - - - -
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ADDI     ADD Immediate                     #x,     BWL        * * * * *
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ADDQ     ADD 3-bit immediate             #<1-8>,   BWL        * * * * *
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ADDX     ADD eXtended                       Dy,Dx      BWL        * * * * *
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                                         -(Ay),-(Ax)
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AND      Bit-wise AND                      ,Dn     BWL        - * * 0 0
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                                           Dn,
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ANDI     Bit-wise AND with Immediate    #,   BWL        - * * 0 0
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ASL      Arithmetic Shift Left            #<1-8>,Dy    BWL        * * * * *
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                                            Dx,Dy
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ASR      Arithmetic Shift Right              ...       BWL        * * * * *
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Bcc      Conditional Branch            Bcc.S 
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                                       Bcc.W 
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BCHG     Test a Bit and CHanGe             Dn,     B-L        - - * - -
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                                        #,
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BCLR     Test a Bit and CLeaR                ...       B-L        - - * - -
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BSET     Test a Bit and SET                  ...       B-L        - - * - -
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BSR      Branch to SubRoutine          BSR.S 
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                                       BSR.W 
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BTST     Bit TeST                          Dn,     B-L        - - * - -
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                                        #,
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CHK      CHecK Dn Against Bounds           ,Dn     -W-        - * U U U
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CLR      CLeaR                                     BWL        - 0 1 0 0
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CMP      CoMPare                           ,Dn     BWL        - * * * *
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CMPA     CoMPare Address                   ,An     -WL        - * * * *
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CMPI     CoMPare Immediate              #,   BWL        - * * * *
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CMPM     CoMPare Memory                  (Ay)+,(Ax)+   BWL        - * * * *
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DBcc     Looping Instruction          DBcc Dn,
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DIVS     DIVide Signed                     ,Dn     -W-        - * * * 0
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DIVU     DIVide Unsigned                   ,Dn     -W-        - * * * 0
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EOR      Exclusive OR                      Dn,     BWL        - * * 0 0
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EORI     Exclusive OR Immediate         #,   BWL        - * * 0 0
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EXG      Exchange any two registers         Rx,Ry      --L        - - - - -
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EXT      Sign EXTend                         Dn        -WL        - * * 0 0
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ILLEGAL  ILLEGAL-Instruction Exception     ILLEGAL                - - - - -
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JMP      JuMP to Affective Address                            - - - - -
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JSR      Jump to SubRoutine                                   - - - - -
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LEA      Load Effective Address            ,An     --L        - - - - -
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LINK     Allocate Stack Frame       An,#            - - - - -
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LSL      Logical Shift Left                 Dx,Dy      BWL        * * * 0 *
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                                          #<1-8>,Dy
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LSR      Logical Shift Right                 ...       BWL        * * * 0 *
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MOVE     Between Effective Addresses      ,    BWL        - * * 0 0
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MOVE     To CCR                           ,CCR     -W-        I I I I I
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MOVE     To SR                             ,SR     -W-        I I I I I
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MOVE     From SR                           SR,     -W-        - - - - -
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MOVE     USP to/from Address Register      USP,An      --L        - - - - -
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                                           An,USP
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MOVEA    MOVE Address                      ,An     -WL        - - - - -
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MOVEM    MOVE Multiple            , -WL        - - - - -
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                                  ,
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---------- Page 2. CUT HERE. ----------
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MOVEP    MOVE Peripheral                  Dn,x(An)     -WL        - - - - -
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                                          x(An),Dn
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MOVEQ    MOVE 8-bit immediate         #<-128.+127>,Dn  --L        - * * 0 0
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MULS     MULtiply Signed                   ,Dn     -W-        - * * 0 0
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MULU     MULtiply Unsigned                 ,Dn     -W-        - * * 0 0
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NBCD     Negate BCD                                B--        * U * U *
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NEG      NEGate                                    BWL        * * * * *
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NEGX     NEGate with eXtend                        BWL        * * * * *
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NOP      No OPeration                        NOP                  - - - - -
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NOT      Form one's complement                     BWL        - * * 0 0
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OR       Bit-wise OR                       ,Dn     BWL        - * * 0 0
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                                           Dn,
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ORI      Bit-wise OR with Immediate     #,   BWL        - * * 0 0
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PEA      Push Effective Address                    --L        - - - - -
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RESET    RESET all external devices         RESET                 - - - - -
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ROL      ROtate Left                      #<1-8>,Dy    BWL        - * * 0 *
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                                            Dx,Dy
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ROR      ROtate Right                        ...       BWL        - * * 0 *
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ROXL     ROtate Left with eXtend             ...       BWL        * * * 0 *
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ROXR     ROtate Right with eXtend            ...       BWL        * * * 0 *
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RTE      ReTurn from Exception               RTE                  I I I I I
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RTR      ReTurn and Restore                  RTR                  I I I I I
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RTS      ReTurn from Subroutine              RTS                  - - - - -
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SBCD     Subtract BCD with eXtend           Dx,Dy      B--        * U * U *
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                                         -(Ax),-(Ay)
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Scc      Set to -1 if True, 0 if False             B--        - - - - -
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STOP     Enable & wait for interrupts      #                I I I I I
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SUB      SUBtract binary                   Dn,     BWL        * * * * *
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                                           ,Dn
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SUBA     SUBtract binary from An           ,An     -WL        - - - - -
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SUBI     SUBtract Immediate                #x,     BWL        * * * * *
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SUBQ     SUBtract 3-bit immediate       #,   BWL        * * * * *
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SUBX     SUBtract eXtended                  Dy,Dx      BWL        * * * * *
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                                         -(Ay),-(Ax)
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SWAP     SWAP words of Dn                    Dn        -W-        - * * 0 0
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TAS      Test & Set MSB & Set N/Z-bits             B--        - * * 0 0
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TRAP     Execute TRAP Exception           #               - - - - -
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TRAPV    TRAPV Exception if V-bit Set       TRAPV                 - - - - -
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TST      TeST for negative or zero                 BWL        - * * 0 0
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UNLK     Deallocate Stack Frame              An                   - - - - -
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                           --------------------------
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Symbol   Meaning
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------   -------
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   *     Set according to result of operation
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   -     Not affected
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   1     Set
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   U     Outcome (state after operation) undefined
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   I     Set by immediate data
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     Effective Address Operand
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   Immediate data
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 TRAP instruction Exception vector (0-15)
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 MOVEM instruction register specification list
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 LINK instruction negative displacement
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...      Same as previous instruction
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                           --------------------------
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---------- Page 3. CUT HERE. ----------
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Addressing Modes                                   Syntax
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----------------                                   ------
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Data Register Direct                                 Dn
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Address Register Direct                              An
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Address Register Indirect                           (An)
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Address Register Indirect with Post-Increment       (An)+
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Address Register Indirect with Pre-Decrement        -(An)
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Address Register Indirect with Displacement         w(An)
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Address Register Indirect with Index               b(An,Rx)
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Absolute Short                                        w
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Absolute Long                                         l
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Program Counter with Displacement                   w(PC)
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Program Counter with Index                         b(PC,Rx)
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Immediate                                            #x
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Status Register                                      SR
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Condition Code Register                              CCR
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Legend
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------
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   Dn    Data Register        (n is 0-7)
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   An    Address Register     (n is 0-7)
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    b    08-bit constant
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    w    16-bit constant
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    l    32-bit constant
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    x    8-, 16-, 32-bit constant
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   Rx    Index Register Specification, one of:
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            Dn.W  Low 16 bits of Data Register
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            Dn.L  All 32 bits of Data Register
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            An.W  Low 16 bits of Address Register
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            An.L  All 32 bits of Address Register
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                           --------------------------
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         Condition Codes for Bcc, DBcc and Scc Instructions.
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         ---------------------------------------------------
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           Condition Codes set after CMP D0,D1 Instruction.
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Relationship      Unsigned                         Signed
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------------      --------                         ------
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D1 <  D0          CS - Carry Bit Set               LT - Less Than
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D1 <= D0          LS - Lower or Same               LE - Less than or Equal
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D1  = D0          EQ - Equal (Z-bit Set)           EQ - Equal (Z-bit Set)
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D1 != D0          NE - Not Equal (Z-bit Clear)     NE - Not Equal (Z-bit Clear)
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D1 >  D0          HI - HIgher than                 GT - Greater Than
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D1 >= D0          CC - Carry Bit Clear             GE - Greater than or Equal
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                  PL - PLus (N-bit Clear)          MI - Minus (N-bit Set)
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                  VC - V-bit Clear (No Overflow)   VS - V-bit Set (Overflow)
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                  RA - BRanch Always
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DBcc Only    -     F - Never Terminate (DBRA is an alternate to DBF)
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                   T - Always Terminate
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Scc Only     -    SF - Never Set
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                  ST - Always Set
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                           --------------------------
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Parts from "Programming the 68000" by Steve Williams. (c) 1985 Sybex Inc.
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Parts from BYTE Magazine article.
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Compiled by Diego Barros.        e-mail : alien@zikzak.apana.org.au
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Revision 2.1                     22 May, 1994
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