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//                              -*- Mode: Verilog -*-
2 
// Filename        : k68_execute.v
3 
// Description     : RISC 68k ALU
4 
// Author          : Shawn Tan
5 
// Created On      : Sun Feb  9 00:05:41 2003
6 
// Last Modified By: .
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// Last Modified On: .
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// Update Count    : 0
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// Status          : Unknown, Use with caution!
10 
/////////////////////////////////////////////////////////////////////
11 
////                                                             ////
12 
//// Copyright (C) 2002 to Shawn Tan Ser Ngiap.                  ////
13 
////                       shawn.tan@aeste.net                   ////
14 
////                                                             ////
15 
//// This source file may be used and distributed without        ////
16 
//// restriction provided that this copyright statement is not   ////
17 
//// removed from the file and that any derivative work contains ////
18 
//// the original copyright notice and the associated disclaimer.////
19 
////                                                             ////
20 
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
21 
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
22 
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
23 
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
24 
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
25 
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
26 
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
27 
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
32 
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
34 
/////////////////////////////////////////////////////////////////////
35 
 
36 
`include "k68_defines.v"
37 
 
38 
module k68_execute (/*AUTOARG*/
39 
   // Outputs
40 
   res_o, ccr_o, ssr_o, add_c_o, alu_o, siz_o, pc_o,
41 
   // Inputs
42 
   clk_i, rst_i, alu_i, src_i, dst_i, add_src_i, add_dst_i, siz_i,
43 
   pc_i, int_i, skip_i
44 
   ) ;
45 
 
46 
   parameter dw = `k68_DATA_W;
47 
   parameter lw = `k68_ALU_W;
48 
   parameter kw = 6;
49 
   parameter sw = `k68_SCR_W;
50 
   parameter zero = `ZERO;
51 
   parameter xxxx = `XXXX;
52 
   parameter esc = `ESC;
53 
   parameter aw = `k68_ADDR_W;
54 
   parameter ccr = `k68_RST_CCR;
55 
   parameter ssr = `k68_RST_SSR;
56 
 
57 
   // FLAGS
58 
   parameter ZF = `k68_Z_FLAG;
59 
   parameter CF = `k68_C_FLAG;
60 
   parameter VF = `k68_V_FLAG;
61 
   parameter NF = `k68_N_FLAG;
62 
   parameter XF = `k68_X_FLAG;
63 
 
64 
   // ALUOPS
65 
   parameter ALU_ABCD = `k68_ALU_ABCD;
66 
   parameter ALU_SBCD = `k68_ALU_SBCD;
67 
   parameter ALU_NBCD = `k68_ALU_NBCD;
68 
   parameter ALU_ADD = `k68_ALU_ADD;
69 
   parameter ALU_ADDX = `k68_ALU_ADDX;
70 
   parameter ALU_SUB = `k68_ALU_SUB;
71 
   parameter ALU_SUBX = `k68_ALU_SUBX;
72 
   parameter ALU_OR = `k68_ALU_OR;
73 
   parameter ALU_AND = `k68_ALU_AND;
74 
   parameter ALU_EOR = `k68_ALU_EOR;
75 
   parameter ALU_BTST = `k68_ALU_BTST;
76 
   parameter ALU_BCHG = `k68_ALU_BCHG;
77 
   parameter ALU_BCLR = `k68_ALU_BCLR;
78 
   parameter ALU_BSET = `k68_ALU_BSET;
79 
   parameter ALU_MOV = `k68_ALU_MOV;
80 
   parameter ALU_DIV = `k68_ALU_DIV;
81 
   parameter ALU_MUL = `k68_ALU_MUL;
82 
   parameter ALU_ASX = `k68_ALU_ASX;
83 
   parameter ALU_LSX = `k68_ALU_LSX;
84 
   parameter ALU_ROX = `k68_ALU_ROX;
85 
   parameter ALU_ROXX = `k68_ALU_ROXX;
86 
   parameter ALU_NOT = `k68_ALU_NOT;
87 
   parameter ALU_NOP = `k68_ALU_NOP;
88 
   parameter ALU_NEGX = `k68_ALU_NEGX;
89 
   parameter ALU_NEG = `k68_ALU_NEG;
90 
 
91 
   parameter ALU_ANDSR = `k68_ALU_ANDSR;
92 
   parameter ALU_ORSR = `k68_ALU_ORSR;
93 
   parameter ALU_EORSR = `k68_ALU_EORSR;
94 
   parameter ALU_MOVSR = `k68_ALU_MOVSR;
95 
 
96 
   parameter ALU_BCC = `k68_ALU_BCC;
97 
   parameter ALU_DBCC = `k68_ALU_DBCC;
98 
   parameter ALU_SCC = `k68_ALU_SCC;
99 
   parameter ALU_SWAP = `k68_ALU_SWAP;
100 
   parameter ALU_STOP = `k68_ALU_STOP;
101 
 
102 
   parameter ALU_VECTOR = `k68_ALU_VECTOR;
103 
   parameter ALU_TAS = `k68_ALU_TAS;
104 
   parameter ALU_TST = `k68_ALU_TST;
105 
   parameter ALU_EA = `k68_ALU_EA;
106 
   parameter ALU_CMP = `k68_ALU_CMP;
107 
 
108 
   output [dw-1:0] res_o;
109 
   output [7:0]    ccr_o, ssr_o;
110 
   output [kw-1:0] add_c_o;
111 
   output [lw-1:0] alu_o;
112 
   output [1:0]    siz_o;
113 
   reg [1:0]        siz_o;
114 
 
115 
   input           clk_i, rst_i;
116 
   input [lw-1:0]  alu_i;
117 
   input [dw-1:0]  src_i, dst_i;
118 
   input [kw-1:0]  add_src_i, add_dst_i;
119 
   input [1:0]      siz_i;
120 
   input [aw-1:0]  pc_i;
121 
   input [2:0]      int_i;
122 
   output [aw-1:0] pc_o;
123 
   input [1:0]      skip_i;
124 
 
125 
   reg [dw-1:0]    res_o;
126 
   reg [sw-1:0]    ccr_o, ssr_o;
127 
   reg [kw-1:0]    add_c_o, add_c;
128 
   reg [lw-1:0]    alu_o, alu;
129 
   reg [aw-1:0]    pc_o, pc;
130 
   reg [dw-1:0]    src,dst;
131 
   reg [dw-1:0]     res;
132 
 
133 
   wire [7:0]       d2ba,d2bb,b2d;
134 
   wire            flag;
135 
   reg [7:0]        bcd;
136 
   wire [dw-1:0]   res_rox,res_lsx,res_asx,res_roxx;
137 
   wire            x;
138 
   reg             c;
139 
 
140 
 
141 
   //
142 
   // Sync Output
143 
   // res_o, add_c_o, ccr_o, ssr_o;
144 
   //
145 
   always @ (posedge clk_i) begin
146 
      if (rst_i) begin
147 
         /*AUTORESET*/
148 
         // Beginning of autoreset for uninitialized flops
149 
         add_c_o <= 0;
150 
         alu_o <= 0;
151 
         ccr_o <= 0;
152 
         pc_o <= 0;
153 
         res_o <= 0;
154 
         siz_o <= 0;
155 
         ssr_o <= 0;
156 
         // End of automatics
157 
 
158 
         ssr_o <= ssr;
159 
         ccr_o <= ccr;
160 
 
161 
      end else begin
162 
 
163 
         pc_o <= pc_i+{skip_i,1'b0};
164 
         alu_o <= alu;
165 
         add_c_o <= add_c;
166 
         siz_o <= siz_i;
167 
 
168 
         //
169 
         // Modify CCR
170 
         //
171 
         case (alu_i)
172 
           ALU_ABCD, ALU_SBCD, ALU_NBCD: begin
173 
              ccr_o[XF] <= c;
174 
              ccr_o[NF] <= 1'bX;
175 
              ccr_o[ZF] <= (res[31:0] == zero) & ccr_o[ZF];
176 
              ccr_o[VF] <= 1'bx;
177 
              ccr_o[CF] <= c;
178 
           end
179 
           ALU_ADD: begin
180 
              ccr_o[XF] <= src[31] & dst[31] | ~res[31] & dst[31] | src[31] & ~res[31];
181 
              ccr_o[NF] <= res[31];
182 
              ccr_o[ZF] <= (res[31:0] == zero);
183 
              ccr_o[VF] <= src[31] & dst[31] & ~res[31] | ~src[31] & ~dst[31] & res[31];
184 
              ccr_o[CF] <= src[31] & dst[31] | ~res[31] & dst[31] | src[31] & ~res[31];
185 
           end
186 
           ALU_ADDX: begin
187 
              ccr_o[XF] <= src[31] & dst[31] | ~res[31] & dst[31] | src[31] & ~res[31];
188 
              ccr_o[NF] <= ccr_o[NF];
189 
              ccr_o[ZF] <= (res[31:0] == zero) & ccr_o[ZF];
190 
              ccr_o[VF] <= src[31] & dst[31] & ~res[31] | ~src[31] & ~dst[31] & res[31];
191 
              ccr_o[CF] <= src[31] & dst[31] | ~res[31] & dst[31] | src[31] & ~res[31];
192 
           end
193 
           ALU_MOV,ALU_AND,ALU_EOR,ALU_OR,ALU_NOT,ALU_TAS,ALU_TST: begin
194 
              ccr_o[XF] <= ccr_o[XF];
195 
              ccr_o[NF] <= res[31];
196 
              ccr_o[ZF] <= (res[31:0] == zero);
197 
              ccr_o[VF] <= 1'b0;
198 
              ccr_o[CF] <= 1'b0;
199 
           end
200 
           ALU_SUB: begin
201 
              ccr_o[XF] <= src[31] & ~dst[31] | res[31] & ~dst[31] | src[31] & res[31];
202 
              ccr_o[NF] <= res[31];
203 
              ccr_o[ZF] <= (res[31:0] == zero);
204 
              ccr_o[VF] <= ~src[31] & dst[31] & ~res[31] | src[31] & ~dst[31] & res[31];
205 
              ccr_o[CF] <= src[31] & ~dst[31] | res[31] & ~dst[31] | src[31] & res[31];
206 
           end
207 
           ALU_SUBX: begin
208 
              ccr_o[XF] <= src[31] & ~dst[31] | res[31] & ~dst[31] | src[31] & res[31];
209 
              ccr_o[NF] <= res[31];
210 
              ccr_o[ZF] <= (res[31:0] == zero) & ccr_o[ZF];
211 
              ccr_o[VF] <= ~src[31] & dst[31] & ~res[31] | src[31] & ~dst[31] & res[31];
212 
              ccr_o[CF] <= src[31] & ~dst[31] | res[31] & ~dst[31] | src[31] & res[31];
213 
           end
214 
           ALU_CMP: begin
215 
              ccr_o[XF] <= ccr_o[XF];
216 
              ccr_o[NF] <= res[31];
217 
              ccr_o[XF] <= (res[31:0] == zero);
218 
              ccr_o[VF] <= ~src[31] & dst[31] & ~res[31] | src[31] & ~dst[31] & res[31];
219 
              ccr_o[CF] <= src[31] & ~dst[31] | res[31] & ~dst[31] | src[31] & res[31];
220 
           end
221 
`ifdef k68_DIVX
222 
           ALU_DIV: begin
223 
              ccr_o[XF] <= ccr_o[XF];
224 
              ccr_o[NF] <= res[31];
225 
              ccr_o[ZF] <= (res[31:0]==zero);
226 
              ccr_o[VF] <= c;
227 
              ccr_o[CF] <= 1'b0;
228 
           end
229 
`endif
230 
`ifdef k68_MULX
231 
           ALU_MUL: begin
232 
              ccr_o[XF] <= ccr_o[XF];
233 
              ccr_o[NF] <= res[31];
234 
              ccr_o[ZF] <= (res[31:0]==zero);
235 
              ccr_o[VF] <= c;
236 
              ccr_o[CF] <= 1'b0;
237 
           end
238 
`endif
239 
           ALU_NEG: begin
240 
              ccr_o[XF] <= dst[31] | res[31];
241 
              ccr_o[NF] <= res[31];
242 
              ccr_o[ZF] <= (res[31:0] == zero);
243 
              ccr_o[VF] <= dst[31] & res[31];
244 
              ccr_o[CF] <= dst[31] | res[31];
245 
           end
246 
           ALU_NEGX: begin
247 
              ccr_o[XF] <= dst[31] | res[31];
248 
              ccr_o[NF] <= res[31];
249 
              ccr_o[ZF] <= (res[31:0] == zero) & ccr_o[ZF];
250 
              ccr_o[VF] <= dst[31] & res[31];
251 
              ccr_o[CF] <= dst[31] | res[31];
252 
           end
253 
           ALU_BSET,ALU_BTST,ALU_BCLR,ALU_BCHG: begin
254 
              ccr_o[XF] <= ccr_o[XF];
255 
              ccr_o[NF] <= ccr_o[NF];
256 
              ccr_o[VF] <= ccr_o[VF];
257 
              ccr_o[CF] <= ccr_o[CF];
258 
              ccr_o[ZF] <= ~dst[src[28:24]];
259 
           end
260 
           ALU_ROX: begin
261 
              ccr_o[XF] <= ccr_o[XF];
262 
              ccr_o[NF] <= res[31];
263 
              ccr_o[ZF] <= (res[31:0] == zero);
264 
              ccr_o[VF] <= 1'b0;
265 
              ccr_o[CF] <= x;
266 
           end
267 
`ifdef k68_LSX
268 
           ALU_LSX: begin
269 
              ccr_o[XF] <= x;
270 
              ccr_o[NF] <= res[31];
271 
              ccr_o[ZF] <= (res[31:0] == zero);
272 
              ccr_o[VF] <= 1'b0;
273 
              ccr_o[CF] <= x;
274 
           end
275 
`endif
276 
`ifdef k68_ROXX
277 
           ALU_ROXX: begin
278 
              ccr_o[XF] <= x;
279 
              ccr_o[NF] <= res[31];
280 
              ccr_o[ZF] <= (res[31:0] == zero);
281 
              ccr_o[VF] <= 1'b0;
282 
              ccr_o[CF] <= x;
283 
           end
284 
`endif
285 
`ifdef k68_ASX
286 
           ALU_ASX: begin
287 
              ccr_o[XF] <= x;
288 
              ccr_o[NF] <= res[31];
289 
              ccr_o[ZF] <= (res[31:0] == zero);
290 
              ccr_o[VF] <= 1'b0;
291 
              ccr_o[CF] <= x;
292 
           end
293 
`endif
294 
           ALU_MOVSR: {ssr_o, ccr_o} <= res[31:16];
295 
           ALU_STOP: {ssr_o,ccr_o} <= src[15:0];
296 
           default: begin
297 
              ccr_o <= ccr_o;
298 
              ssr_o <= {ssr_o[7:3],int_i};
299 
           end
300 
 
301 
         endcase // case(alu_i)
302 
 
303 
         // ****************************************************
304 
 
305 
         //
306 
         // Set res
307 
         //
308 
         case (siz_i)
309 
           2'b00: res_o <= {dst_i[31:8],res[31:24]}; // BYTE
310 
           2'b01: res_o <= {dst_i[31:16],res[31:16]}; // WORD
311 
           default: res_o <= res[31:0]; // LONG
312 
           //default: res_o <= dst_i; // PASSTHROUGH
313 
         endcase // case(siz_i)
314 
      end// else: !if(run_i)
315 
 
316 
   end
317 
 
318 
   //
319 
   // Async Stuff, Actual ALU
320 
   //
321 
   always @ (/*AUTOSENSE*/add_c_o or add_dst_i or add_src_i or alu_i
322 
             or dst_i or res_o or rst_i or siz_i or src_i) begin
323 
      if (rst_i) begin
324 
         /*AUTORESET*/
325 
         // Beginning of autoreset for uninitialized flops
326 
         dst <= 0;
327 
         src <= 0;
328 
         // End of automatics
329 
      end else begin
330 
 
331 
         //
332 
         // Fit src and dst with Operand Forwarding & Special OP Ignore
333 
         //
334 
         case(alu_i)
335 
           ALU_ROX:
336 
             case (siz_i)
337 
               2'b00: begin // BYTE
338 
                  src <= {src_i[7:0],src_i[7:0],src_i[7:0],src_i[7:0]};
339 
                  if ((add_dst_i == add_c_o) && ~(add_c_o == 6'b111100) && ~(add_c_o == esc))
340 
                    dst <= {res_o[7:0],res_o[7:0],res_o[7:0],res_o[7:0]};
341 
                  else
342 
                    dst <= {dst_i[7:0],dst_i[7:0],dst_i[7:0],dst_i[7:0]};
343 
               end
344 
               2'b01: begin // WORD
345 
                  src <= {src_i[15:0],src_i[15:0]};
346 
                  if ((add_dst_i == add_c_o) && ~(add_c_o == 6'b111100) && ~(add_c_o == esc))
347 
                    dst <= {res_o[15:0],res_o[15:0]};
348 
                  else
349 
                    dst <= {dst_i[15:0],dst_i[15:0]};
350 
               end
351 
               default: begin // LONG
352 
                  src <= src_i;
353 
                  if ((add_dst_i == add_c_o) && ~(add_c_o == 6'b111100) && ~(add_c_o == esc))
354 
                    dst <= res_o;
355 
                  else
356 
                    dst <= dst_i;
357 
               end
358 
             endcase // case(siz_i)
359 
 
360 
           default:
361 
             case (siz_i)
362 
               2'b00: begin // BYTE
363 
                  if ((add_src_i == add_c_o) && ~(add_c_o == 6'b111100) && ~(add_c_o == esc))
364 
                    src <= {res_o[7:0],24'd0};
365 
                  else
366 
                    src <= {src_i[7:0],24'd0};
367 
                  if ((add_dst_i == add_c_o) && ~(add_c_o == 6'b111100) && ~(add_c_o == esc))
368 
                    dst <= {res_o[7:0],24'd0};
369 
                  else
370 
                    dst <= {dst_i[7:0],24'd0};
371 
               end
372 
               2'b01: begin // WORD
373 
                  if ((add_src_i == add_c_o) && ~(add_c_o == 6'b111100) && ~(add_c_o == esc))
374 
                    src <= {res_o[15:0],16'd0};
375 
                  else
376 
                    src <= {src_i[15:0],16'd0};
377 
                  if ((add_dst_i == add_c_o) && ~(add_c_o == 6'b111100) && ~(add_c_o == esc))
378 
                    dst <= {res_o[15:0],16'd0};
379 
                  else
380 
                    dst <= {dst_i[15:0],16'd0};
381 
               end
382 
               default: begin // LONG
383 
                  if ((add_src_i == add_c_o) && ~(add_c_o == 6'b111100) && ~(add_c_o == esc))
384 
                    src <= res_o;
385 
                  else
386 
                    src <= src_i;
387 
                  if ((add_dst_i == add_c_o) && ~(add_c_o == 6'b111100) && ~(add_c_o == esc))
388 
                    dst <= res_o;
389 
                  else
390 
                    dst <= dst_i;
391 
               end
392 
             endcase // case(siz_i)
393 
         endcase // case(alu_i)
394 
 
395 
      end // else: !if(rst_i)
396 
   end // always @ (...
397 
 
398 
 
399 
 
400 
   always @(/*AUTOSENSE*/add_dst_i or add_src_i or alu_i or b2d
401 
            or ccr_o or d2ba or d2bb or dst or flag or pc_i or res_asx
402 
            or res_lsx or res_rox or res_roxx or rst_i or src or ssr_o) begin
403 
      if (rst_i) begin
404 
         /*AUTORESET*/
405 
         // Beginning of autoreset for uninitialized flops
406 
         add_c <= 0;
407 
         alu <= 0;
408 
         bcd <= 0;
409 
         c <= 0;
410 
         pc <= 0;
411 
         res <= 0;
412 
         // End of automatics
413 
      end else begin
414 
         // ***************************************************
415 
 
416 
         alu <= alu_i;
417 
         pc <= pc_i;
418 
         //add_c <= add_dst_i;
419 
 
420 
         //
421 
         // Modify results... Actual Execution
422 
         //
423 
         case (alu_i)
424 
 
425 
           // ARITHMETIC
426 
           ALU_ADD: begin
427 
              res <= src + dst;//res_a;
428 
              add_c <= add_dst_i;
429 
           end
430 
           ALU_SUB: begin
431 
              res <= dst - src;
432 
              add_c <= add_dst_i;
433 
           end
434 
`ifdef k68_MULX
435 
           ALU_MUL: begin
436 
              res <= dst;
437 
              add_c <= add_dst_i;
438 
           end
439 
`endif
440 
`ifdef k68_DIVX
441 
           ALU_DIV: begin
442 
              res <= dst;
443 
              add_c <= add_dst_i;
444 
           end
445 
`endif
446 
           ALU_NEG: begin
447 
              res <= zero - dst;
448 
              add_c <= add_dst_i;
449 
           end
450 
           ALU_ADDX: begin
451 
              res <= src + dst + ccr_o[XF];
452 
              add_c <= add_dst_i;
453 
           end
454 
           ALU_SUBX: begin
455 
              res <= dst - src - ccr_o[XF];
456 
              add_c <= add_dst_i;
457 
           end
458 
 
459 
           ALU_NEGX: begin
460 
              res <= zero - dst - ccr_o[XF];
461 
              add_c <= add_dst_i;
462 
           end
463 
 
464 
           // Compare
465 
           ALU_CMP: begin
466 
              res <= dst - src;
467 
              add_c <= esc;
468 
           end
469 
 
470 
           // BCDS
471 
           ALU_ABCD: begin
472 
              {res[31:0]} <= {b2d, 24'd0};
473 
              {c,bcd} <= d2ba + d2bb + ccr_o[XF];
474 
              add_c <= add_dst_i;
475 
           end
476 
           ALU_SBCD: begin
477 
              {res[31:0]} <= {b2d, 24'd0};
478 
              {c,bcd} <= d2bb - d2ba - ccr_o[XF];
479 
              add_c <= add_dst_i;
480 
           end
481 
           ALU_NBCD: begin
482 
              {res[31:0]} <= {b2d, 24'd0};
483 
              {c,bcd} <= 8'd0 - d2bb - ccr_o[XF];
484 
              add_c <= add_dst_i;
485 
           end
486 
 
487 
           // SHIFTS
488 
`ifdef k68_ASX
489 
           ALU_ASX: begin
490 
              res <= res_asx;
491 
              add_c <= add_dst_i;
492 
           end
493 
`endif
494 
`ifdef k68_LSX
495 
           ALU_LSX: begin
496 
              res <= res_lsx;
497 
              add_c <= add_dst_i;
498 
           end
499 
`endif
500 
`ifdef k68_ROXX
501 
           ALU_ROXX: begin
502 
              res <= res_roxx;
503 
              add_c <= add_dst_i;
504 
           end
505 
`endif
506 
           ALU_ROX: begin
507 
              res <= res_rox;
508 
              add_c <= add_dst_i;
509 
           end
510 
 
511 
           // LOGICS
512 
           ALU_AND: begin
513 
              res <= dst & src;
514 
              add_c <= add_dst_i;
515 
           end
516 
           ALU_OR: begin
517 
              res <= dst | src;
518 
              add_c <= add_dst_i;
519 
           end
520 
           ALU_EOR: begin
521 
              res <= dst ^ src;
522 
              add_c <= add_dst_i;
523 
           end
524 
           ALU_NOT: begin
525 
              res <= ~dst;
526 
              add_c <= add_dst_i;
527 
           end
528 
 
529 
           // SSR CCR
530 
           ALU_ANDSR: begin
531 
              res <= {ssr_o,ccr_o,16'd0} & src;
532 
              add_c <= add_dst_i;
533 
           end
534 
           ALU_ORSR: begin
535 
              res <= {ssr_o,ccr_o,16'd0} | src;
536 
              add_c <= add_dst_i;
537 
           end
538 
           ALU_EORSR: begin
539 
              res <= {ssr_o,ccr_o,16'd0} ^ src;
540 
              add_c <= add_dst_i;
541 
           end
542 
           ALU_MOVSR: begin
543 
              if(add_dst_i==6'h3C)
544 
                res <= { (ssr_o & dst[31:24]) | src[31:24] , src[23:16], 16'd0};
545 
              else
546 
                res <= {ssr_o, ccr_o, 16'd0};
547 
              add_c <= add_dst_i;
548 
           end
549 
 
550 
           // MOVS
551 
           ALU_MOV: begin
552 
              res <= src;
553 
              add_c <= add_dst_i;
554 
           end
555 
 
556 
           // BIT TESTS
557 
           ALU_BCHG: begin
558 
              res <= dst;
559 
              res[src[28:24]] <= ~dst[src[28:24]];
560 
              add_c <= add_dst_i;
561 
 
562 
           end
563 
           ALU_BCLR: begin
564 
              res <= dst;
565 
              res[src[28:24]] <= 1'b0;
566 
              add_c <= add_dst_i;
567 
 
568 
           end
569 
           ALU_BSET: begin
570 
              res <= dst;
571 
              res[src[28:24]] <= 1'b1;
572 
              add_c <= add_dst_i;
573 
           end
574 
           ALU_BTST: begin
575 
              res <= dst;
576 
              add_c <= 6'h3C;
577 
           end
578 
 
579 
 
580 
 
581 
           // BCC DBCC SCC
582 
           ALU_BCC:
583 
              case(flag)
584 
                1'b1: begin
585 
                   res <= src + dst;
586 
                   add_c <= add_dst_i;
587 
                end
588 
                default: begin
589 
                   res <= zero;
590 
                   add_c <= esc;
591 
                end
592 
              endcase // case(flag)
593 
 
594 
           ALU_SCC:
595 
             case (flag)
596 
               1'b1: begin
597 
                  res <= 32'hFFFFFFFF;
598 
                  add_c <= add_dst_i;
599 
               end
600 
               default: begin
601 
                  res <= zero;
602 
                  add_c <= add_dst_i;
603 
               end
604 
             endcase // case(flag)
605 
 
606 
//         ALU_DBCC:
607 
//           case (flag)
608 
//             1'b1: begin
609 
//                res <= dst;
610 
//                add_c <= 6'h3C;
611 
//                alu <= ALU_NOP;
612 
//             end
613 
//             default: begin
614 
//                res <= dst - 1'b1;
615 
//                add_c <= 6'h3C;
616 
//                case (res[15:0])
617 
//                  16'hFFFF: begin
618 
//                     pc <= pc_i + src_i;
619 
//                     alu <= ALU_DBCC;
620 
//                  end
621 
//                  default: begin
622 
//                     pc <= add_dst_i;
623 
//                     alu <= ALU_SCC;
624 
//                  end
625 
//                endcase // case(res[15:0])
626 
//             end
627 
//           endcase // case(flag)
628 
 
629 
 
630 
           // MISC
631 
           ALU_SWAP: begin
632 
              res <= {dst[15:0],dst[31:16]};
633 
              add_c <= add_dst_i;
634 
           end
635 
 
636 
           ALU_STOP: begin
637 
              res <= dst - 2'b10;
638 
              add_c <= 6'h3C;
639 
           end
640 
 
641 
           ALU_VECTOR: begin
642 
              case (add_src_i)
643 
                6'h3C: begin
644 
                   add_c <= 6'h3C;
645 
                   res <= ((src[5:0] + dst[5:0]) << 2) | 1'b1;
646 
                end
647 
                default:
648 
                  if (ccr_o[VF])  begin
649 
                       add_c <= 6'h3C;
650 
                       res <= ((src[5:0] + dst[5:0]) << 2) | 1'b1;
651 
                    end else begin
652 
                       add_c <= ALU_NOP;
653 
                       res <= zero;
654 
                    end
655 
              endcase // case(add_src_i)
656 
           end
657 
 
658 
           ALU_TAS: begin
659 
              res <= {1'b1, dst[30:0]};
660 
              add_c <= add_dst_i;
661 
           end
662 
 
663 
           ALU_TST: begin
664 
              res <= dst;
665 
              add_c <= add_dst_i;
666 
           end
667 
 
668 
           ALU_EA: begin
669 
              res <= dst;
670 
              add_c <= add_dst_i;
671 
           end
672 
 
673 
           default: begin
674 
              res <= zero;
675 
              add_c <= add_c;
676 
           end
677 
 
678 
         endcase // case(alu_i)
679 
 
680 
         // ****************************************************
681 
 
682 
      end
683 
 
684 
 
685 
   end
686 
 
687 
   //
688 
   // Instantiate Functions Blocks
689 
   // Shifters, Multipliers, Converters
690 
   //
691 
 
692 
   /********************************************************
693 
    *******************************************************
694 
    * *****************************************************/
695 
 
696 
 
697 
   //
698 
   // Shifters
699 
   //
700 
   k68_rox rox0(
701 
                .step(src[5:0]),
702 
                .in(dst),
703 
                .res(res_rox)
704 
                );
705 
 
706 
`ifdef k68_ASX
707 
   k68_asx asx0(
708 
                .step(src[5:0]),
709 
                .in(dst),
710 
                .res(res_asx)
711 
                );
712 
`endif
713 
`ifdef k68_LSX
714 
   k68_lsx lsx0(
715 
                .step(src[5:0]),
716 
                .in(dst),
717 
                .res(res_lsx)
718 
                );
719 
`endif
720 
`ifdef k68_ROXX
721 
   k68_rox roxx0(
722 
                .step(src[5:0]),
723 
                .in(dst),
724 
                .xin(ccr_o[XF]),
725 
                .res(res_roxx)
726 
                );
727 
`endif
728 
 
729 
   //
730 
   // K68 Multiplier. Instantiate your own hardware
731 
   // multiplier here. It must be single cycle operation
732 
   //
733 
`ifdef k68_MULX
734 
`endif
735 
 
736 
   //
737 
   // K68 Divider. Instantiate your own hardware
738 
   // divider here. It must be single cycle operation
739 
   //
740 
`ifdef k68_DIVX
741 
`endif
742 
 
743 
   //
744 
   //  BCD Convertors
745 
   //
746 
   k68_d2b d2b0(
747 
                .d(src[31:24]),
748 
                .b(d2ba)
749 
                );
750 
 
751 
   k68_d2b d2b1(
752 
                .d(dst[31:24]),
753 
                .b(d2bb)
754 
                );
755 
 
756 
   k68_b2d b2d0(
757 
                .b(bcd),
758 
                .d(b2d)
759 
                );
760 
 
761 
 
762 
   //
763 
   // Conditional Code Checker for Xcc kind of instructions
764 
   //
765 
   k68_ccc ccc0(
766 
                .cc(ccr_o),
767 
                .code(add_src_i[3:0]),
768 
                .flag(flag)
769 
                );
770 
 
771 
 
772 
endmodule // k68_execute
773 
 

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