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[/] [k68/] [trunk/] [rtl/] [verilog/] [k68_fetch.v] - Blame information for rev 4

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//                              -*- Mode: Verilog -*-
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// Filename        : k68_fetch.v
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// Description     : RISC Like Fetch Unit
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// Author          : Shawn Tan
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// Created On      : Fri Feb  7 16:17:17 2003
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// Last Modified By: .
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// Last Modified On: .
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// Update Count    : 0
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// Status          : Unknown, Use with caution!
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2002 to Shawn Tan Ser Ngiap.                  ////
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////                       shawn.tan@aeste.net                   ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`include "k68_defines.v"
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module k68_fetch (/*AUTOARG*/
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   // Outputs
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   p_cs_o, p_add_o, pc_o, op_o, imm_o,
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   // Inputs
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   p_dat_i, cpu_clk_i, mem_clk_i, rst_i, brch_i, pc_i
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   ) ;
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   parameter dw = `k68_DATA_W;
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   parameter aw = `k68_ADDR_W;
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   parameter nop = `k68_OP_NOP;
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   parameter ow = `k68_OP_W;
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   parameter zero = `ZERO;
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   parameter reset = `k68_RST_VECTOR;
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   input [ow-1:0] p_dat_i;
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   input            cpu_clk_i,mem_clk_i,rst_i, brch_i;
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   output           p_cs_o;//, rdy_o;
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   output [aw-1:0]  p_add_o, pc_o;
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   input [aw-1:0]   pc_i;
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   output [ow-1:0] op_o;
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   output [dw-1:0]   imm_o;
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   reg               rdy;
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   reg [ow-1:0]      op_o,immh_o,imml_o, tmpa,tmpb,tmpc,tmpd;
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   // Internal State Counters Assume it takes 4 counts to read data
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   reg [1:0]          mem_cnt, cpu_cnt;
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   reg [aw-1:0]      p_add_o,pc;
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   assign            pc_o = pc;
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   assign            imm_o = {immh_o, imml_o};
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   assign            p_cs_o = 1'b1;
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   //
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   // CPU SIDE
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   //
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   always @ (posedge cpu_clk_i) begin
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      if (rst_i) begin
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         /*AUTORESET*/
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         // Beginning of autoreset for uninitialized flops
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         cpu_cnt <= 0;
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         immh_o <= 0;
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         imml_o <= 0;
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         op_o <= 0;
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         p_add_o <= 0;
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         pc <= 0;
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         // End of automatics
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         p_add_o <= reset;
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         pc <= reset;
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         op_o <= nop;
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      end else begin
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         if (rdy) begin
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            case (cpu_cnt)
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              2'b00: begin
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                 op_o <= tmpa;
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                 immh_o <= tmpb;
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                 imml_o <= tmpc;
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              end
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              2'b01: begin
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                 op_o <= tmpb;
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                 immh_o <= tmpc;
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                 imml_o <= tmpd;
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              end
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              2'b10: begin
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                 op_o <= tmpc;
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                 immh_o <= tmpd;
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                 imml_o <= tmpa;
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              end
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              2'b11: begin
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                 op_o <= tmpd;
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                 immh_o <= tmpa;
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                 imml_o <= tmpb;
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              end
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            endcase // case(cnt[3:2])
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         end else begin // if (rdy)
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            op_o <= nop;
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            {immh_o, imml_o} <= zero;
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         end // else: !if(rdy)
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         if (brch_i) begin
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            pc <= pc_i;
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            cpu_cnt <= 2'd0;
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            p_add_o <= pc_i;
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         end else begin
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            if (rdy) begin
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               pc <= pc + 2'd2;
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            end
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            p_add_o <= p_add_o + 2'd2;
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            cpu_cnt <= cpu_cnt + 1'd1;
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         end // else: !if(brch_i)
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      end
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   end
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   //
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   //  RDY FLAG
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   //
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   always @ (/*AUTOSENSE*/brch_i or p_add_o or pc or rst_i) begin
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      if (rst_i || brch_i) begin
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         /*AUTORESET*/
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         // Beginning of autoreset for uninitialized flops
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         rdy <= 0;
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         // End of automatics
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      end else if (p_add_o[3:1] - pc[3:1] == 3'd3) begin
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         rdy <= 1'b1;
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      end else begin
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         rdy <= 1'b0;
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      end
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   end // always @ (...
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   wire [ow-1:0]     s_dat_i;
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`ifdef k68_SWAP
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   assign            s_dat_i = {p_dat_i[7:0],p_dat_i[15:8]};
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`else
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   assign            s_dat_i = p_dat_i;
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`endif
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   //
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   // PMEM SIDE
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   //
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   always @(posedge mem_clk_i) begin
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      if (rst_i) begin
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         /*AUTORESET*/
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         // Beginning of autoreset for uninitialized flops
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         mem_cnt <= 0;
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         tmpa <= 0;
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         tmpb <= 0;
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         tmpc <= 0;
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         tmpd <= 0;
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         // End of automatics
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         tmpa <= nop;
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         tmpb <= nop;
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         tmpc <= nop;
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         tmpd <= nop;
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      end else begin
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         if (mem_cnt == 2'b00) begin
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            case (cpu_cnt)
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              2'b00: tmpd <= s_dat_i;
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              2'b01: tmpa <= s_dat_i;
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              2'b10: tmpb <= s_dat_i;
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              2'b11: tmpc <= s_dat_i;
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            endcase // case(cpu_cnt)
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         end
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         if (brch_i) begin
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            tmpd <= nop;
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            tmpa <= nop;
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            tmpc <= nop;
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            tmpb <= nop;
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         end
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         mem_cnt <= mem_cnt + 1'd1;
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      end
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   end
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endmodule // k68_fetch
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