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//                              -*- Mode: Verilog -*-
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// Filename        : k68_soc.v
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// Description     : k68 SOC Top Level
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// Author          : Shawn Tan
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// Created On      : Sat Feb  8 20:58:34 2003
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// Last Modified By: .
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// Last Modified On: .
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// Update Count    : 0
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// Status          : Unknown, Use with caution!
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2002 to Shawn Tan Ser Ngiap.                  ////
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////                       shawn.tan@aeste.net                   ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`include "k68_defines.v"
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module k68_soc (/*AUTOARG*/
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   // Outputs
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   add_o, dat_o, we_o, tx_o, rts_o, clk_o, rst_o,
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   // Inputs
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   dat_i, rst_i, clk_i, rx_i, cts_i, int_i
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   ) ;
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   parameter aw = `k68_ADDR_W;
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   parameter dw = `k68_DATA_W;
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   output [aw-1:0] add_o;
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   input [dw-1:0]  dat_i;
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   output [dw-1:0] dat_o;
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   output          we_o;
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   input           rst_i, clk_i;
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   input [1:0]      rx_i,cts_i;
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   output [1:0]    tx_o,rts_o;
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   input [2:0]      int_i;
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   output          clk_o;
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   output          rst_o;
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   wire            cs;
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   wire [aw-1:0]   m_add_o;
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   wire [dw-1:0]   m_dat_o;
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   wire [dw-1:0]   m_dat_i;
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   wire            m_we_o;
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   wire            m_cs_o;
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   wire [9:0]       a_dat_i, b_dat_i;
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   wire            r_cs_o, r_we_o, a_cs_o, b_cs_o, a_we_o, b_we_o;
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   wire            rst;
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   wire [31:0]      d_dat_o,d_dat_i;
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   assign          add_o = m_add_o;
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   assign          dat_o = m_dat_o;
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   assign          we_o = r_we_o;
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   //
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   // Arbiter
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   //
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   k68_arb arb0 (
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                 .m_we_o(r_we_o),
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                 .m_cs_o(r_cs_o),
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                 .m_dat_i(dat_i),
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                 .a_we_o(a_we_o),
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                 .a_cs_o(a_cs_o),
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                 .a_dat_i(a_dat_i),
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                 .b_we_o(b_we_o),
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                 .b_cs_o(b_cs_o),
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                 .b_dat_i(b_dat_i),
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                 .m_add_i(m_add_o),
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                 .m_we_i(m_we_o),
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                 .m_dat_o(m_dat_i),
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                 .rst_i(rst_o)
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                 );
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   //
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   // Instantiate CPU
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   //
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   k68_cpu cpu0(
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                .add_o(m_add_o),
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                .dat_o(m_dat_o),
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                .dat_i(m_dat_i),
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                .we_o(m_we_o),
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                .int_i(int_i),
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                .cs_o(cs),
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                .clk_o(clk_o), .rst_o(rst_o),
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                .clk_i(clk_i), .rst_i(rst_i)
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                );
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`ifdef k68_UART
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   //
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   // k68_sasc
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   //
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   wire [7:0]       brg0,brg1;
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   assign          brg0 = `k68_div0;
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   assign          brg1 = `k68_div1;
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   k68_sasc uart0(
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                  .tx_o(tx_o[0]),
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                  .rts_o(rts_o[0]),
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                  .dat_i({brg1,brg0,m_dat_o[7:0]}),
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                  .dat_o(a_dat_i),
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                  .cts_i(cts_i[0]),
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                  .rx_i(rx_i[0]),
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                  .cs_i(a_cs_o),
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                  .we_i(a_we_o),
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                  .clk_i(clk_o),.rst_i(rst_o)
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                  );
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   k68_sasc uart1(
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                  .tx_o(tx_o[1]),
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                  .rts_o(rts_o[1]),
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                  .dat_i({brg1,brg0,m_dat_o[7:0]}),
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                  .dat_o(b_dat_i),
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                  .cts_i(cts_i[1]),
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                  .rx_i(rx_i[1]),
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                  .cs_i(b_cs_o),
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                  .we_i(b_we_o),
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                  .clk_i(clk_o),.rst_i(rst_o)
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                  );
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`endif
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endmodule // k68_soc
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/*
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 *
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 * Synchronous Bus Arbiter
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 * Consider placing 0xFF000000 - 0xFFFFFFFF to Peripheral space
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 *
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 * 0xFF000000 - GPIO
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 * 0xFF010000 - UARTA
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 * 0xFF020000 - UARTB
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 * 0xFF030000 - DES
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 *
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 * Others Reserved
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 *
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 */
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module k68_arb (/*AUTOARG*/
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   // Outputs
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   m_dat_o, m_we_o, m_cs_o, g_we_o, g_cs_o, a_we_o, a_cs_o, b_we_o,
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   b_cs_o,
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   // Inputs
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   rst_i, m_add_i, m_we_i, m_dat_i, g_dat_i, a_dat_i, b_dat_i
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   ) ;
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   parameter aw = `k68_ADDR_W;
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   parameter dw = `k68_DATA_W;
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   parameter ow = `k68_OP_W;
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   // Program Memory
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   //input [dw-1:0]  p_dat_i;
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   input     rst_i;
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   // Data Memory
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   output [dw-1:0] m_dat_o;
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   input [aw-1:0]  m_add_i;
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   input           m_we_i;
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   reg [dw-1:0]    m_dat_o;
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   // SPRAM
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   input [dw-1:0]  m_dat_i;
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   output          m_we_o;
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   output          m_cs_o;
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   reg             m_we_o, m_cs_o;
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   //
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   // Peripherals
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   //
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   // GPIO PORTS
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   input [15:0]    g_dat_i;
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   output          g_we_o, g_cs_o;
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   reg             g_we_o, g_cs_o;
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   // UART A
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   input [9:0]      a_dat_i;
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   output          a_we_o, a_cs_o;
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   reg             a_we_o, a_cs_o;
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   // UART B
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   input [9:0]      b_dat_i;
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   output          b_we_o, b_cs_o;
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   reg             b_we_o, b_cs_o;
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   always @ ( /*AUTOSENSE*/a_dat_i or b_dat_i or g_dat_i or m_add_i
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             or m_dat_i or m_we_i or rst_i) begin
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    if (rst_i) begin
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      /*AUTORESET*/
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      // Beginning of autoreset for uninitialized flops
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      a_cs_o <= 0;
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      a_we_o <= 0;
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      b_cs_o <= 0;
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      b_we_o <= 0;
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      g_cs_o <= 0;
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      g_we_o <= 0;
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      m_cs_o <= 0;
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      m_dat_o <= 0;
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      m_we_o <= 0;
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      // End of automatics
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    end else begin // if (rst_i)
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       /*AUTORESET*/
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       // Beginning of autoreset for uninitialized flops
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       a_cs_o <= 0;
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       a_we_o <= 0;
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       b_cs_o <= 0;
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       b_we_o <= 0;
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       g_cs_o <= 0;
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       g_we_o <= 0;
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       m_cs_o <= 0;
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       m_dat_o <= 0;
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       m_we_o <= 0;
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       // End of automatics
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      case (m_add_i[aw-1])
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        1'b1:
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          case (m_add_i[31:24])
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            8'hFF:
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              case (m_add_i[23:16])
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                8'h00: begin // GPIO
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                   g_cs_o <= 1'b1;
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                   g_we_o <= m_we_i;
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                   m_dat_o <= g_dat_i;
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                end
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`ifdef k68_UART
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                8'h01: begin // UART A
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                   a_cs_o <= 1'b1;
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                   a_we_o <= m_we_i;
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                   m_dat_o <= a_dat_i;
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                end
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                8'h02: begin // UART B
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                   b_cs_o <= 1'b1;
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                   b_we_o <= m_we_i;
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                   m_dat_o <= b_dat_i;
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                end
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`endif
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                default: begin
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                   /*AUTORESET*/
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                   // Beginning of autoreset for uninitialized flops
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                   a_cs_o <= 0;
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                   a_we_o <= 0;
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                   b_cs_o <= 0;
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                   b_we_o <= 0;
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                   g_cs_o <= 0;
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                   g_we_o <= 0;
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                   m_cs_o <= 0;
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                   m_dat_o <= 0;
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                   m_we_o <= 0;
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                   // End of automatics
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                end
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              endcase // case(m_add_i)
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            default: begin
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               m_we_o <= m_we_i;
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               m_cs_o <= 1'b1;
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               m_dat_o <= m_dat_i;
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            end
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          endcase // case(m_add_i[31:24])
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        default:
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          case (m_add_i[1])
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            1'b1: begin
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               m_dat_o <= {m_dat_i[31:16], m_dat_i[31:16]};
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               m_we_o <= 1'b0;
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               m_cs_o <= 1'b0;
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               a_cs_o <= 1'b0;
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               b_cs_o <= 1'b0;
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               g_cs_o <= 1'b0;
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            end
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            default: begin
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               m_dat_o <= {m_dat_i[15:0], m_dat_i[15:0]};
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               m_we_o <= 1'b0;
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               m_cs_o <= 1'b0;
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               a_cs_o <= 1'b0;
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               b_cs_o <= 1'b0;
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               g_cs_o <= 1'b0;
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            end
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          endcase // case(m_add_i[1])
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      endcase // case(m_add_i[31])
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    end
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   end
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endmodule // k68_arb
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