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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE DMA Priority Encoder ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: wb_dma_ch_pri_enc.v,v 1.1.1.1 2006-05-29 13:45:12 fukuchi Exp $
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//
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// $Date: 2006-05-29 13:45:12 $
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// $Revision: 1.1.1.1 $
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// $Author: fukuchi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/02/01 01:54:44 rudi
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//
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// - Minor cleanup
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//
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// Revision 1.4 2001/10/19 04:35:04 rudi
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//
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// - Made the core parameterized
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//
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// Revision 1.3 2001/08/15 05:40:30 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Added Section 3.10, describing DMA restart.
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//
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// Revision 1.2 2001/08/07 08:00:43 rudi
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//
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//
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// Split up priority encoder modules to separate files
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//
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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//
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// Revision 1.2 2001/06/05 10:22:36 rudi
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//
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//
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// - Added Support of up to 31 channels
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// - Added support for 2,4 and 8 priority levels
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// - Now can have up to 31 channels
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// - Added many configuration items
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// - Changed reset to async
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//
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// Revision 1.1.1.1 2001/03/19 13:10:50 rudi
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// Initial Release
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//
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//
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//
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`include "wb_dma_defines.v"
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// Priority Encoder
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//
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// Determines the channel with the highest priority, also takes
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// the valid bit in consideration
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module wb_dma_ch_pri_enc(clk, valid,
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pri0, pri1, pri2, pri3,
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pri4, pri5, pri6, pri7,
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pri8, pri9, pri10, pri11,
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pri12, pri13, pri14, pri15,
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pri16, pri17, pri18, pri19,
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pri20, pri21, pri22, pri23,
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pri24, pri25, pri26, pri27,
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pri28, pri29, pri30,
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pri_out);
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////////////////////////////////////////////////////////////////////
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//
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// Module Parameters
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//
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// chXX_conf = { CBUF, ED, ARS, EN }
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parameter [1:0] pri_sel = 2'd0;
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parameter [3:0] ch0_conf = 4'h1;
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parameter [3:0] ch1_conf = 4'h0;
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parameter [3:0] ch2_conf = 4'h0;
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parameter [3:0] ch3_conf = 4'h0;
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parameter [3:0] ch4_conf = 4'h0;
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parameter [3:0] ch5_conf = 4'h0;
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parameter [3:0] ch6_conf = 4'h0;
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parameter [3:0] ch7_conf = 4'h0;
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parameter [3:0] ch8_conf = 4'h0;
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parameter [3:0] ch9_conf = 4'h0;
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parameter [3:0] ch10_conf = 4'h0;
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parameter [3:0] ch11_conf = 4'h0;
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parameter [3:0] ch12_conf = 4'h0;
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parameter [3:0] ch13_conf = 4'h0;
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parameter [3:0] ch14_conf = 4'h0;
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parameter [3:0] ch15_conf = 4'h0;
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parameter [3:0] ch16_conf = 4'h0;
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parameter [3:0] ch17_conf = 4'h0;
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parameter [3:0] ch18_conf = 4'h0;
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parameter [3:0] ch19_conf = 4'h0;
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parameter [3:0] ch20_conf = 4'h0;
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parameter [3:0] ch21_conf = 4'h0;
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parameter [3:0] ch22_conf = 4'h0;
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parameter [3:0] ch23_conf = 4'h0;
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parameter [3:0] ch24_conf = 4'h0;
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parameter [3:0] ch25_conf = 4'h0;
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parameter [3:0] ch26_conf = 4'h0;
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parameter [3:0] ch27_conf = 4'h0;
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parameter [3:0] ch28_conf = 4'h0;
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parameter [3:0] ch29_conf = 4'h0;
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parameter [3:0] ch30_conf = 4'h0;
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////////////////////////////////////////////////////////////////////
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//
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// Module IOs
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//
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input clk;
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input [30:0] valid; // Channel Valid bits
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input [2:0] pri0, pri1, pri2, pri3; // Channel Priorities
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input [2:0] pri4, pri5, pri6, pri7;
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input [2:0] pri8, pri9, pri10, pri11;
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input [2:0] pri12, pri13, pri14, pri15;
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input [2:0] pri16, pri17, pri18, pri19;
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input [2:0] pri20, pri21, pri22, pri23;
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input [2:0] pri24, pri25, pri26, pri27;
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input [2:0] pri28, pri29, pri30;
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output [2:0] pri_out; // Highest unserviced priority
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wire [7:0] pri0_out, pri1_out, pri2_out, pri3_out;
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wire [7:0] pri4_out, pri5_out, pri6_out, pri7_out;
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wire [7:0] pri8_out, pri9_out, pri10_out, pri11_out;
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wire [7:0] pri12_out, pri13_out, pri14_out, pri15_out;
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wire [7:0] pri16_out, pri17_out, pri18_out, pri19_out;
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wire [7:0] pri20_out, pri21_out, pri22_out, pri23_out;
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wire [7:0] pri24_out, pri25_out, pri26_out, pri27_out;
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wire [7:0] pri28_out, pri29_out, pri30_out;
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wire [7:0] pri_out_tmp;
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reg [2:0] pri_out;
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reg [2:0] pri_out2;
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reg [2:0] pri_out1;
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reg [2:0] pri_out0;
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wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u0( // Use channel config 1 for channel 0 encoder
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.valid( valid[0] ),
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.pri_in( pri0 ),
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.pri_out( pri0_out )
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);
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wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u1(
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.valid( valid[1] ),
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.pri_in( pri1 ),
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.pri_out( pri1_out )
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);
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wb_dma_pri_enc_sub #(ch2_conf,pri_sel) u2(
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.valid( valid[2] ),
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.pri_in( pri2 ),
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.pri_out( pri2_out )
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);
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wb_dma_pri_enc_sub #(ch3_conf,pri_sel) u3(
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.valid( valid[3] ),
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.pri_in( pri3 ),
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.pri_out( pri3_out )
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);
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wb_dma_pri_enc_sub #(ch4_conf,pri_sel) u4(
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.valid( valid[4] ),
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.pri_in( pri4 ),
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.pri_out( pri4_out )
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);
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wb_dma_pri_enc_sub #(ch5_conf,pri_sel) u5(
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.valid( valid[5] ),
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.pri_in( pri5 ),
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.pri_out( pri5_out )
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);
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wb_dma_pri_enc_sub #(ch6_conf,pri_sel) u6(
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.valid( valid[6] ),
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.pri_in( pri6 ),
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.pri_out( pri6_out )
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);
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wb_dma_pri_enc_sub #(ch7_conf,pri_sel) u7(
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.valid( valid[7] ),
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.pri_in( pri7 ),
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.pri_out( pri7_out )
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);
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wb_dma_pri_enc_sub #(ch8_conf,pri_sel) u8(
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.valid( valid[8] ),
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.pri_in( pri8 ),
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.pri_out( pri8_out )
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);
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wb_dma_pri_enc_sub #(ch9_conf,pri_sel) u9(
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.valid( valid[9] ),
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.pri_in( pri9 ),
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.pri_out( pri9_out )
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);
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wb_dma_pri_enc_sub #(ch10_conf,pri_sel) u10(
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.valid( valid[10] ),
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.pri_in( pri10 ),
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.pri_out( pri10_out )
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);
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wb_dma_pri_enc_sub #(ch11_conf,pri_sel) u11(
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.valid( valid[11] ),
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.pri_in( pri11 ),
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.pri_out( pri11_out )
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);
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wb_dma_pri_enc_sub #(ch12_conf,pri_sel) u12(
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.valid( valid[12] ),
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.pri_in( pri12 ),
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.pri_out( pri12_out )
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);
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wb_dma_pri_enc_sub #(ch13_conf,pri_sel) u13(
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.valid( valid[13] ),
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.pri_in( pri13 ),
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.pri_out( pri13_out )
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);
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wb_dma_pri_enc_sub #(ch14_conf,pri_sel) u14(
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.valid( valid[14] ),
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.pri_in( pri14 ),
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.pri_out( pri14_out )
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);
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wb_dma_pri_enc_sub #(ch15_conf,pri_sel) u15(
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.valid( valid[15] ),
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.pri_in( pri15 ),
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.pri_out( pri15_out )
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);
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wb_dma_pri_enc_sub #(ch16_conf,pri_sel) u16(
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.valid( valid[16] ),
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.pri_in( pri16 ),
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.pri_out( pri16_out )
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);
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wb_dma_pri_enc_sub #(ch17_conf,pri_sel) u17(
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.valid( valid[17] ),
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.pri_in( pri17 ),
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.pri_out( pri17_out )
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);
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wb_dma_pri_enc_sub #(ch18_conf,pri_sel) u18(
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.valid( valid[18] ),
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.pri_in( pri18 ),
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.pri_out( pri18_out )
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);
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wb_dma_pri_enc_sub #(ch19_conf,pri_sel) u19(
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.valid( valid[19] ),
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.pri_in( pri19 ),
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.pri_out( pri19_out )
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);
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wb_dma_pri_enc_sub #(ch20_conf,pri_sel) u20(
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.valid( valid[20] ),
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.pri_in( pri20 ),
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.pri_out( pri20_out )
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);
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wb_dma_pri_enc_sub #(ch21_conf,pri_sel) u21(
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.valid( valid[21] ),
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.pri_in( pri21 ),
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.pri_out( pri21_out )
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);
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wb_dma_pri_enc_sub #(ch22_conf,pri_sel) u22(
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.valid( valid[22] ),
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.pri_in( pri22 ),
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.pri_out( pri22_out )
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);
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wb_dma_pri_enc_sub #(ch23_conf,pri_sel) u23(
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.valid( valid[23] ),
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.pri_in( pri23 ),
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.pri_out( pri23_out )
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);
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wb_dma_pri_enc_sub #(ch24_conf,pri_sel) u24(
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.valid( valid[24] ),
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.pri_in( pri24 ),
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.pri_out( pri24_out )
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);
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wb_dma_pri_enc_sub #(ch25_conf,pri_sel) u25(
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.valid( valid[25] ),
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.pri_in( pri25 ),
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.pri_out( pri25_out )
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);
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wb_dma_pri_enc_sub #(ch26_conf,pri_sel) u26(
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.valid( valid[26] ),
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.pri_in( pri26 ),
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| 313 |
|
|
.pri_out( pri26_out )
|
| 314 |
|
|
);
|
| 315 |
|
|
wb_dma_pri_enc_sub #(ch27_conf,pri_sel) u27(
|
| 316 |
|
|
.valid( valid[27] ),
|
| 317 |
|
|
.pri_in( pri27 ),
|
| 318 |
|
|
.pri_out( pri27_out )
|
| 319 |
|
|
);
|
| 320 |
|
|
wb_dma_pri_enc_sub #(ch28_conf,pri_sel) u28(
|
| 321 |
|
|
.valid( valid[28] ),
|
| 322 |
|
|
.pri_in( pri28 ),
|
| 323 |
|
|
.pri_out( pri28_out )
|
| 324 |
|
|
);
|
| 325 |
|
|
wb_dma_pri_enc_sub #(ch29_conf,pri_sel) u29(
|
| 326 |
|
|
.valid( valid[29] ),
|
| 327 |
|
|
.pri_in( pri29 ),
|
| 328 |
|
|
.pri_out( pri29_out )
|
| 329 |
|
|
);
|
| 330 |
|
|
wb_dma_pri_enc_sub #(ch30_conf,pri_sel) u30(
|
| 331 |
|
|
.valid( valid[30] ),
|
| 332 |
|
|
.pri_in( pri30 ),
|
| 333 |
|
|
.pri_out( pri30_out )
|
| 334 |
|
|
);
|
| 335 |
|
|
|
| 336 |
|
|
assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out |
|
| 337 |
|
|
pri4_out | pri5_out | pri6_out | pri7_out |
|
| 338 |
|
|
pri8_out | pri9_out | pri10_out | pri11_out |
|
| 339 |
|
|
pri12_out | pri13_out | pri14_out | pri15_out |
|
| 340 |
|
|
pri16_out | pri17_out | pri18_out | pri19_out |
|
| 341 |
|
|
pri20_out | pri21_out | pri22_out | pri23_out |
|
| 342 |
|
|
pri24_out | pri25_out | pri26_out | pri27_out |
|
| 343 |
|
|
pri28_out | pri29_out | pri30_out;
|
| 344 |
|
|
|
| 345 |
|
|
// 8 Priority Levels
|
| 346 |
|
|
always @(posedge clk)
|
| 347 |
|
|
if(pri_out_tmp[7]) pri_out2 <= #1 3'h7;
|
| 348 |
|
|
else
|
| 349 |
|
|
if(pri_out_tmp[6]) pri_out2 <= #1 3'h6;
|
| 350 |
|
|
else
|
| 351 |
|
|
if(pri_out_tmp[5]) pri_out2 <= #1 3'h5;
|
| 352 |
|
|
else
|
| 353 |
|
|
if(pri_out_tmp[4]) pri_out2 <= #1 3'h4;
|
| 354 |
|
|
else
|
| 355 |
|
|
if(pri_out_tmp[3]) pri_out2 <= #1 3'h3;
|
| 356 |
|
|
else
|
| 357 |
|
|
if(pri_out_tmp[2]) pri_out2 <= #1 3'h2;
|
| 358 |
|
|
else
|
| 359 |
|
|
if(pri_out_tmp[1]) pri_out2 <= #1 3'h1;
|
| 360 |
|
|
else pri_out2 <= #1 3'h0;
|
| 361 |
|
|
|
| 362 |
|
|
// 4 Priority Levels
|
| 363 |
|
|
always @(posedge clk)
|
| 364 |
|
|
if(pri_out_tmp[3]) pri_out1 <= #1 3'h3;
|
| 365 |
|
|
else
|
| 366 |
|
|
if(pri_out_tmp[2]) pri_out1 <= #1 3'h2;
|
| 367 |
|
|
else
|
| 368 |
|
|
if(pri_out_tmp[1]) pri_out1 <= #1 3'h1;
|
| 369 |
|
|
else pri_out1 <= #1 3'h0;
|
| 370 |
|
|
|
| 371 |
|
|
// 2 Priority Levels
|
| 372 |
|
|
always @(posedge clk)
|
| 373 |
|
|
if(pri_out_tmp[1]) pri_out0 <= #1 3'h1;
|
| 374 |
|
|
else pri_out0 <= #1 3'h0;
|
| 375 |
|
|
|
| 376 |
|
|
// Select configured priority
|
| 377 |
|
|
always @(pri_sel or pri_out0 or pri_out1 or pri_out2)
|
| 378 |
|
|
case(pri_sel) // synopsys parallel_case full_case
|
| 379 |
|
|
2'd0: pri_out = pri_out0;
|
| 380 |
|
|
2'd1: pri_out = pri_out1;
|
| 381 |
|
|
2'd2: pri_out = pri_out2;
|
| 382 |
|
|
endcase
|
| 383 |
|
|
|
| 384 |
|
|
endmodule
|
