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[/] [kiss-board/] [tags/] [initial/] [kiss-board_soc/] [src/] [extend/] [wb_dma/] [wb_dma_ch_rf.v] - Blame information for rev 11

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE DMA One Channel Register File                     ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_dma_ch_rf.v,v 1.1.1.1 2006-05-29 13:45:13 fukuchi Exp $
//
//  $Date: 2006-05-29 13:45:13 $
//  $Revision: 1.1.1.1 $
//  $Author: fukuchi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.5  2002/02/01 01:54:45  rudi
//
//               - Minor cleanup
//
//               Revision 1.4  2001/10/30 02:06:17  rudi
//
//               - Fixed problem where synthesis tools would instantiate latches instead of flip-flops
//
//               Revision 1.3  2001/10/19 04:35:04  rudi
//
//               - Made the core parameterized
//
//               Revision 1.2  2001/08/15 05:40:30  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Added Section 3.10, describing DMA restart.
//
//               Revision 1.1  2001/07/29 08:57:02  rudi
//
//
//               1) Changed Directory Structure
//               2) Added restart signal (REST)
//
//               Revision 1.3  2001/06/14 08:50:01  rudi
//
//               Changed Module Name to match file name.
//
//               Revision 1.2  2001/06/13 02:26:48  rudi
//
//
//               Small changes after running lint.
//
//               Revision 1.1  2001/06/05 10:25:27  rudi
//
//
//               Initial checkin of register file for one channel.
//
//
//
//
 
`include "wb_dma_defines.v"
 
module wb_dma_ch_rf(    clk, rst,
                        pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,
                        ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,
 
                        wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,
 
                        // DMA Registers Write Back Channel Select
                        ch_sel, ndnr,
 
                        // DMA Engine Status
                        dma_busy, dma_err, dma_done, dma_done_all,
 
                        // DMA Engine Reg File Update ctrl signals
                        de_csr, de_txsz, de_adr0, de_adr1,
                        de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,
                        de_fetch_descr, dma_rest,
                        ptr_set
 
                );
 
parameter       [4:0]    CH_NO    = 5'h0;  // This Instances Channel ID
parameter       [0:0]     CH_EN    = 1'b1;  // This channel exists
parameter       [0:0]     HAVE_ARS = 1'b1;  // 1=this Instance Supports ARS
parameter       [0:0]     HAVE_ED  = 1'b1;  // 1=this Instance Supports External Descriptors
parameter       [0:0]     HAVE_CBUF= 1'b1;  // 1=this Instance Supports Cyclic Buffers
 
input           clk, rst;
 
output  [31:0]   pointer;
output  [31:0]   pointer_s;
output  [31:0]   ch_csr;
output  [31:0]   ch_txsz;
output  [31:0]   ch_adr0;
output  [31:0]   ch_adr1;
output  [31:0]   ch_am0;
output  [31:0]   ch_am1;
output  [31:0]   sw_pointer;
output          ch_stop;
output          ch_dis;
output          int;
 
input   [31:0]   wb_rf_din;
input   [7:0]    wb_rf_adr;
input           wb_rf_we;
input           wb_rf_re;
 
input   [4:0]    ch_sel;
input           ndnr;
 
// DMA Engine Status
input           dma_busy, dma_err, dma_done, dma_done_all;
 
// DMA Engine Reg File Update ctrl signals
input   [31:0]   de_csr;
input   [11:0]   de_txsz;
input   [31:0]   de_adr0;
input   [31:0]   de_adr1;
input           de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
input           de_fetch_descr;
input           dma_rest;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
 
wire    [31:0]   pointer;
reg     [27:0]   pointer_r;
reg     [27:0]   pointer_sr;
reg             ptr_valid;
reg             ch_eol;
 
wire    [31:0]   ch_csr, ch_txsz;
 
reg     [8:0]    ch_csr_r;
reg     [2:0]    ch_csr_r2;
reg     [2:0]    ch_csr_r3;
reg     [2:0]    int_src_r;
reg             ch_err_r;
reg             ch_stop;
reg             ch_busy;
reg             ch_done;
reg             ch_err;
reg             rest_en;
 
reg     [10:0]   ch_chk_sz_r;
reg     [11:0]   ch_tot_sz_r;
reg     [22:0]   ch_txsz_s;
reg             ch_sz_inf;
 
wire    [31:0]   ch_adr0, ch_adr1;
reg     [29:0]   ch_adr0_r, ch_adr1_r;
wire    [31:0]   ch_am0, ch_am1;
reg     [27:0]   ch_am0_r, ch_am1_r;
 
reg     [29:0]   ch_adr0_s, ch_adr1_s;
 
reg     [29:0]   sw_pointer_r;
wire            sw_pointer_we;
wire    [28:0]   cmp_adr;
reg             ch_dis;
wire            ch_enable;
 
wire            pointer_we;
wire            ch_csr_we, ch_csr_re, ch_txsz_we, ch_adr0_we, ch_adr1_we;
wire            ch_am0_we, ch_am1_we;
reg             ch_rl;
wire            ch_done_we;
wire            ch_err_we;
wire            chunk_done_we;
 
wire            ch_csr_dewe, ch_txsz_dewe, ch_adr0_dewe, ch_adr1_dewe;
 
wire            this_ptr_set;
wire            ptr_inv;
 
////////////////////////////////////////////////////////////////////
//
// Aliases
//
 
assign ch_adr0          = CH_EN ? {ch_adr0_r, 2'h0}   : 32'h0;
assign ch_adr1          = CH_EN ? {ch_adr1_r, 2'h0}   : 32'h0;
assign ch_am0           = (CH_EN & HAVE_CBUF) ? {ch_am0_r, 4'h0}    : 32'hffff_fff0;
assign ch_am1           = (CH_EN & HAVE_CBUF) ? {ch_am1_r, 4'h0}    : 32'hffff_fff0;
assign sw_pointer       = (CH_EN & HAVE_CBUF) ? {sw_pointer_r,2'h0} : 32'h0;
 
assign pointer          = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0;
assign pointer_s        = CH_EN ? {pointer_sr, 4'h0}  : 32'h0;
assign ch_csr           = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
                                        ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0;
assign ch_txsz          = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0;
 
assign ch_enable        = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0;
 
////////////////////////////////////////////////////////////////////
//
// CH0 control signals
//
 
parameter       [4:0]    CH_ADR = CH_NO + 5'h1;
 
assign ch_csr_we        = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
assign ch_csr_re        = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
assign ch_txsz_we       = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1);
assign ch_adr0_we       = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2);
assign ch_am0_we        = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3);
assign ch_adr1_we       = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4);
assign ch_am1_we        = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);
assign pointer_we       = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);
assign sw_pointer_we    = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);
 
assign ch_done_we       = CH_EN & (((ch_sel==CH_NO) & dma_done_all) | ndnr) &
                          (ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
assign chunk_done_we    = CH_EN & (ch_sel==CH_NO) & dma_done;
assign ch_err_we        = CH_EN & (ch_sel==CH_NO) & dma_err;
assign ch_csr_dewe      = CH_EN & de_csr_we & (ch_sel==CH_NO);
assign ch_txsz_dewe     = CH_EN & de_txsz_we & (ch_sel==CH_NO);
assign ch_adr0_dewe     = CH_EN & de_adr0_we & (ch_sel==CH_NO);
assign ch_adr1_dewe     = CH_EN & de_adr1_we & (ch_sel==CH_NO);
 
assign ptr_inv          = CH_EN & ((ch_sel==CH_NO) & dma_done_all) | ndnr;
assign this_ptr_set     = CH_EN & ptr_set & (ch_sel==CH_NO);
 
always @(posedge clk)
        ch_rl <= #1     CH_EN & HAVE_ARS & (
                        (rest_en & dma_rest) |
                        ((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
                        );
 
// ---------------------------------------------------
// Pointers
 
always @(posedge clk or negedge rst)
        if(!rst)                        ptr_valid <= #1 1'b0;
        else
        if(CH_EN & HAVE_ED)
           begin
                if( this_ptr_set | (rest_en & dma_rest) )
                                        ptr_valid <= #1 1'b1;
                else
                if(ptr_inv)             ptr_valid <= #1 1'b0;
           end
        else                            ptr_valid <= #1 1'b0;
 
always @(posedge clk or negedge rst)
        if(!rst)                        ch_eol <= #1 1'b0;
        else
        if(CH_EN & HAVE_ED)
           begin
                if(ch_csr_dewe)         ch_eol <= #1 de_csr[`WDMA_ED_EOL];
                else
                if(ch_done_we)          ch_eol <= #1 1'b0;
           end
        else                            ch_eol <= #1 1'b0;
 
always @(posedge clk)
        if(CH_EN & HAVE_ED)
           begin
                if(pointer_we)          pointer_r <= #1 wb_rf_din[31:4];
                else
                if(this_ptr_set)        pointer_r <= #1 de_csr[31:4];
           end
        else                            pointer_r <= #1 1'b0;
 
always @(posedge clk)
        if(CH_EN & HAVE_ED)
           begin
                if(this_ptr_set)        pointer_sr <= #1 pointer_r;
           end
        else                            pointer_sr <= #1 1'b0;
 
// ---------------------------------------------------
// CSR
 
always @(posedge clk or negedge rst)
        if(!rst)                        ch_csr_r <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(ch_csr_we)           ch_csr_r <= #1 wb_rf_din[8:0];
                else
                   begin
                        if(ch_done_we)  ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
                        if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];
                   end
           end
 
// done bit
always @(posedge clk or negedge rst)
        if(!rst)                ch_done <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(ch_csr_we)           ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
                else
                if(ch_done_we)          ch_done <= #1 1'b1;
           end
 
// busy bit
always @(posedge clk)
        ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy;
 
// stop bit
always @(posedge clk)
        ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP];
 
// error bit
always @(posedge clk or negedge rst)
        if(!rst)                        ch_err <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(ch_err_we)           ch_err <= #1 1'b1;
                else
                if(ch_csr_re)           ch_err <= #1 1'b0;
           end
 
// Priority Bits
always @(posedge clk or negedge rst)
        if(!rst)                        ch_csr_r2 <= #1 3'h0;
        else
        if(CH_EN & ch_csr_we)           ch_csr_r2 <= #1 wb_rf_din[15:13];
 
// Restart Enable Bit (REST)
always @(posedge clk or negedge rst)
        if(!rst)                        rest_en <= #1 1'b0;
        else
        if(CH_EN & ch_csr_we)           rest_en <= #1 wb_rf_din[16];
 
// INT Mask
always @(posedge clk or negedge rst)
        if(!rst)                        ch_csr_r3 <= #1 3'h0;
        else
        if(CH_EN & ch_csr_we)           ch_csr_r3 <= #1 wb_rf_din[19:17];
 
// INT Source
always @(posedge clk or negedge rst)
        if(!rst)                        int_src_r[2] <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(chunk_done_we)       int_src_r[2] <= #1 1'b1;
                else
                if(ch_csr_re)           int_src_r[2] <= #1 1'b0;
           end
 
always @(posedge clk or negedge rst)
        if(!rst)                        int_src_r[1] <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(ch_done_we)          int_src_r[1] <= #1 1'b1;
                else
                if(ch_csr_re)           int_src_r[1] <= #1 1'b0;
           end
 
always @(posedge clk or negedge rst)
        if(!rst)                        int_src_r[0] <= #1 1'b0;
        else
        if(CH_EN)
           begin
                if(ch_err_we)           int_src_r[0] <= #1 1'b1;
                else
                if(ch_csr_re)           int_src_r[0] <= #1 1'b0;
           end
 
// Interrupt Output
assign int = |(int_src_r & ch_csr_r3) & CH_EN;
 
// ---------------------------------------------------
// TXZS
always @(posedge clk)
        if(CH_EN)
           begin
                if(ch_txsz_we)
                        {ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
                else
                if(ch_txsz_dewe)
                        ch_tot_sz_r <= #1 de_txsz;
                else
                if(ch_rl)
                        {ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;
           end
 
// txsz shadow register
always @(posedge clk)
        if(CH_EN & HAVE_ARS)
           begin
 
                if(ch_txsz_we)  ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
                else
                if(rest_en & ch_txsz_dewe & de_fetch_descr)
                                ch_txsz_s[11:0] <= #1 de_txsz[11:0];
           end
 
// Infinite Size indicator
always @(posedge clk)
        if(CH_EN)
           begin
                if(ch_txsz_we)          ch_sz_inf <= #1 wb_rf_din[15];
           end
 
// ---------------------------------------------------
// ADR0
always @(posedge clk)
        if(CH_EN)
           begin
                if(ch_adr0_we)          ch_adr0_r <= #1 wb_rf_din[31:2];
                else
                if(ch_adr0_dewe)        ch_adr0_r <= #1 de_adr0[31:2];
                else
                if(ch_rl)               ch_adr0_r <= #1 ch_adr0_s;
           end
 
// Adr0 shadow register
always @(posedge clk)
        if(CH_EN & HAVE_ARS)
           begin
                if(ch_adr0_we)  ch_adr0_s <= #1 wb_rf_din[31:2];
                else
                if(rest_en & ch_adr0_dewe & de_fetch_descr)
                                ch_adr0_s <= #1 de_adr0[31:2];
           end
 
// ---------------------------------------------------
// AM0
always @(posedge clk or negedge rst)
        if(!rst)                ch_am0_r <= #1 28'hfffffff;
        else
        if(ch_am0_we)           ch_am0_r <= #1 wb_rf_din[31:4];
 
// ---------------------------------------------------
// ADR1
always @(posedge clk)
        if(CH_EN)
           begin
                if(ch_adr1_we)          ch_adr1_r <= #1 wb_rf_din[31:2];
                else
                if(ch_adr1_dewe)        ch_adr1_r <= #1 de_adr1[31:2];
                else
                if(ch_rl)               ch_adr1_r <= #1 ch_adr1_s;
           end
 
// Adr1 shadow register
always @(posedge clk)
        if(CH_EN & HAVE_ARS)
           begin
                if(ch_adr1_we)  ch_adr1_s <= #1 wb_rf_din[31:2];
                else
                if(rest_en & ch_adr1_dewe & de_fetch_descr)
                                ch_adr1_s <= #1 de_adr1[31:2];
           end
 
// ---------------------------------------------------
// AM1
always @(posedge clk or negedge rst)
        if(!rst)                                ch_am1_r <= #1 28'hfffffff;
        else
        if(ch_am1_we & CH_EN & HAVE_CBUF)       ch_am1_r <= #1 wb_rf_din[31:4];
 
// ---------------------------------------------------
// Software Pointer
always @(posedge clk or negedge rst)
        if(!rst)                                sw_pointer_r <= #1 28'h0;
        else
        if(sw_pointer_we & CH_EN & HAVE_CBUF)   sw_pointer_r <= #1 wb_rf_din[31:4];
 
// ---------------------------------------------------
// Software Pointer Match logic
 
assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];
 
always @(posedge clk)
        ch_dis <= #1 CH_EN & HAVE_CBUF & (sw_pointer[30:2] == cmp_adr) & sw_pointer[31];
 
endmodule
 
 
module wb_dma_ch_rf_dummy(clk, rst,
                        pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,
                        ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,
 
                        wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,
 
                        // DMA Registers Write Back Channel Select
                        ch_sel, ndnr,
 
                        // DMA Engine Status
                        dma_busy, dma_err, dma_done, dma_done_all,
 
                        // DMA Engine Reg File Update ctrl signals
                        de_csr, de_txsz, de_adr0, de_adr1,
                        de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,
                        de_fetch_descr, dma_rest,
                        ptr_set
 
                );
 
parameter       CH_NO = 0;
parameter       HAVE_ARS = 1;
parameter       HAVE_ED  = 1;
parameter       HAVE_CBUF= 1;
 
input           clk, rst;
 
output  [31:0]   pointer;
output  [31:0]   pointer_s;
output  [31:0]   ch_csr;
output  [31:0]   ch_txsz;
output  [31:0]   ch_adr0;
output  [31:0]   ch_adr1;
output  [31:0]   ch_am0;
output  [31:0]   ch_am1;
output  [31:0]   sw_pointer;
output          ch_stop;
output          ch_dis;
output          int;
 
input   [31:0]   wb_rf_din;
input   [7:0]    wb_rf_adr;
input           wb_rf_we;
input           wb_rf_re;
 
input   [4:0]    ch_sel;
input           ndnr;
 
// DMA Engine Status
input           dma_busy, dma_err, dma_done, dma_done_all;
 
// DMA Engine Reg File Update ctrl signals
input   [31:0]   de_csr;
input   [11:0]   de_txsz;
input   [31:0]   de_adr0;
input   [31:0]   de_adr1;
input           de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
input           de_fetch_descr;
input           dma_rest;
 
assign          pointer = 32'h0;
assign          pointer_s = 32'h0;
assign          ch_csr = 32'h0;
assign          ch_txsz = 32'h0;
assign          ch_adr0 = 32'h0;
assign          ch_adr1 = 32'h0;
assign          ch_am0 = 32'h0;
assign          ch_am1 = 32'h0;
assign          sw_pointer = 32'h0;
assign          ch_stop = 1'b0;
assign          ch_dis = 1'b0;
assign          int = 1'b0;
 
endmodule

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[/] [kiss-board/] [tags/] [initial/] [kiss-board_soc/] [src/] [extend/] [wb_dma/] [wb_dma_ch_rf.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	2	fukuchi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE DMA One Channel Register File ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: wb_dma_ch_rf.v,v 1.1.1.1 2006-05-29 13:45:13 fukuchi Exp $`
42			`//`
43			`// $Date: 2006-05-29 13:45:13 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: fukuchi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.5 2002/02/01 01:54:45 rudi`
52			`//`
53			`// - Minor cleanup`
54			`//`
55			`// Revision 1.4 2001/10/30 02:06:17 rudi`
56			`//`
57			`// - Fixed problem where synthesis tools would instantiate latches instead of flip-flops`
58			`//`
59			`// Revision 1.3 2001/10/19 04:35:04 rudi`
60			`//`
61			`// - Made the core parameterized`
62			`//`
63			`// Revision 1.2 2001/08/15 05:40:30 rudi`
64			`//`
65			`// - Changed IO names to be more clear.`
66			`// - Uniquifyed define names to be core specific.`
67			`// - Added Section 3.10, describing DMA restart.`
68			`//`
69			`// Revision 1.1 2001/07/29 08:57:02 rudi`
70			`//`
71			`//`
72			`// 1) Changed Directory Structure`
73			`// 2) Added restart signal (REST)`
74			`//`
75			`// Revision 1.3 2001/06/14 08:50:01 rudi`
76			`//`
77			`// Changed Module Name to match file name.`
78			`//`
79			`// Revision 1.2 2001/06/13 02:26:48 rudi`
80			`//`
81			`//`
82			`// Small changes after running lint.`
83			`//`
84			`// Revision 1.1 2001/06/05 10:25:27 rudi`
85			`//`
86			`//`
87			`// Initial checkin of register file for one channel.`
88			`//`
89			`//`
90			`//`
91			`//`
92
93			`include "wb_dma_defines.v"
94
95			`module wb_dma_ch_rf( clk, rst,`
96			`pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,`
97			`ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,`
98
99			`wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,`
100
101			`// DMA Registers Write Back Channel Select`
102			`ch_sel, ndnr,`
103
104			`// DMA Engine Status`
105			`dma_busy, dma_err, dma_done, dma_done_all,`
106
107			`// DMA Engine Reg File Update ctrl signals`
108			`de_csr, de_txsz, de_adr0, de_adr1,`
109			`de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,`
110			`de_fetch_descr, dma_rest,`
111			`ptr_set`
112
113			`);`
114
115			`parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID`
116			`parameter [0:0] CH_EN = 1'b1; // This channel exists`
117			`parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS`
118			`parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors`
119			`parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers`
120
121			`input clk, rst;`
122
123			`output [31:0] pointer;`
124			`output [31:0] pointer_s;`
125			`output [31:0] ch_csr;`
126			`output [31:0] ch_txsz;`
127			`output [31:0] ch_adr0;`
128			`output [31:0] ch_adr1;`
129			`output [31:0] ch_am0;`
130			`output [31:0] ch_am1;`
131			`output [31:0] sw_pointer;`
132			`output ch_stop;`
133			`output ch_dis;`
134			`output int;`
135
136			`input [31:0] wb_rf_din;`
137			`input [7:0] wb_rf_adr;`
138			`input wb_rf_we;`
139			`input wb_rf_re;`
140
141			`input [4:0] ch_sel;`
142			`input ndnr;`
143
144			`// DMA Engine Status`
145			`input dma_busy, dma_err, dma_done, dma_done_all;`
146
147			`// DMA Engine Reg File Update ctrl signals`
148			`input [31:0] de_csr;`
149			`input [11:0] de_txsz;`
150			`input [31:0] de_adr0;`
151			`input [31:0] de_adr1;`
152			`input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;`
153			`input de_fetch_descr;`
154			`input dma_rest;`
155
156			`////////////////////////////////////////////////////////////////////`
157			`//`
158			`// Local Wires and Registers`
159			`//`
160
161			`wire [31:0] pointer;`
162			`reg [27:0] pointer_r;`
163			`reg [27:0] pointer_sr;`
164			`reg ptr_valid;`
165			`reg ch_eol;`
166
167			`wire [31:0] ch_csr, ch_txsz;`
168
169			`reg [8:0] ch_csr_r;`
170			`reg [2:0] ch_csr_r2;`
171			`reg [2:0] ch_csr_r3;`
172			`reg [2:0] int_src_r;`
173			`reg ch_err_r;`
174			`reg ch_stop;`
175			`reg ch_busy;`
176			`reg ch_done;`
177			`reg ch_err;`
178			`reg rest_en;`
179
180			`reg [10:0] ch_chk_sz_r;`
181			`reg [11:0] ch_tot_sz_r;`
182			`reg [22:0] ch_txsz_s;`
183			`reg ch_sz_inf;`
184
185			`wire [31:0] ch_adr0, ch_adr1;`
186			`reg [29:0] ch_adr0_r, ch_adr1_r;`
187			`wire [31:0] ch_am0, ch_am1;`
188			`reg [27:0] ch_am0_r, ch_am1_r;`
189
190			`reg [29:0] ch_adr0_s, ch_adr1_s;`
191
192			`reg [29:0] sw_pointer_r;`
193			`wire sw_pointer_we;`
194			`wire [28:0] cmp_adr;`
195			`reg ch_dis;`
196			`wire ch_enable;`
197
198			`wire pointer_we;`
199			`wire ch_csr_we, ch_csr_re, ch_txsz_we, ch_adr0_we, ch_adr1_we;`
200			`wire ch_am0_we, ch_am1_we;`
201			`reg ch_rl;`
202			`wire ch_done_we;`
203			`wire ch_err_we;`
204			`wire chunk_done_we;`
205
206			`wire ch_csr_dewe, ch_txsz_dewe, ch_adr0_dewe, ch_adr1_dewe;`
207
208			`wire this_ptr_set;`
209			`wire ptr_inv;`
210
211			`////////////////////////////////////////////////////////////////////`
212			`//`
213			`// Aliases`
214			`//`
215
216			`assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0;`
217			`assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0;`
218			`assign ch_am0 = (CH_EN & HAVE_CBUF) ? {ch_am0_r, 4'h0} : 32'hffff_fff0;`
219			`assign ch_am1 = (CH_EN & HAVE_CBUF) ? {ch_am1_r, 4'h0} : 32'hffff_fff0;`
220			`assign sw_pointer = (CH_EN & HAVE_CBUF) ? {sw_pointer_r,2'h0} : 32'h0;`
221
222			`assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0;`
223			`assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0;`
224			`assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,`
225			`ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0;`
226			`assign ch_txsz = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0;`
227
228			assign ch_enable = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0;
229
230			`////////////////////////////////////////////////////////////////////`
231			`//`
232			`// CH0 control signals`
233			`//`
234
235			`parameter [4:0] CH_ADR = CH_NO + 5'h1;`
236
237			`assign ch_csr_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);`
238			`assign ch_csr_re = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);`
239			`assign ch_txsz_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1);`
240			`assign ch_adr0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2);`
241			`assign ch_am0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3);`
242			`assign ch_adr1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4);`
243			`assign ch_am1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);`
244			`assign pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);`
245			`assign sw_pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);`
246
247			`assign ch_done_we = CH_EN & (((ch_sel==CH_NO) & dma_done_all) \| ndnr) &`
248			(ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
249			`assign chunk_done_we = CH_EN & (ch_sel==CH_NO) & dma_done;`
250			`assign ch_err_we = CH_EN & (ch_sel==CH_NO) & dma_err;`
251			`assign ch_csr_dewe = CH_EN & de_csr_we & (ch_sel==CH_NO);`
252			`assign ch_txsz_dewe = CH_EN & de_txsz_we & (ch_sel==CH_NO);`
253			`assign ch_adr0_dewe = CH_EN & de_adr0_we & (ch_sel==CH_NO);`
254			`assign ch_adr1_dewe = CH_EN & de_adr1_we & (ch_sel==CH_NO);`
255
256			`assign ptr_inv = CH_EN & ((ch_sel==CH_NO) & dma_done_all) \| ndnr;`
257			`assign this_ptr_set = CH_EN & ptr_set & (ch_sel==CH_NO);`
258
259			`always @(posedge clk)`
260			`ch_rl <= #1 CH_EN & HAVE_ARS & (`
261			`(rest_en & dma_rest) \|`
262			((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
263			`);`
264
265			`// ---------------------------------------------------`
266			`// Pointers`
267
268			`always @(posedge clk or negedge rst)`
269			`if(!rst) ptr_valid <= #1 1'b0;`
270			`else`
271			`if(CH_EN & HAVE_ED)`
272			`begin`
273			`if( this_ptr_set \| (rest_en & dma_rest) )`
274			`ptr_valid <= #1 1'b1;`
275			`else`
276			`if(ptr_inv) ptr_valid <= #1 1'b0;`
277			`end`
278			`else ptr_valid <= #1 1'b0;`
279
280			`always @(posedge clk or negedge rst)`
281			`if(!rst) ch_eol <= #1 1'b0;`
282			`else`
283			`if(CH_EN & HAVE_ED)`
284			`begin`
285			if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL];
286			`else`
287			`if(ch_done_we) ch_eol <= #1 1'b0;`
288			`end`
289			`else ch_eol <= #1 1'b0;`
290
291			`always @(posedge clk)`
292			`if(CH_EN & HAVE_ED)`
293			`begin`
294			`if(pointer_we) pointer_r <= #1 wb_rf_din[31:4];`
295			`else`
296			`if(this_ptr_set) pointer_r <= #1 de_csr[31:4];`
297			`end`
298			`else pointer_r <= #1 1'b0;`
299
300			`always @(posedge clk)`
301			`if(CH_EN & HAVE_ED)`
302			`begin`
303			`if(this_ptr_set) pointer_sr <= #1 pointer_r;`
304			`end`
305			`else pointer_sr <= #1 1'b0;`
306
307			`// ---------------------------------------------------`
308			`// CSR`
309
310			`always @(posedge clk or negedge rst)`
311			`if(!rst) ch_csr_r <= #1 1'b0;`
312			`else`
313			`if(CH_EN)`
314			`begin`
315			`if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0];`
316			`else`
317			`begin`
318			if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
319			`if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];`
320			`end`
321			`end`
322
323			`// done bit`
324			`always @(posedge clk or negedge rst)`
325			`if(!rst) ch_done <= #1 1'b0;`
326			`else`
327			`if(CH_EN)`
328			`begin`
329			if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
330			`else`
331			`if(ch_done_we) ch_done <= #1 1'b1;`
332			`end`
333
334			`// busy bit`
335			`always @(posedge clk)`
336			`ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy;`
337
338			`// stop bit`
339			`always @(posedge clk)`
340			ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP];
341
342			`// error bit`
343			`always @(posedge clk or negedge rst)`
344			`if(!rst) ch_err <= #1 1'b0;`
345			`else`
346			`if(CH_EN)`
347			`begin`
348			`if(ch_err_we) ch_err <= #1 1'b1;`
349			`else`
350			`if(ch_csr_re) ch_err <= #1 1'b0;`
351			`end`
352
353			`// Priority Bits`
354			`always @(posedge clk or negedge rst)`
355			`if(!rst) ch_csr_r2 <= #1 3'h0;`
356			`else`
357			`if(CH_EN & ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13];`
358
359			`// Restart Enable Bit (REST)`
360			`always @(posedge clk or negedge rst)`
361			`if(!rst) rest_en <= #1 1'b0;`
362			`else`
363			`if(CH_EN & ch_csr_we) rest_en <= #1 wb_rf_din[16];`
364
365			`// INT Mask`
366			`always @(posedge clk or negedge rst)`
367			`if(!rst) ch_csr_r3 <= #1 3'h0;`
368			`else`
369			`if(CH_EN & ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17];`
370
371			`// INT Source`
372			`always @(posedge clk or negedge rst)`
373			`if(!rst) int_src_r[2] <= #1 1'b0;`
374			`else`
375			`if(CH_EN)`
376			`begin`
377			`if(chunk_done_we) int_src_r[2] <= #1 1'b1;`
378			`else`
379			`if(ch_csr_re) int_src_r[2] <= #1 1'b0;`
380			`end`
381
382			`always @(posedge clk or negedge rst)`
383			`if(!rst) int_src_r[1] <= #1 1'b0;`
384			`else`
385			`if(CH_EN)`
386			`begin`
387			`if(ch_done_we) int_src_r[1] <= #1 1'b1;`
388			`else`
389			`if(ch_csr_re) int_src_r[1] <= #1 1'b0;`
390			`end`
391
392			`always @(posedge clk or negedge rst)`
393			`if(!rst) int_src_r[0] <= #1 1'b0;`
394			`else`
395			`if(CH_EN)`
396			`begin`
397			`if(ch_err_we) int_src_r[0] <= #1 1'b1;`
398			`else`
399			`if(ch_csr_re) int_src_r[0] <= #1 1'b0;`
400			`end`
401
402			`// Interrupt Output`
403			`assign int = \|(int_src_r & ch_csr_r3) & CH_EN;`
404
405			`// ---------------------------------------------------`
406			`// TXZS`
407			`always @(posedge clk)`
408			`if(CH_EN)`
409			`begin`
410			`if(ch_txsz_we)`
411			`{ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};`
412			`else`
413			`if(ch_txsz_dewe)`
414			`ch_tot_sz_r <= #1 de_txsz;`
415			`else`
416			`if(ch_rl)`
417			`{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;`
418			`end`
419
420			`// txsz shadow register`
421			`always @(posedge clk)`
422			`if(CH_EN & HAVE_ARS)`
423			`begin`
424
425			`if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};`
426			`else`
427			`if(rest_en & ch_txsz_dewe & de_fetch_descr)`
428			`ch_txsz_s[11:0] <= #1 de_txsz[11:0];`
429			`end`
430
431			`// Infinite Size indicator`
432			`always @(posedge clk)`
433			`if(CH_EN)`
434			`begin`
435			`if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15];`
436			`end`
437
438			`// ---------------------------------------------------`
439			`// ADR0`
440			`always @(posedge clk)`
441			`if(CH_EN)`
442			`begin`
443			`if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2];`
444			`else`
445			`if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2];`
446			`else`
447			`if(ch_rl) ch_adr0_r <= #1 ch_adr0_s;`
448			`end`
449
450			`// Adr0 shadow register`
451			`always @(posedge clk)`
452			`if(CH_EN & HAVE_ARS)`
453			`begin`
454			`if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2];`
455			`else`
456			`if(rest_en & ch_adr0_dewe & de_fetch_descr)`
457			`ch_adr0_s <= #1 de_adr0[31:2];`
458			`end`
459
460			`// ---------------------------------------------------`
461			`// AM0`
462			`always @(posedge clk or negedge rst)`
463			`if(!rst) ch_am0_r <= #1 28'hfffffff;`
464			`else`
465			`if(ch_am0_we) ch_am0_r <= #1 wb_rf_din[31:4];`
466
467			`// ---------------------------------------------------`
468			`// ADR1`
469			`always @(posedge clk)`
470			`if(CH_EN)`
471			`begin`
472			`if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2];`
473			`else`
474			`if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2];`
475			`else`
476			`if(ch_rl) ch_adr1_r <= #1 ch_adr1_s;`
477			`end`
478
479			`// Adr1 shadow register`
480			`always @(posedge clk)`
481			`if(CH_EN & HAVE_ARS)`
482			`begin`
483			`if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2];`
484			`else`
485			`if(rest_en & ch_adr1_dewe & de_fetch_descr)`
486			`ch_adr1_s <= #1 de_adr1[31:2];`
487			`end`
488
489			`// ---------------------------------------------------`
490			`// AM1`
491			`always @(posedge clk or negedge rst)`
492			`if(!rst) ch_am1_r <= #1 28'hfffffff;`
493			`else`
494			`if(ch_am1_we & CH_EN & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4];`
495
496			`// ---------------------------------------------------`
497			`// Software Pointer`
498			`always @(posedge clk or negedge rst)`
499			`if(!rst) sw_pointer_r <= #1 28'h0;`
500			`else`
501			`if(sw_pointer_we & CH_EN & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4];`
502
503			`// ---------------------------------------------------`
504			`// Software Pointer Match logic`
505
506			`assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];`
507
508			`always @(posedge clk)`
509			`ch_dis <= #1 CH_EN & HAVE_CBUF & (sw_pointer[30:2] == cmp_adr) & sw_pointer[31];`
510
511			`endmodule`
512
513
514			`module wb_dma_ch_rf_dummy(clk, rst,`
515			`pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,`
516			`ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,`
517
518			`wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,`
519
520			`// DMA Registers Write Back Channel Select`
521			`ch_sel, ndnr,`
522
523			`// DMA Engine Status`
524			`dma_busy, dma_err, dma_done, dma_done_all,`
525
526			`// DMA Engine Reg File Update ctrl signals`
527			`de_csr, de_txsz, de_adr0, de_adr1,`
528			`de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,`
529			`de_fetch_descr, dma_rest,`
530			`ptr_set`
531
532			`);`
533
534			`parameter CH_NO = 0;`
535			`parameter HAVE_ARS = 1;`
536			`parameter HAVE_ED = 1;`
537			`parameter HAVE_CBUF= 1;`
538
539			`input clk, rst;`
540
541			`output [31:0] pointer;`
542			`output [31:0] pointer_s;`
543			`output [31:0] ch_csr;`
544			`output [31:0] ch_txsz;`
545			`output [31:0] ch_adr0;`
546			`output [31:0] ch_adr1;`
547			`output [31:0] ch_am0;`
548			`output [31:0] ch_am1;`
549			`output [31:0] sw_pointer;`
550			`output ch_stop;`
551			`output ch_dis;`
552			`output int;`
553
554			`input [31:0] wb_rf_din;`
555			`input [7:0] wb_rf_adr;`
556			`input wb_rf_we;`
557			`input wb_rf_re;`
558
559			`input [4:0] ch_sel;`
560			`input ndnr;`
561
562			`// DMA Engine Status`
563			`input dma_busy, dma_err, dma_done, dma_done_all;`
564
565			`// DMA Engine Reg File Update ctrl signals`
566			`input [31:0] de_csr;`
567			`input [11:0] de_txsz;`
568			`input [31:0] de_adr0;`
569			`input [31:0] de_adr1;`
570			`input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;`
571			`input de_fetch_descr;`
572			`input dma_rest;`
573
574			`assign pointer = 32'h0;`
575			`assign pointer_s = 32'h0;`
576			`assign ch_csr = 32'h0;`
577			`assign ch_txsz = 32'h0;`
578			`assign ch_adr0 = 32'h0;`
579			`assign ch_adr1 = 32'h0;`
580			`assign ch_am0 = 32'h0;`
581			`assign ch_am1 = 32'h0;`
582			`assign sw_pointer = 32'h0;`
583			`assign ch_stop = 1'b0;`
584			`assign ch_dis = 1'b0;`
585			`assign int = 1'b0;`
586
587			`endmodule`