1 |
2 |
fukuchi |
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`timescale 1ps/1ps
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module tessera_mem_core (
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res,
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clk,
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write_req,
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write_byte,
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write_address,
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write_data,
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write_ack,
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read_req,
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read_byte,
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read_address,
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read_data,
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read_ack,
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mem_cs2_n,
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mem_cs2_g_n,
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mem_cs2_dir,
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mem_cs2_rstdrv,
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mem_cs2_int,
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mem_cs2_iochrdy,
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mem_cs1_n,
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mem_cs1_rst_n,
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mem_cs1_rdy,
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mem_cs0_n,
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mem_we_n,
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mem_oe_n,
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mem_a,
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mem_d_o,
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mem_d_oe,
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mem_d_i
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);
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input res;
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input clk;
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input write_req;
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input [3:0] write_byte;
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input [31:0] write_address;
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input [31:0] write_data;
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output write_ack;
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input read_req;
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input [3:0] read_byte;
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input [31:0] read_address;
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output [31:0] read_data;
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output read_ack;
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//
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output mem_cs2_n;
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output mem_cs2_g_n;
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output mem_cs2_dir;
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output mem_cs2_rstdrv;
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input mem_cs2_int;
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input mem_cs2_iochrdy;
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// for FLASH(big)
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output mem_cs1_n;
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output mem_cs1_rst_n;
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input mem_cs1_rdy;
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// for FLASH(small)
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output mem_cs0_n;
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// misc
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output mem_we_n;
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output mem_oe_n;
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output [22:0] mem_a;
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output [7:0] mem_d_o;
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output [7:0] mem_d_oe;
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input [7:0] mem_d_i;
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//
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// request control(no-ff)
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//
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wire cs0_write_req;
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wire cs0_read_req;
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wire cs1_write_req;
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wire cs1_read_req;
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wire cs2_write_req;
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wire cs2_read_req;
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wire write_fin;
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wire read_fin;
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reg write_ack;
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reg read_ack;
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assign cs0_write_req = write_req && !write_ack && (write_address[23:22]==2'b00); // BASE + 0x000x_xxxx
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assign cs0_read_req = (read_req&&!write_req) && !read_ack && ( read_address[23:22]==2'b00); // BASE + 0x000x_xxxx
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assign cs2_write_req = write_req && !write_ack && (write_address[23:22]==2'b01); // BASE + 0x004x_xxxx
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assign cs2_read_req = (read_req&&!write_req) && !read_ack && ( read_address[23:22]==2'b01); // BASE + 0x004x_xxxx
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assign cs1_write_req = write_req && !write_ack && (write_address[23] ==1'b1); // BASE + 0x008x_xxxx
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assign cs1_read_req = (read_req&&!write_req) && !read_ack && ( read_address[23] ==1'b1); // BASE + 0x008x_xxxx
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//
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// cs0
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//
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wire cs0_write_count_full;
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wire cs0_write_byte_full;
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wire cs0_write_cs;
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wire cs0_write_strobe;
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wire [3:0] cs0_write_load;
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wire [22:0] cs0_write_addr;
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wire cs0_write_fin;
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reg [2:0] cs0_write_count;
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reg [1:0] cs0_write_byte;
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assign cs0_write_count_full = (3'd7==cs0_write_count);
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assign cs0_write_byte_full = (2'd3==cs0_write_byte);
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assign cs0_write_cs = cs0_write_req && (3'd0!=cs0_write_count) && (3'd7!=cs0_write_count);
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assign cs0_write_strobe = cs0_write_req && (3'd0!=cs0_write_count) && (3'd1!=cs0_write_count) && (3'd6!=cs0_write_count) && (3'd7!=cs0_write_count);
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assign cs0_write_load[0] = cs0_write_req && (2'd3==cs0_write_byte) && (3'd0==cs0_write_count);
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assign cs0_write_load[1] = cs0_write_req && (2'd2==cs0_write_byte) && (3'd0==cs0_write_count);
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assign cs0_write_load[2] = cs0_write_req && (2'd1==cs0_write_byte) && (3'd0==cs0_write_count);
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assign cs0_write_load[3] = cs0_write_req && (2'd0==cs0_write_byte) && (3'd0==cs0_write_count);
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assign cs0_write_addr = (cs0_write_req) ? {write_address[22:2],cs0_write_byte[1:0]}: 23'd0;
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assign cs0_write_fin = cs0_write_req && (2'd3==cs0_write_byte) && (3'd7==cs0_write_count);
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always @(posedge clk or posedge res)
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if (res) cs0_write_count <= 3'd0;
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else if (!cs0_write_req) cs0_write_count <= 3'd0;
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else cs0_write_count <= (cs0_write_count_full) ? 3'd0: {cs0_write_count + 3'd1};
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always @(posedge clk or posedge res)
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if (res) cs0_write_byte <= 2'd0;
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else if (!cs0_write_req) cs0_write_byte <= 2'd0;
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else if (cs0_write_count_full) cs0_write_byte <= (cs0_write_byte_full) ? 2'd0: {cs0_write_byte + 2'd1};
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wire cs0_read_count_full;
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wire cs0_read_byte_full;
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wire cs0_read_cs;
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wire cs0_read_strobe;
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wire [3:0] cs0_read_load;
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wire [22:0] cs0_read_addr;
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wire cs0_read_fin;
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reg [2:0] cs0_read_count;
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reg [1:0] cs0_read_byte;
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//assign cs0_read_count_full = (3'd7==cs0_read_count);
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//assign cs0_read_byte_full = (2'd3==cs0_read_byte);
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//assign cs0_read_cs = cs0_read_req && (3'd0!=cs0_read_count) && (3'd7!=cs0_read_count);
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//assign cs0_read_strobe = cs0_read_req && (3'd0!=cs0_read_count) && (3'd1!=cs0_read_count) && (3'd6!=cs0_read_count) && (3'd7!=cs0_read_count);
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//assign cs0_read_load[0] = cs0_read_req && (2'd3==cs0_read_byte) && (3'd7==cs0_read_count);
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//assign cs0_read_load[1] = cs0_read_req && (2'd2==cs0_read_byte) && (3'd7==cs0_read_count);
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//assign cs0_read_load[2] = cs0_read_req && (2'd1==cs0_read_byte) && (3'd7==cs0_read_count);
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//assign cs0_read_load[3] = cs0_read_req && (2'd0==cs0_read_byte) && (3'd7==cs0_read_count);
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//assign cs0_read_addr = (cs0_read_req) ? {read_address[22:2],cs0_read_byte[1:0]}: 23'd0;
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//assign cs0_read_fin = cs0_read_req && (2'd3==cs0_read_byte) && (3'd7==cs0_read_count);
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assign cs0_read_count_full = (3'd7==cs0_read_count);
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assign cs0_read_byte_full = (2'd3==cs0_read_byte);
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assign cs0_read_cs = cs0_read_req && (3'd0!=cs0_read_count) && (3'd7!=cs0_read_count);
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assign cs0_read_strobe = cs0_read_req && (3'd0!=cs0_read_count) && (3'd1!=cs0_read_count) && (3'd6!=cs0_read_count) && (3'd7!=cs0_read_count);
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assign cs0_read_load[0] = cs0_read_req && (2'd3==cs0_read_byte) && (3'd7==cs0_read_count); // test 7->6
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assign cs0_read_load[1] = cs0_read_req && (2'd2==cs0_read_byte) && (3'd7==cs0_read_count); // test 7->6
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assign cs0_read_load[2] = cs0_read_req && (2'd1==cs0_read_byte) && (3'd7==cs0_read_count); // test 7->6
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assign cs0_read_load[3] = cs0_read_req && (2'd0==cs0_read_byte) && (3'd7==cs0_read_count); // test 7->6
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assign cs0_read_addr = (cs0_read_req) ? {read_address[22:2],cs0_read_byte[1:0]}: 23'd0;
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assign cs0_read_fin = cs0_read_req && (2'd3==cs0_read_byte) && (3'd7==cs0_read_count);
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always @(posedge clk or posedge res)
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if (res) cs0_read_count <= 3'd0;
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else if (!cs0_read_req) cs0_read_count <= 3'd0;
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else cs0_read_count <= (cs0_read_count_full) ? 3'd0: {cs0_read_count + 3'd1};
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always @(posedge clk or posedge res)
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if (res) cs0_read_byte <= 2'd0;
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else if (!cs0_read_req) cs0_read_byte <= 2'd0;
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else if (cs0_read_count_full) cs0_read_byte <= (cs0_read_byte_full) ? 2'd0: {cs0_read_byte + 2'd1};
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//
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// cs0 outputs
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//
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reg mem_cs0_n;
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always @(posedge clk or posedge res)
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if (res) mem_cs0_n <= 1'b1;
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else mem_cs0_n <= !(cs0_write_cs||cs0_read_cs);
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//
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// cs1
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//
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wire cs1_write_count_full;
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wire cs1_write_byte_full;
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wire cs1_write_cs;
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wire cs1_write_strobe;
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wire [3:0] cs1_write_load;
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wire [22:0] cs1_write_addr;
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wire cs1_write_fin;
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reg [2:0] cs1_write_count;
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reg [1:0] cs1_write_byte;
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assign cs1_write_count_full = (3'd7==cs1_write_count);
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assign cs1_write_byte_full = (2'd3==cs1_write_byte);
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assign cs1_write_cs = cs1_write_req && (3'd0!=cs1_write_count) && (3'd7!=cs1_write_count);
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assign cs1_write_strobe = cs1_write_req && (3'd0!=cs1_write_count) && (3'd1!=cs1_write_count) && (3'd6!=cs1_write_count) && (3'd7!=cs1_write_count);
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assign cs1_write_load[0] = cs1_write_req && (2'd3==cs1_write_byte) && (3'd0==cs1_write_count);
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assign cs1_write_load[1] = cs1_write_req && (2'd2==cs1_write_byte) && (3'd0==cs1_write_count);
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assign cs1_write_load[2] = cs1_write_req && (2'd1==cs1_write_byte) && (3'd0==cs1_write_count);
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assign cs1_write_load[3] = cs1_write_req && (2'd0==cs1_write_byte) && (3'd0==cs1_write_count);
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assign cs1_write_addr = (cs1_write_req) ? {write_address[22:2],cs1_write_byte[1:0]}: 23'd0;
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assign cs1_write_fin = cs1_write_req && (2'd3==cs1_write_byte) && (3'd7==cs1_write_count);
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always @(posedge clk or posedge res)
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if (res) cs1_write_count <= 3'd0;
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else if (!cs1_write_req) cs1_write_count <= 3'd0;
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else cs1_write_count <= (cs1_write_count_full) ? 3'd0: {cs1_write_count + 3'd1};
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always @(posedge clk or posedge res)
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if (res) cs1_write_byte <= 2'd0;
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else if (!cs1_write_req) cs1_write_byte <= 2'd0;
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else if (cs1_write_count_full) cs1_write_byte <= (cs1_write_byte_full) ? 2'd0: {cs1_write_byte + 2'd1};
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wire cs1_read_count_full;
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wire cs1_read_byte_full;
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wire cs1_read_cs;
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wire cs1_read_strobe;
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wire [3:0] cs1_read_load;
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wire [22:0] cs1_read_addr;
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wire cs1_read_fin;
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reg [2:0] cs1_read_count;
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reg [1:0] cs1_read_byte;
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assign cs1_read_count_full = (3'd7==cs1_read_count);
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assign cs1_read_byte_full = (2'd3==cs1_read_byte);
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assign cs1_read_cs = cs1_read_req && (3'd0!=cs1_read_count) && (3'd7!=cs1_read_count);
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assign cs1_read_strobe = cs1_read_req && (3'd0!=cs1_read_count) && (3'd1!=cs1_read_count) && (3'd6!=cs1_read_count) && (3'd7!=cs1_read_count);
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assign cs1_read_load[0] = cs1_read_req && (2'd3==cs1_read_byte) && (3'd7==cs1_read_count);
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assign cs1_read_load[1] = cs1_read_req && (2'd2==cs1_read_byte) && (3'd7==cs1_read_count);
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assign cs1_read_load[2] = cs1_read_req && (2'd1==cs1_read_byte) && (3'd7==cs1_read_count);
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assign cs1_read_load[3] = cs1_read_req && (2'd0==cs1_read_byte) && (3'd7==cs1_read_count);
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assign cs1_read_addr = (cs1_read_req) ? {read_address[22:2],cs1_read_byte[1:0]}: 23'd0;
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assign cs1_read_fin = cs1_read_req && (2'd3==cs1_read_byte) && (3'd7==cs1_read_count);
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always @(posedge clk or posedge res)
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if (res) cs1_read_count <= 3'd0;
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else if (!cs1_read_req) cs1_read_count <= 3'd0;
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214 |
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else cs1_read_count <= (cs1_read_count_full) ? 3'd0: {cs1_read_count + 3'd1};
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215 |
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always @(posedge clk or posedge res)
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if (res) cs1_read_byte <= 2'd0;
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217 |
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else if (!cs1_read_req) cs1_read_byte <= 2'd0;
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218 |
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else if (cs1_read_count_full) cs1_read_byte <= (cs1_read_byte_full) ? 2'd0: {cs1_read_byte + 2'd1};
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219 |
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//
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220 |
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// cs1 outputs
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//
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222 |
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reg mem_cs1_n;
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reg mem_cs1_rst_n;
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always @(posedge clk or posedge res)
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225 |
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if (res) mem_cs1_n <= 1'b1;
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226 |
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else mem_cs1_n <= !(cs1_write_cs||cs1_read_cs);
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227 |
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always @(posedge clk or posedge res)
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if (res) mem_cs1_rst_n <= 1'b0;
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else mem_cs1_rst_n <= 1'b1;
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230 |
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//
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231 |
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// cs2
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232 |
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//
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233 |
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wire cs2_write_count_full;
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234 |
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wire cs2_write_byte_full;
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235 |
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wire cs2_write_cs;
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236 |
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wire cs2_write_strobe;
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237 |
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wire [3:0] cs2_write_load;
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238 |
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wire [22:0] cs2_write_addr;
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239 |
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wire cs2_write_fin;
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240 |
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reg [2:0] cs2_write_count;
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241 |
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reg [1:0] cs2_write_byte;
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242 |
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assign cs2_write_count_full = (3'd7==cs2_write_count);
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243 |
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assign cs2_write_byte_full = (2'd3==cs2_write_byte);
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244 |
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assign cs2_write_cs = cs2_write_req && (3'd0!=cs2_write_count) && (3'd7!=cs2_write_count);
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245 |
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assign cs2_write_strobe = cs2_write_req && (3'd0!=cs2_write_count) && (3'd1!=cs2_write_count) && (3'd6!=cs2_write_count) && (3'd7!=cs2_write_count);
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246 |
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assign cs2_write_load[0] = cs2_write_req && (2'd3==cs2_write_byte) && (3'd0==cs2_write_count);
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247 |
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assign cs2_write_load[1] = cs2_write_req && (2'd2==cs2_write_byte) && (3'd0==cs2_write_count);
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248 |
|
|
assign cs2_write_load[2] = cs2_write_req && (2'd1==cs2_write_byte) && (3'd0==cs2_write_count);
|
249 |
|
|
assign cs2_write_load[3] = cs2_write_req && (2'd0==cs2_write_byte) && (3'd0==cs2_write_count);
|
250 |
|
|
assign cs2_write_addr = (cs2_write_req) ? {write_address[22:2],cs2_write_byte[1:0]}: 23'd0;
|
251 |
|
|
assign cs2_write_fin = cs2_write_req && (2'd3==cs2_write_byte) && (3'd7==cs2_write_count);
|
252 |
|
|
always @(posedge clk or posedge res)
|
253 |
|
|
if (res) cs2_write_count <= 3'd0;
|
254 |
|
|
else if (!cs2_write_req) cs2_write_count <= 3'd0;
|
255 |
|
|
else cs2_write_count <= (cs2_write_count_full) ? 3'd0: {cs2_write_count + 3'd1};
|
256 |
|
|
always @(posedge clk or posedge res)
|
257 |
|
|
if (res) cs2_write_byte <= 2'd0;
|
258 |
|
|
else if (!cs2_write_req) cs2_write_byte <= 2'd0;
|
259 |
|
|
else if (cs2_write_count_full) cs2_write_byte <= (cs2_write_byte_full) ? 2'd0: {cs2_write_byte + 2'd1};
|
260 |
|
|
wire cs2_read_count_full;
|
261 |
|
|
wire cs2_read_byte_full;
|
262 |
|
|
wire cs2_read_cs;
|
263 |
|
|
wire cs2_read_strobe;
|
264 |
|
|
wire [3:0] cs2_read_load;
|
265 |
|
|
wire [22:0] cs2_read_addr;
|
266 |
|
|
wire cs2_read_fin;
|
267 |
|
|
reg [2:0] cs2_read_count;
|
268 |
|
|
reg [1:0] cs2_read_byte;
|
269 |
|
|
assign cs2_read_count_full = (3'd7==cs2_read_count);
|
270 |
|
|
assign cs2_read_byte_full = (2'd3==cs2_read_byte);
|
271 |
|
|
assign cs2_read_cs = cs2_read_req && (3'd0!=cs2_read_count) && (3'd7!=cs2_read_count);
|
272 |
|
|
assign cs2_read_strobe = cs2_read_req && (3'd0!=cs2_read_count) && (3'd1!=cs2_read_count) && (3'd6!=cs2_read_count) && (3'd7!=cs2_read_count);
|
273 |
|
|
assign cs2_read_load[0] = cs2_read_req && (2'd3==cs2_read_byte) && (3'd7==cs2_read_count);
|
274 |
|
|
assign cs2_read_load[1] = cs2_read_req && (2'd2==cs2_read_byte) && (3'd7==cs2_read_count);
|
275 |
|
|
assign cs2_read_load[2] = cs2_read_req && (2'd1==cs2_read_byte) && (3'd7==cs2_read_count);
|
276 |
|
|
assign cs2_read_load[3] = cs2_read_req && (2'd0==cs2_read_byte) && (3'd7==cs2_read_count);
|
277 |
|
|
assign cs2_read_fin = cs2_read_req && (2'd3==cs2_read_byte) && (3'd7==cs2_read_count);
|
278 |
|
|
assign cs2_read_addr = (cs2_read_req) ? {read_address[22:2],cs2_read_byte[1:0]}: 23'd0;
|
279 |
|
|
always @(posedge clk or posedge res)
|
280 |
|
|
if (res) cs2_read_count <= 3'd0;
|
281 |
|
|
else if (!cs2_read_req) cs2_read_count <= 3'd0;
|
282 |
|
|
else cs2_read_count <= (cs2_read_count_full) ? 3'd0: {cs2_read_count + 3'd1};
|
283 |
|
|
always @(posedge clk or posedge res)
|
284 |
|
|
if (res) cs2_read_byte <= 2'd0;
|
285 |
|
|
else if (!cs2_read_req) cs2_read_byte <= 2'd0;
|
286 |
|
|
else if (cs2_read_count_full) cs2_read_byte <= (cs2_read_byte_full) ? 2'd0: {cs2_read_byte + 2'd1};
|
287 |
|
|
//
|
288 |
|
|
// cs2 outputs
|
289 |
|
|
//
|
290 |
|
|
reg mem_cs2_n;
|
291 |
|
|
reg mem_cs2_g_n;
|
292 |
|
|
reg mem_cs2_dir;
|
293 |
|
|
reg mem_cs2_rstdrv;
|
294 |
|
|
always @(posedge clk or posedge res)
|
295 |
|
|
if (res) mem_cs2_n <= 1'b1;
|
296 |
|
|
else mem_cs2_n <= !(cs2_write_cs||cs2_read_cs);
|
297 |
|
|
always @(posedge clk or posedge res)
|
298 |
|
|
if (res) mem_cs2_g_n <= 1'b1;
|
299 |
|
|
else mem_cs2_g_n <= !(cs2_write_cs||cs2_read_strobe);
|
300 |
|
|
always @(posedge clk or posedge res)
|
301 |
|
|
if (res) mem_cs2_dir <= 1'b1;
|
302 |
|
|
else mem_cs2_dir <= (cs2_write_req) ? 1'b1: (cs2_read_req) ? 1'b0: mem_cs2_dir;
|
303 |
|
|
always @(posedge clk or posedge res)
|
304 |
|
|
if (res) mem_cs2_rstdrv <= 1'b1;
|
305 |
|
|
else mem_cs2_rstdrv <= 1'b0;
|
306 |
|
|
//
|
307 |
|
|
//
|
308 |
|
|
//
|
309 |
|
|
wire write_strobe;
|
310 |
|
|
wire read_strobe;
|
311 |
|
|
|
312 |
|
|
wire [3:0] write_load;
|
313 |
|
|
wire [3:0] read_load;
|
314 |
|
|
|
315 |
|
|
wire [22:0] write_addr;
|
316 |
|
|
wire [22:0] read_addr;
|
317 |
|
|
|
318 |
|
|
|
319 |
|
|
assign write_strobe = cs2_write_strobe || cs1_write_strobe || cs0_write_strobe;
|
320 |
|
|
assign read_strobe = cs2_read_strobe || cs1_read_strobe || cs0_read_strobe;
|
321 |
|
|
|
322 |
|
|
assign write_load = cs2_write_load|cs1_write_load|cs0_write_load;
|
323 |
|
|
assign read_load = cs2_read_load |cs1_read_load |cs0_read_load;
|
324 |
|
|
|
325 |
|
|
assign write_addr = cs2_write_addr|cs1_write_addr|cs0_write_addr;
|
326 |
|
|
assign read_addr = cs2_read_addr |cs1_read_addr |cs0_read_addr;
|
327 |
|
|
|
328 |
|
|
//
|
329 |
|
|
// outputs(common)
|
330 |
|
|
//
|
331 |
|
|
reg mem_we_n;
|
332 |
|
|
reg mem_oe_n;
|
333 |
|
|
reg [22:0] mem_a;
|
334 |
|
|
reg [7:0] mem_d_oe;
|
335 |
|
|
always @(posedge clk or posedge res)
|
336 |
|
|
if (res) mem_we_n <= 1'b1;
|
337 |
|
|
else mem_we_n <= !write_strobe;
|
338 |
|
|
always @(posedge clk or posedge res)
|
339 |
|
|
if (res) mem_oe_n <= 1'b1;
|
340 |
|
|
else mem_oe_n <= !read_strobe;
|
341 |
|
|
always @(posedge clk or posedge res)
|
342 |
|
|
if (res) mem_a <= 23'h00_0000;
|
343 |
|
|
else mem_a <= write_addr|read_addr;
|
344 |
|
|
always @(posedge clk or posedge res)
|
345 |
|
|
if (res) mem_d_oe <= 8'h00;
|
346 |
|
|
else mem_d_oe <= {8{cs2_write_cs||cs1_write_cs||cs0_write_cs}}; // only write
|
347 |
|
|
//
|
348 |
|
|
// inputs(common)
|
349 |
|
|
//
|
350 |
|
|
//
|
351 |
|
|
// int->ext
|
352 |
|
|
//
|
353 |
|
|
reg [7:0] pre_mem_d_o;
|
354 |
|
|
always @(posedge clk or posedge res)
|
355 |
|
|
if (res) pre_mem_d_o <= 32'h0000_0000;
|
356 |
|
|
else begin
|
357 |
|
|
if (write_load[3]) pre_mem_d_o <= write_data[31:24];
|
358 |
|
|
if (write_load[2]) pre_mem_d_o <= write_data[23:16];
|
359 |
|
|
if (write_load[1]) pre_mem_d_o <= write_data[15: 8];
|
360 |
|
|
if (write_load[0]) pre_mem_d_o <= write_data[ 7: 0];
|
361 |
|
|
end
|
362 |
|
|
//
|
363 |
|
|
reg [7:0] mem_d_o; // IOB
|
364 |
|
|
always @(posedge clk or posedge res)
|
365 |
|
|
if (res) mem_d_o <= 8'h00;
|
366 |
|
|
else mem_d_o <= pre_mem_d_o;
|
367 |
|
|
|
368 |
|
|
//
|
369 |
|
|
// ext->int
|
370 |
|
|
//
|
371 |
|
|
reg [7:0] pre_mem_d_i; // IOB
|
372 |
|
|
always @(posedge clk or posedge res)
|
373 |
|
|
if (res) pre_mem_d_i <= 8'h00;
|
374 |
|
|
else pre_mem_d_i <= mem_d_i;
|
375 |
|
|
//
|
376 |
|
|
reg [31:0] read_data;
|
377 |
|
|
always @(posedge clk or posedge res)
|
378 |
|
|
if (res) read_data <= 32'h0000_0000;
|
379 |
|
|
else begin
|
380 |
|
|
if (read_load[3]) read_data[31:24] <= pre_mem_d_i;
|
381 |
|
|
if (read_load[2]) read_data[23:16] <= pre_mem_d_i;
|
382 |
|
|
if (read_load[1]) read_data[15: 8] <= pre_mem_d_i;
|
383 |
|
|
if (read_load[0]) read_data[ 7: 0] <= pre_mem_d_i;
|
384 |
|
|
end
|
385 |
|
|
//
|
386 |
|
|
// ack
|
387 |
|
|
//
|
388 |
|
|
assign write_fin = cs2_write_fin || cs1_write_fin || cs0_write_fin;
|
389 |
|
|
always @(posedge clk or posedge res)
|
390 |
|
|
if (res) write_ack <= 1'b0;
|
391 |
|
|
else if (!write_req) write_ack <= 1'b0;
|
392 |
|
|
else if (write_fin) write_ack <= 1'b1;
|
393 |
|
|
assign read_fin = cs2_read_fin || cs1_read_fin || cs0_read_fin;
|
394 |
|
|
always @(posedge clk or posedge res)
|
395 |
|
|
if (res) read_ack <= 1'b0;
|
396 |
|
|
else if (!read_req) read_ack <= 1'b0;
|
397 |
|
|
else if (read_fin) read_ack <= 1'b1;
|
398 |
|
|
endmodule
|
399 |
|
|
|
400 |
|
|
module tessera_mem_wbif (
|
401 |
|
|
res,
|
402 |
|
|
clk,
|
403 |
|
|
wb_cyc_i,
|
404 |
|
|
wb_stb_i,
|
405 |
|
|
wb_adr_i,
|
406 |
|
|
wb_sel_i,
|
407 |
|
|
wb_we_i,
|
408 |
|
|
wb_dat_i,
|
409 |
|
|
wb_cab_i,
|
410 |
|
|
wb_dat_o,
|
411 |
|
|
wb_ack_o,
|
412 |
|
|
wb_err_o,
|
413 |
|
|
write_req,
|
414 |
|
|
write_byte,
|
415 |
|
|
write_address,
|
416 |
|
|
write_data,
|
417 |
|
|
write_ack,
|
418 |
|
|
read_req,
|
419 |
|
|
read_byte,
|
420 |
|
|
read_address,
|
421 |
|
|
read_data,
|
422 |
|
|
read_ack
|
423 |
|
|
);
|
424 |
|
|
input res;
|
425 |
|
|
input clk;
|
426 |
|
|
input wb_cyc_i;
|
427 |
|
|
input wb_stb_i;
|
428 |
|
|
input [31:0] wb_adr_i;
|
429 |
|
|
input [3:0] wb_sel_i;
|
430 |
|
|
input wb_we_i;
|
431 |
|
|
input [31:0] wb_dat_i;
|
432 |
|
|
input wb_cab_i;
|
433 |
|
|
output [31:0] wb_dat_o;
|
434 |
|
|
output wb_ack_o;
|
435 |
|
|
output wb_err_o;
|
436 |
|
|
output write_req;
|
437 |
|
|
output [3:0] write_byte;
|
438 |
|
|
output [31:0] write_address;
|
439 |
|
|
output [31:0] write_data;
|
440 |
|
|
input write_ack;
|
441 |
|
|
output read_req;
|
442 |
|
|
output [3:0] read_byte;
|
443 |
|
|
output [31:0] read_address;
|
444 |
|
|
input [31:0] read_data;
|
445 |
|
|
input read_ack;
|
446 |
|
|
//
|
447 |
|
|
//
|
448 |
|
|
//
|
449 |
|
|
assign wb_err_o = 1'b0;
|
450 |
|
|
//
|
451 |
|
|
//
|
452 |
|
|
//
|
453 |
|
|
reg write_ack_z;
|
454 |
|
|
reg read_ack_z;
|
455 |
|
|
reg wb_ack;
|
456 |
|
|
always @(posedge clk or posedge res)
|
457 |
|
|
if (res) write_ack_z <= 1'b0;
|
458 |
|
|
else write_ack_z <= write_ack;
|
459 |
|
|
always @(posedge clk or posedge res)
|
460 |
|
|
if (res) read_ack_z <= 1'b0;
|
461 |
|
|
else read_ack_z <= read_ack;
|
462 |
|
|
always @(posedge clk or posedge res)
|
463 |
|
|
if (res) wb_ack <= 1'b0;
|
464 |
|
|
//else wb_ack <= (write_ack_z&&!write_ack)||(read_ack_z&&!read_ack); // release negedge ack(late)
|
465 |
|
|
else wb_ack <= (!write_ack_z&&write_ack)||(!read_ack_z&&read_ack); // release posedge ack(fast)
|
466 |
|
|
assign wb_ack_o = (wb_cyc_i&&wb_stb_i) ? wb_ack: 1'b0;
|
467 |
|
|
//
|
468 |
|
|
//
|
469 |
|
|
//
|
470 |
|
|
reg [31:0] wb_dat;
|
471 |
|
|
always @(posedge clk or posedge res)
|
472 |
|
|
if (res) wb_dat <= {4{8'h00}};
|
473 |
|
|
else wb_dat <= read_data;
|
474 |
|
|
assign wb_dat_o = (wb_cyc_i&&wb_stb_i) ? wb_dat[31:0]: {4{8'h00}};
|
475 |
|
|
//
|
476 |
|
|
//
|
477 |
|
|
//
|
478 |
|
|
reg [3:0] write_byte;
|
479 |
|
|
reg [31:0] write_address;
|
480 |
|
|
reg [31:0] write_data;
|
481 |
|
|
//
|
482 |
|
|
reg [3:0] read_byte;
|
483 |
|
|
reg [31:0] read_address;
|
484 |
|
|
always @(posedge clk or posedge res)
|
485 |
|
|
if (res) begin
|
486 |
|
|
write_byte <= {4{1'b0}};
|
487 |
|
|
write_address <= 32'd0;
|
488 |
|
|
write_data <= {4{8'h00}};
|
489 |
|
|
//
|
490 |
|
|
read_byte <= {4{1'b0}};
|
491 |
|
|
read_address <= 32'd0;
|
492 |
|
|
end
|
493 |
|
|
else begin
|
494 |
|
|
write_byte <= wb_sel_i;
|
495 |
|
|
write_address <= {8'd0,wb_adr_i[23:0]};
|
496 |
|
|
write_data <= wb_dat_i;
|
497 |
|
|
//
|
498 |
|
|
read_byte <= wb_sel_i;
|
499 |
|
|
read_address <= {8'd0,wb_adr_i[23:0]};
|
500 |
|
|
end
|
501 |
|
|
//
|
502 |
|
|
//
|
503 |
|
|
//
|
504 |
|
|
reg write_req;
|
505 |
|
|
reg read_req;
|
506 |
|
|
always @(posedge clk or posedge res)
|
507 |
|
|
if (res) write_req <= 1'b0;
|
508 |
|
|
else if (write_ack) write_req <= 1'b0;
|
509 |
|
|
else if (wb_cyc_i && wb_stb_i && !wb_ack_o && !write_ack_z && wb_we_i) write_req <= 1'b1; // wait ack low
|
510 |
|
|
|
511 |
|
|
always @(posedge clk or posedge res)
|
512 |
|
|
if (res) read_req <= 1'b0;
|
513 |
|
|
else if (read_ack) read_req <= 1'b0;
|
514 |
|
|
else if (wb_cyc_i && wb_stb_i && !wb_ack_o && !read_ack_z && !wb_we_i) read_req <= 1'b1; // wait ack low
|
515 |
|
|
|
516 |
|
|
endmodule
|
517 |
|
|
|
518 |
|
|
module tessera_mem (
|
519 |
|
|
//
|
520 |
|
|
sys_wb_res,
|
521 |
|
|
sys_wb_clk,
|
522 |
|
|
//
|
523 |
|
|
sys_mem_res,
|
524 |
|
|
sys_mem_clk,
|
525 |
|
|
//
|
526 |
|
|
wb_cyc_i,
|
527 |
|
|
wb_stb_i,
|
528 |
|
|
wb_adr_i,
|
529 |
|
|
wb_sel_i,
|
530 |
|
|
wb_we_i,
|
531 |
|
|
wb_dat_i,
|
532 |
|
|
wb_cab_i,
|
533 |
|
|
wb_dat_o,
|
534 |
|
|
wb_ack_o,
|
535 |
|
|
wb_err_o,
|
536 |
|
|
//
|
537 |
|
|
mem_cs2_n,
|
538 |
|
|
mem_cs2_g_n,
|
539 |
|
|
mem_cs2_dir,
|
540 |
|
|
mem_cs2_rstdrv,
|
541 |
|
|
mem_cs2_int,
|
542 |
|
|
mem_cs2_iochrdy,
|
543 |
|
|
//
|
544 |
|
|
mem_cs1_n,
|
545 |
|
|
mem_cs1_rst_n,
|
546 |
|
|
mem_cs1_rdy,
|
547 |
|
|
//
|
548 |
|
|
mem_cs0_n,
|
549 |
|
|
//
|
550 |
|
|
mem_we_n,
|
551 |
|
|
mem_oe_n,
|
552 |
|
|
mem_a,
|
553 |
|
|
mem_d_o,
|
554 |
|
|
mem_d_oe,
|
555 |
|
|
mem_d_i
|
556 |
|
|
);
|
557 |
|
|
// System
|
558 |
|
|
input sys_wb_res;
|
559 |
|
|
input sys_wb_clk;
|
560 |
|
|
input sys_mem_res;
|
561 |
|
|
input sys_mem_clk;
|
562 |
|
|
// WishBone
|
563 |
|
|
input wb_cyc_i;
|
564 |
|
|
input wb_stb_i;
|
565 |
|
|
input [31:0] wb_adr_i;
|
566 |
|
|
input [3:0] wb_sel_i;
|
567 |
|
|
input wb_we_i;
|
568 |
|
|
input [31:0] wb_dat_i;
|
569 |
|
|
input wb_cab_i;
|
570 |
|
|
output [31:0] wb_dat_o;
|
571 |
|
|
output wb_ack_o;
|
572 |
|
|
output wb_err_o;
|
573 |
|
|
// for MAC-PHY
|
574 |
|
|
output mem_cs2_n;
|
575 |
|
|
output mem_cs2_g_n;
|
576 |
|
|
output mem_cs2_dir;
|
577 |
|
|
output mem_cs2_rstdrv;
|
578 |
|
|
input mem_cs2_int;
|
579 |
|
|
input mem_cs2_iochrdy;
|
580 |
|
|
// for FLASH(big)
|
581 |
|
|
output mem_cs1_n;
|
582 |
|
|
output mem_cs1_rst_n;
|
583 |
|
|
input mem_cs1_rdy;
|
584 |
|
|
// for FLASH(small)
|
585 |
|
|
output mem_cs0_n;
|
586 |
|
|
// misc
|
587 |
|
|
output mem_we_n;
|
588 |
|
|
output mem_oe_n;
|
589 |
|
|
output [22:0] mem_a;
|
590 |
|
|
output [7:0] mem_d_o;
|
591 |
|
|
output [7:0] mem_d_oe;
|
592 |
|
|
input [7:0] mem_d_i;
|
593 |
|
|
|
594 |
|
|
// mem_wbif
|
595 |
|
|
wire wbif_write_req;
|
596 |
|
|
wire [3:0] wbif_write_byte;
|
597 |
|
|
wire [31:0] wbif_write_address;
|
598 |
|
|
wire [31:0] wbif_write_data;
|
599 |
|
|
//wire wbif_write_ack;
|
600 |
|
|
reg wbif_write_ack;
|
601 |
|
|
wire wbif_read_req;
|
602 |
|
|
wire [3:0] wbif_read_byte;
|
603 |
|
|
wire [31:0] wbif_read_address;
|
604 |
|
|
wire [31:0] wbif_read_data;
|
605 |
|
|
//wire wbif_read_ack;
|
606 |
|
|
reg wbif_read_ack;
|
607 |
|
|
|
608 |
|
|
// me,_core
|
609 |
|
|
//wire core_write_req;
|
610 |
|
|
reg core_write_req;
|
611 |
|
|
wire [3:0] core_write_byte;
|
612 |
|
|
wire [31:0] core_write_address;
|
613 |
|
|
wire [31:0] core_write_data;
|
614 |
|
|
wire core_write_ack;
|
615 |
|
|
//wire core_read_req;
|
616 |
|
|
reg core_read_req;
|
617 |
|
|
wire [3:0] core_read_byte;
|
618 |
|
|
wire [31:0] core_read_address;
|
619 |
|
|
wire [31:0] core_read_data;
|
620 |
|
|
wire core_read_ack;
|
621 |
|
|
// WishBone Clock domain
|
622 |
|
|
tessera_mem_wbif i_tessera_mem_wbif (
|
623 |
|
|
.res( sys_wb_res),
|
624 |
|
|
.clk( sys_wb_clk),
|
625 |
|
|
.wb_cyc_i( wb_cyc_i),
|
626 |
|
|
.wb_stb_i( wb_stb_i),
|
627 |
|
|
.wb_adr_i( wb_adr_i),
|
628 |
|
|
.wb_sel_i( wb_sel_i),
|
629 |
|
|
.wb_we_i( wb_we_i),
|
630 |
|
|
.wb_dat_i( wb_dat_i),
|
631 |
|
|
.wb_cab_i( wb_cab_i),
|
632 |
|
|
.wb_dat_o( wb_dat_o),
|
633 |
|
|
.wb_ack_o( wb_ack_o),
|
634 |
|
|
.wb_err_o( wb_err_o),
|
635 |
|
|
.write_req( wbif_write_req),
|
636 |
|
|
.write_byte( wbif_write_byte),
|
637 |
|
|
.write_address( wbif_write_address),
|
638 |
|
|
.write_data( wbif_write_data),
|
639 |
|
|
.write_ack( wbif_write_ack),
|
640 |
|
|
.read_req( wbif_read_req),
|
641 |
|
|
.read_byte( wbif_read_byte),
|
642 |
|
|
.read_address( wbif_read_address),
|
643 |
|
|
.read_data( wbif_read_data),
|
644 |
|
|
.read_ack( wbif_read_ack)
|
645 |
|
|
);
|
646 |
|
|
// no-mt1-mt2(TYPE A:same clock)
|
647 |
|
|
/*
|
648 |
|
|
// sd to wb
|
649 |
|
|
assign wbif_write_ack = core_write_ack;
|
650 |
|
|
assign wbif_read_data = core_read_data;
|
651 |
|
|
assign wbif_read_ack = core_read_ack;
|
652 |
|
|
// wb to sd
|
653 |
|
|
assign core_write_req = wbif_write_req;
|
654 |
|
|
assign core_write_byte = wbif_write_byte;
|
655 |
|
|
assign core_write_address = wbif_write_address;
|
656 |
|
|
assign core_write_data = wbif_write_data;
|
657 |
|
|
assign core_read_req = wbif_read_req;
|
658 |
|
|
assign core_read_byte = wbif_read_byte;
|
659 |
|
|
assign core_read_address = wbif_read_address;
|
660 |
|
|
*/
|
661 |
|
|
// only startpoint(TYPE B:same clock,pos<->neg,timeing is safety)
|
662 |
|
|
/*
|
663 |
|
|
reg mt_write_ack;
|
664 |
|
|
reg [31:0] mt_read_data;
|
665 |
|
|
reg mt_read_ack;
|
666 |
|
|
always @(posedge sys_wb_clk or posedge sys_wb_res)
|
667 |
|
|
if (sys_wb_res) begin
|
668 |
|
|
mt_write_ack <= 1'b0;
|
669 |
|
|
mt_read_data <= {4{8'h00}};
|
670 |
|
|
mt_read_ack <= 1'b0;
|
671 |
|
|
end
|
672 |
|
|
else begin
|
673 |
|
|
mt_write_ack <= core_write_ack;
|
674 |
|
|
mt_read_data <= core_read_data;
|
675 |
|
|
mt_read_ack <= core_read_ack;
|
676 |
|
|
end
|
677 |
|
|
reg mt_write_req;
|
678 |
|
|
reg [3:0] mt_write_byte;
|
679 |
|
|
reg [31:0] mt_write_address;
|
680 |
|
|
reg [31:0] mt_write_data;
|
681 |
|
|
reg mt_read_req;
|
682 |
|
|
reg [3:0] mt_read_byte;
|
683 |
|
|
reg [31:0] mt_read_address;
|
684 |
|
|
always @(posedge sys_mem_clk or posedge sys_mem_res)
|
685 |
|
|
if (sys_mem_res) begin
|
686 |
|
|
mt_write_req <= 1'b0;
|
687 |
|
|
mt_write_byte <= {4{1'b0}};
|
688 |
|
|
mt_write_address <= 32'd0;
|
689 |
|
|
mt_write_data <= {4{8'h00}};
|
690 |
|
|
mt_read_req <= 1'b0;
|
691 |
|
|
mt_read_byte <= {4{1'b0}};
|
692 |
|
|
mt_read_address <= 32'd0;
|
693 |
|
|
end
|
694 |
|
|
else begin
|
695 |
|
|
mt_write_req <= wbif_write_req;
|
696 |
|
|
mt_write_byte <= wbif_write_byte;
|
697 |
|
|
mt_write_address <= wbif_write_address;
|
698 |
|
|
mt_write_data <= wbif_write_data;
|
699 |
|
|
mt_read_req <= wbif_read_req;
|
700 |
|
|
mt_read_byte <= wbif_read_byte;
|
701 |
|
|
mt_read_address <= wbif_read_address;
|
702 |
|
|
end
|
703 |
|
|
// sd to wb
|
704 |
|
|
assign wbif_write_ack = mt_write_ack;
|
705 |
|
|
assign wbif_read_data = mt_read_data;
|
706 |
|
|
assign wbif_read_ack = mt_read_ack;
|
707 |
|
|
// wb to sd
|
708 |
|
|
assign core_write_req = mt_write_req;
|
709 |
|
|
assign core_write_byte = mt_write_byte;
|
710 |
|
|
assign core_write_address = mt_write_address;
|
711 |
|
|
assign core_write_data = mt_write_data;
|
712 |
|
|
assign core_read_req = mt_read_req;
|
713 |
|
|
assign core_read_byte = mt_read_byte;
|
714 |
|
|
assign core_read_address = mt_read_address;
|
715 |
|
|
*/
|
716 |
|
|
// mt1 mt2(TYPE C:other clock)
|
717 |
|
|
reg mt1_write_ack;
|
718 |
|
|
reg [31:0] mt1_read_data;
|
719 |
|
|
reg mt1_read_ack;
|
720 |
|
|
always @(posedge sys_wb_clk or posedge sys_wb_res)
|
721 |
|
|
if (sys_wb_res) begin
|
722 |
|
|
mt1_write_ack <= 1'b0;
|
723 |
|
|
mt1_read_data <= {4{8'h00}};
|
724 |
|
|
mt1_read_ack <= 1'b0;
|
725 |
|
|
end
|
726 |
|
|
else begin
|
727 |
|
|
mt1_write_ack <= core_write_ack;
|
728 |
|
|
mt1_read_data <= core_read_data;
|
729 |
|
|
mt1_read_ack <= core_read_ack;
|
730 |
|
|
end
|
731 |
|
|
reg mt2_write_ack;
|
732 |
|
|
reg [31:0] mt2_read_data;
|
733 |
|
|
reg mt2_read_ack;
|
734 |
|
|
always @(posedge sys_wb_clk or posedge sys_wb_res)
|
735 |
|
|
if (sys_wb_res) begin
|
736 |
|
|
mt2_write_ack <= 1'b0;
|
737 |
|
|
mt2_read_data <= {4{8'h00}};
|
738 |
|
|
mt2_read_ack <= 1'b0;
|
739 |
|
|
end
|
740 |
|
|
else begin
|
741 |
|
|
mt2_write_ack <= mt1_write_ack;
|
742 |
|
|
mt2_read_data <= mt1_read_data;
|
743 |
|
|
mt2_read_ack <= mt1_read_ack;
|
744 |
|
|
end
|
745 |
|
|
reg mt1_write_req;
|
746 |
|
|
reg [3:0] mt1_write_byte;
|
747 |
|
|
reg [31:0] mt1_write_address;
|
748 |
|
|
reg [31:0] mt1_write_data;
|
749 |
|
|
reg mt1_read_req;
|
750 |
|
|
reg [3:0] mt1_read_byte;
|
751 |
|
|
reg [31:0] mt1_read_address;
|
752 |
|
|
always @(posedge sys_mem_clk or posedge sys_mem_res)
|
753 |
|
|
if (sys_mem_res) begin
|
754 |
|
|
mt1_write_req <= 1'b0;
|
755 |
|
|
mt1_write_byte <= {4{1'b0}};
|
756 |
|
|
mt1_write_address <= 32'd0;
|
757 |
|
|
mt1_write_data <= {4{8'h00}};
|
758 |
|
|
mt1_read_req <= 1'b0;
|
759 |
|
|
mt1_read_byte <= {4{1'b0}};
|
760 |
|
|
mt1_read_address <= 32'd0;
|
761 |
|
|
end
|
762 |
|
|
else begin
|
763 |
|
|
mt1_write_req <= wbif_write_req;
|
764 |
|
|
mt1_write_byte <= wbif_write_byte;
|
765 |
|
|
mt1_write_address <= wbif_write_address;
|
766 |
|
|
mt1_write_data <= wbif_write_data;
|
767 |
|
|
mt1_read_req <= wbif_read_req;
|
768 |
|
|
mt1_read_byte <= wbif_read_byte;
|
769 |
|
|
mt1_read_address <= wbif_read_address;
|
770 |
|
|
end
|
771 |
|
|
reg mt2_write_req;
|
772 |
|
|
reg [3:0] mt2_write_byte;
|
773 |
|
|
reg [31:0] mt2_write_address;
|
774 |
|
|
reg [31:0] mt2_write_data;
|
775 |
|
|
reg mt2_read_req;
|
776 |
|
|
reg [3:0] mt2_read_byte;
|
777 |
|
|
reg [31:0] mt2_read_address;
|
778 |
|
|
always @(posedge sys_mem_clk or posedge sys_mem_res)
|
779 |
|
|
if (sys_mem_res) begin
|
780 |
|
|
mt2_write_req <= 1'b0;
|
781 |
|
|
mt2_write_byte <= {4{1'b0}};
|
782 |
|
|
mt2_write_address <= 32'd0;
|
783 |
|
|
mt2_write_data <= {4{8'h00}};
|
784 |
|
|
mt2_read_req <= 1'b0;
|
785 |
|
|
mt2_read_byte <= {4{1'b0}};
|
786 |
|
|
mt2_read_address <= 32'd0;
|
787 |
|
|
end
|
788 |
|
|
else begin
|
789 |
|
|
mt2_write_req <= mt1_write_req;
|
790 |
|
|
mt2_write_byte <= mt1_write_byte;
|
791 |
|
|
mt2_write_address <= mt1_write_address;
|
792 |
|
|
mt2_write_data <= mt1_write_data;
|
793 |
|
|
mt2_read_req <= mt1_read_req;
|
794 |
|
|
mt2_read_byte <= mt1_read_byte;
|
795 |
|
|
mt2_read_address <= mt1_read_address;
|
796 |
|
|
end
|
797 |
|
|
|
798 |
|
|
// mem to wb
|
799 |
|
|
//assign wbif_write_ack = mt2_write_ack;
|
800 |
|
|
//assign wbif_read_ack = mt2_read_ack;
|
801 |
|
|
always @(posedge sys_wb_clk or posedge sys_wb_res)
|
802 |
|
|
if (sys_wb_res) begin
|
803 |
|
|
wbif_write_ack <= 1'b0;
|
804 |
|
|
wbif_read_ack <= 1'b0;
|
805 |
|
|
end
|
806 |
|
|
else begin
|
807 |
|
|
wbif_write_ack <= mt2_write_ack; // can not load xxxxx, so must +1delay
|
808 |
|
|
wbif_read_ack <= mt2_read_ack; // can not load xxxxx, so must +1delay
|
809 |
|
|
end
|
810 |
|
|
assign wbif_read_data = mt2_read_data;
|
811 |
|
|
|
812 |
|
|
// wb to mem
|
813 |
|
|
//assign core_write_req = mt2_write_req;
|
814 |
|
|
//assign core_read_req = mt2_read_req;
|
815 |
|
|
always @(posedge sys_mem_clk or posedge sys_mem_res)
|
816 |
|
|
if (sys_mem_res) begin
|
817 |
|
|
core_write_req <= 1'b0;
|
818 |
|
|
core_read_req <= 1'b0;
|
819 |
|
|
end
|
820 |
|
|
else begin
|
821 |
|
|
core_write_req <= mt2_write_req; // can not load xxxxx, so must +1delay
|
822 |
|
|
core_read_req <= mt2_read_req; // can not load xxxxx, so must +1delay
|
823 |
|
|
end
|
824 |
|
|
assign core_write_byte = mt2_write_byte;
|
825 |
|
|
assign core_write_address = mt2_write_address;
|
826 |
|
|
assign core_write_data = mt2_write_data;
|
827 |
|
|
assign core_read_byte = mt2_read_byte;
|
828 |
|
|
assign core_read_address = mt2_read_address;
|
829 |
|
|
|
830 |
|
|
// MEM Clock domain
|
831 |
|
|
tessera_mem_core i_tessera_mem_core (
|
832 |
|
|
.res( sys_mem_res),
|
833 |
|
|
.clk( sys_mem_clk),
|
834 |
|
|
.write_req( core_write_req),
|
835 |
|
|
.write_byte( core_write_byte),
|
836 |
|
|
.write_address( core_write_address),
|
837 |
|
|
.write_data( core_write_data),
|
838 |
|
|
.write_ack( core_write_ack),
|
839 |
|
|
.read_req( core_read_req),
|
840 |
|
|
.read_byte( core_read_byte),
|
841 |
|
|
.read_address( core_read_address),
|
842 |
|
|
.read_data( core_read_data),
|
843 |
|
|
.read_ack( core_read_ack),
|
844 |
|
|
.mem_cs2_n( mem_cs2_n),
|
845 |
|
|
.mem_cs2_g_n( mem_cs2_g_n),
|
846 |
|
|
.mem_cs2_dir( mem_cs2_dir),
|
847 |
|
|
.mem_cs2_rstdrv( mem_cs2_rstdrv),
|
848 |
|
|
.mem_cs2_int( mem_cs2_int),
|
849 |
|
|
.mem_cs2_iochrdy( mem_cs2_iochrdy),
|
850 |
|
|
.mem_cs1_n( mem_cs1_n),
|
851 |
|
|
.mem_cs1_rst_n( mem_cs1_rst_n),
|
852 |
|
|
.mem_cs1_rdy( mem_cs1_rdy),
|
853 |
|
|
.mem_cs0_n( mem_cs0_n),
|
854 |
|
|
.mem_we_n( mem_we_n),
|
855 |
|
|
.mem_oe_n( mem_oe_n),
|
856 |
|
|
.mem_a( mem_a),
|
857 |
|
|
.mem_d_o( mem_d_o),
|
858 |
|
|
.mem_d_oe( mem_d_oe),
|
859 |
|
|
.mem_d_i( mem_d_i)
|
860 |
|
|
);
|
861 |
|
|
|
862 |
|
|
endmodule
|
863 |
|
|
|