| 1 |
2 |
fukuchi |
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| 2 |
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`timescale 1ps/1ps
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| 3 |
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| 4 |
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// {cke,cs_n,ras_n,cas_n,we_n}
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| 5 |
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`define COMMAND_RES 5'b01000
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| 6 |
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`define COMMAND_NOP 5'b11000
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| 7 |
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`define COMMAND_DES 5'b10000
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| 8 |
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`define COMMAND_PAL 5'b11101
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| 9 |
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`define COMMAND_MRS 5'b11111
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| 10 |
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`define COMMAND_REF 5'b11110
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| 11 |
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`define COMMAND_ACT 5'b11100
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| 12 |
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`define COMMAND_WRI 5'b11011
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| 13 |
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`define COMMAND_REA 5'b11010
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| 14 |
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| 15 |
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// state
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| 16 |
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`define S0 'd0
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| 17 |
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`define S1 'd1
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| 18 |
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`define S2 'd2
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| 19 |
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`define S3 'd3
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| 20 |
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`define S4 'd4
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| 21 |
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`define S5 'd5
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| 22 |
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`define S6 'd6
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| 23 |
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`define S7 'd7
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| 24 |
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`define S8 'd8
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| 25 |
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`define S9 'd9
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| 26 |
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`define S10 'd10
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`define S11 'd11
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| 28 |
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`define S12 'd12
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| 29 |
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`define S13 'd13
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| 30 |
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`define S14 'd14
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| 31 |
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`define S15 'd15
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| 33 |
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module tessera_sdram_ctrl (
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| 34 |
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res,
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| 35 |
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clk,
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| 36 |
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init_req,
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| 37 |
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init_enter,
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| 38 |
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init_exit,
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| 39 |
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refresh_req,
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| 40 |
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refresh_enter,
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| 41 |
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refresh_exit,
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| 42 |
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write_req,
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| 43 |
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write_enter,
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| 44 |
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write_valid,
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| 45 |
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write_exit,
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| 46 |
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write_address,
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| 47 |
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read_req,
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| 48 |
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read_enter,
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| 49 |
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read_valid,
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| 50 |
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read_exit,
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| 51 |
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read_address,
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| 52 |
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dma_req,
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| 53 |
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dma_enter,
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| 54 |
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dma_valid,
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| 55 |
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dma_exit,
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| 56 |
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dma_address,
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| 57 |
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ctrl_cmd,
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| 58 |
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ctrl_cs,
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| 59 |
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ctrl_ba,
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| 60 |
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ctrl_a,
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| 61 |
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option
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| 62 |
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);
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| 63 |
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input res;
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| 64 |
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input clk;
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| 65 |
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input init_req;
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| 66 |
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output init_enter;
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| 67 |
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output init_exit;
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| 68 |
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input refresh_req;
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| 69 |
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output refresh_enter;
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| 70 |
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output refresh_exit;
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| 71 |
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input write_req;
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| 72 |
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output write_enter;
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| 73 |
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output write_valid;
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| 74 |
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output write_exit;
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| 75 |
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input [31:0] write_address;
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| 76 |
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input read_req;
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| 77 |
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output read_enter;
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| 78 |
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output read_valid;
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| 79 |
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output read_exit;
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| 80 |
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input [31:0] read_address;
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| 81 |
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input dma_req;
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| 82 |
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output dma_enter;
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| 83 |
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output dma_valid;
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| 84 |
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output dma_exit;
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| 85 |
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input [31:0] dma_address;
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| 86 |
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output [4:0] ctrl_cmd;
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| 87 |
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output [1:0] ctrl_cs;
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| 88 |
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output [1:0] ctrl_ba;
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| 89 |
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output [12:0] ctrl_a;
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| 90 |
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input option;
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| 91 |
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| 92 |
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//
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| 93 |
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// address
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| 94 |
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//
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| 95 |
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wire [31:0] next_wri_adr;
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| 96 |
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wire [31:0] next_rea_adr;
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| 97 |
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wire [31:0] next_dma_adr;
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| 98 |
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//
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| 99 |
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wire [11:0] next_wri_adr_col;
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| 100 |
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wire [11:0] next_rea_adr_col;
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| 101 |
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wire [11:0] next_dma_adr_col;
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| 102 |
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//
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| 103 |
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wire [12:0] next_wri_adr_row;
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| 104 |
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wire [12:0] next_rea_adr_row;
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| 105 |
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wire [12:0] next_dma_adr_row;
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| 106 |
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//
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| 107 |
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wire [1:0] next_wri_ba;
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| 108 |
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wire [1:0] next_rea_ba;
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| 109 |
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wire [1:0] next_dma_ba;
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| 110 |
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//
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| 111 |
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wire [1:0] next_wri_cs;
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| 112 |
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wire [1:0] next_rea_cs;
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| 113 |
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wire [1:0] next_dma_cs;
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| 114 |
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//
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| 115 |
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//assign next_wri_adr = {8'h00,write_address[23:0]}; // limit,so wishbone arbiter is pass_through uper bit
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| 116 |
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//assign next_rea_adr = {8'h00, read_address[23:0]}; // limit,so wishbone arbiter is pass_through uper bit
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| 117 |
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//assign next_dma_adr = {8'h00, dma_address[23:0]}; // limit,so wishbone arbiter is pass_through uper bit
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| 118 |
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| 119 |
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reg pre_option;
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| 120 |
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always @(posedge clk) pre_option <= option;
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| 121 |
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assign next_wri_adr = {7'h00,pre_option,write_address[23:0]}; // limit,so wishbone arbiter is pass_through uper bit
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| 122 |
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assign next_rea_adr = {7'h00,pre_option,read_address[23:0]}; // limit,so wishbone arbiter is pass_through uper bit
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| 123 |
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assign next_dma_adr = {7'h00,pre_option,dma_address[23:0]}; // limit,so wishbone arbiter is pass_through uper bit
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| 124 |
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| 125 |
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| 126 |
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// 64MBit: x16 SDRAM
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| 127 |
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// 12bit(A12-A11,A9-A0) ->col 8it(3bit not use)
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| 128 |
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// 13bit(A12-A0) ->row 12bit(1bit not use)
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| 129 |
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// 2bit ->ba
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| 130 |
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// 2bit ->cs
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| 131 |
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// assign next_wri_adr_col = {4'b0000,next_wri_adr[8:2],1'b0};
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| 132 |
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// assign next_rea_adr_col = {4'b0000,next_rea_adr[8:2],1'b0};
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| 133 |
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// assign next_dma_adr_col = {4'b0000,next_dma_adr[8:2],1'b0};
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| 134 |
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// //
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| 135 |
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// assign next_wri_adr_row = {1'b0,next_wri_adr[20:9]};
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| 136 |
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// assign next_rea_adr_row = {1'b0,next_rea_adr[20:9]};
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| 137 |
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// assign next_dma_adr_row = {1'b0,next_dma_adr[20:9]};
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| 138 |
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// //
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| 139 |
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// assign next_wri_ba = next_wri_adr[22:21];
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| 140 |
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// assign next_rea_ba = next_rea_adr[22:21];
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| 141 |
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// assign next_dma_ba = next_dma_adr[22:21];
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| 142 |
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// //
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| 143 |
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// assign next_wri_cs = {next_wri_adr[23],!next_wri_adr[23]};
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| 144 |
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// assign next_rea_cs = {next_rea_adr[23],!next_rea_adr[23]};
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| 145 |
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// assign next_dma_cs = {next_dma_adr[23],!next_dma_adr[23]};
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| 146 |
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| 147 |
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| 148 |
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// 128MBit: x16 SDRAM
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| 149 |
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// 12bit(A12-A11,A9-A0) ->col 9it(3bit not use)
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| 150 |
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// 13bit(A12-A0) ->row 12bit(1bit not use)
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| 151 |
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// 2bit ->ba
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| 152 |
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// 2bit ->cs
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| 153 |
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assign next_wri_adr_col = {3'b000,next_wri_adr[9:2],1'b0};
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| 154 |
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assign next_rea_adr_col = {3'b000,next_rea_adr[9:2],1'b0};
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| 155 |
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assign next_dma_adr_col = {3'b000,next_dma_adr[9:2],1'b0};
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| 156 |
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//
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| 157 |
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assign next_wri_adr_row = {1'b0,next_wri_adr[21:10]};
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| 158 |
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assign next_rea_adr_row = {1'b0,next_rea_adr[21:10]};
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| 159 |
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assign next_dma_adr_row = {1'b0,next_dma_adr[21:10]};
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| 160 |
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//
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| 161 |
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assign next_wri_ba = next_wri_adr[23:22];
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| 162 |
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assign next_rea_ba = next_rea_adr[23:22];
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| 163 |
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assign next_dma_ba = next_dma_adr[23:22];
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| 164 |
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//
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| 165 |
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assign next_wri_cs = {next_wri_adr[24],!next_wri_adr[24]};
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| 166 |
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assign next_rea_cs = {next_rea_adr[24],!next_rea_adr[24]};
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| 167 |
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assign next_dma_cs = {next_dma_adr[24],!next_dma_adr[24]};
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| 168 |
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| 169 |
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// 256MBit: x16 SDRAM
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| 170 |
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// 12bit(A12-A11,A9-A0) ->col 9it(3bit not use)
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| 171 |
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// 13bit(A12-A0) ->row 13bit
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| 172 |
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// 2bit ->ba
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| 173 |
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// 2bit ->cs
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| 174 |
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// assign next_wri_adr_col = {3'b000,next_wri_adr[9:2],1'b0};
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| 175 |
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// assign next_rea_adr_col = {3'b000,next_rea_adr[9:2],1'b0};
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| 176 |
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// assign next_dma_adr_col = {3'b000,next_dma_adr[9:2],1'b0};
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| 177 |
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// //
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| 178 |
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// assign next_wri_adr_row = next_wri_adr[22:10];
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| 179 |
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// assign next_rea_adr_row = next_rea_adr[22:10];
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| 180 |
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// assign next_dma_adr_row = next_dma_adr[22:10];
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| 181 |
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// //
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| 182 |
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// assign next_wri_ba = next_wri_adr[24:23];
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| 183 |
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// assign next_rea_ba = next_rea_adr[24:23];
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| 184 |
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// assign next_dma_ba = next_dma_adr[24:23];
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| 185 |
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// //
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| 186 |
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// assign next_wri_cs = {next_wri_adr[25],!next_wri_adr[25]};
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| 187 |
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// assign next_rea_cs = {next_rea_adr[25],!next_rea_adr[25]};
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| 188 |
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// assign next_dma_cs = {next_dma_adr[25],!next_dma_adr[25]};
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| 189 |
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| 190 |
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//
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| 191 |
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// gnt execute
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| 192 |
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//
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| 193 |
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wire init_eve;
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| 194 |
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wire write_eve;
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| 195 |
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wire dma_eve;
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| 196 |
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wire refresh_eve;
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| 197 |
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wire read_eve;
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| 198 |
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wire [4:0] next_execute;
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| 199 |
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reg [4:0] gnt_execute;
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| 200 |
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wire init_syn;
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| 201 |
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wire refresh_syn;
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| 202 |
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wire dma_syn;
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| 203 |
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wire write_syn;
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| 204 |
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wire read_syn;
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| 205 |
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wire init_fin;
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| 206 |
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wire refresh_fin;
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| 207 |
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wire dma_fin;
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| 208 |
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wire write_fin;
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| 209 |
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wire read_fin;
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| 210 |
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//
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| 211 |
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// initilize(0)
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| 212 |
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//
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| 213 |
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reg [4:0] ini_cmd;
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| 214 |
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reg [1:0] ini_cs;
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| 215 |
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reg [1:0] ini_ba;
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| 216 |
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reg [12:0] ini_adr;
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| 217 |
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reg [3:0] ini_sta;
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| 218 |
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reg [3:0] ini_sub;
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| 219 |
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reg timer_enable;
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| 220 |
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reg [15:0] timer;
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| 221 |
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reg timer_expire;
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| 222 |
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//
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| 223 |
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// refresh(1)
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| 224 |
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//
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| 225 |
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reg [4:0] ref_cmd;
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| 226 |
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reg [1:0] ref_cs;
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| 227 |
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reg [1:0] ref_ba;
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| 228 |
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reg [12:0] ref_adr;
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| 229 |
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reg [3:0] ref_sta;
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| 230 |
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//
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| 231 |
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// dma(2)
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| 232 |
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//
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| 233 |
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reg [4:0] dma_cmd;
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| 234 |
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reg [1:0] dma_cs;
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| 235 |
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reg [1:0] dma_ba;
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| 236 |
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reg [12:0] dma_adr;
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| 237 |
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reg [3:0] dma_sta;
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| 238 |
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reg [3:0] dma_sub;
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| 239 |
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reg dma_val;
|
| 240 |
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//
|
| 241 |
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// write(3)
|
| 242 |
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//
|
| 243 |
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reg [4:0] wri_cmd;
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| 244 |
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reg [1:0] wri_cs;
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| 245 |
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reg [1:0] wri_ba;
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| 246 |
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reg [12:0] wri_adr;
|
| 247 |
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reg [3:0] wri_sta;
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| 248 |
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reg [3:0] wri_sub;
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| 249 |
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reg wri_val;
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| 250 |
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//
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| 251 |
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// read(4)
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| 252 |
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//
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| 253 |
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reg [4:0] rea_cmd;
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| 254 |
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reg [1:0] rea_cs;
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| 255 |
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reg [1:0] rea_ba;
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| 256 |
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reg [12:0] rea_adr;
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| 257 |
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reg [3:0] rea_sta;
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| 258 |
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reg [3:0] rea_sub;
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| 259 |
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reg rea_val;
|
| 260 |
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//
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| 261 |
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// output signal
|
| 262 |
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//
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| 263 |
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reg init_enter;
|
| 264 |
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reg refresh_enter;
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| 265 |
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reg dma_enter;
|
| 266 |
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reg write_enter;
|
| 267 |
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reg read_enter;
|
| 268 |
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//
|
| 269 |
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reg init_exit;
|
| 270 |
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reg refresh_exit;
|
| 271 |
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reg dma_exit;
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| 272 |
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reg write_exit;
|
| 273 |
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reg read_exit;
|
| 274 |
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//
|
| 275 |
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// bus arbitor
|
| 276 |
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//
|
| 277 |
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//
|
| 278 |
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// external bus fast release
|
| 279 |
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//
|
| 280 |
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assign init_eve = init_req && !( init_exit|| init_fin);
|
| 281 |
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assign write_eve = write_req && !( write_exit|| write_fin);
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| 282 |
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assign dma_eve = dma_req && !( dma_exit|| dma_fin);
|
| 283 |
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assign refresh_eve = refresh_req && !(refresh_exit||refresh_fin);
|
| 284 |
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assign read_eve = read_req && !( read_exit|| read_fin);
|
| 285 |
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assign next_execute = {
|
| 286 |
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!(init_eve||refresh_eve||dma_eve||write_eve) && read_eve, // low priority
|
| 287 |
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!(init_eve||refresh_eve||dma_eve) && write_eve,
|
| 288 |
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!(init_eve||refresh_eve) && dma_eve,
|
| 289 |
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!(init_eve) && refresh_eve,
|
| 290 |
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init_eve // high priority
|
| 291 |
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};
|
| 292 |
|
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always @(posedge clk or posedge res)
|
| 293 |
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if (res) gnt_execute <= 5'b00000;
|
| 294 |
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else if (
|
| 295 |
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!(
|
| 296 |
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|(gnt_execute[4:0]&{read_eve,write_eve,dma_eve,refresh_eve,init_eve})
|
| 297 |
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)
|
| 298 |
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) gnt_execute <= next_execute;
|
| 299 |
|
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//
|
| 300 |
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// external bus slow release
|
| 301 |
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//
|
| 302 |
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//assign next_execute = {
|
| 303 |
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// !(init_req||refresh_req||dma_req||write_req) && read_req, // low priority
|
| 304 |
|
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// !(init_req||refresh_req||dma_req) && write_req,
|
| 305 |
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// !(init_req||refresh_req) && dma_req,
|
| 306 |
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// !(init_req) && refresh_req,
|
| 307 |
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// init_req // high priority
|
| 308 |
|
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//};
|
| 309 |
|
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//always @(posedge clk or posedge res)
|
| 310 |
|
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// if (res) gnt_execute <= 5'b00000;
|
| 311 |
|
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// else if (
|
| 312 |
|
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// !(
|
| 313 |
|
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// |(gnt_execute[4:0]&{read_req,write_req,dma_req,refresh_req,init_req})
|
| 314 |
|
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// )
|
| 315 |
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// ) gnt_execute <= next_execute;
|
| 316 |
|
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//
|
| 317 |
|
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// output signal
|
| 318 |
|
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//
|
| 319 |
|
|
assign init_syn = (gnt_execute[0]&&(ini_sta==`S0));
|
| 320 |
|
|
assign refresh_syn = (gnt_execute[1]&&(ref_sta==`S0));
|
| 321 |
|
|
assign dma_syn = (gnt_execute[2]&&(dma_sta==`S0));
|
| 322 |
|
|
assign write_syn = (gnt_execute[3]&&(wri_sta==`S0));
|
| 323 |
|
|
assign read_syn = (gnt_execute[4]&&(rea_sta==`S0));
|
| 324 |
|
|
|
| 325 |
|
|
assign init_fin = (gnt_execute[0]&&(ini_sta==`S15));
|
| 326 |
|
|
assign refresh_fin = (gnt_execute[1]&&(ref_sta==`S6));
|
| 327 |
|
|
assign dma_fin = (gnt_execute[2]&&(dma_sta==`S6));
|
| 328 |
|
|
assign write_fin = (gnt_execute[3]&&(wri_sta==`S6));
|
| 329 |
|
|
assign read_fin = (gnt_execute[4]&&(rea_sta==`S6));
|
| 330 |
|
|
|
| 331 |
|
|
always @(posedge clk or posedge res)
|
| 332 |
|
|
if (res) begin
|
| 333 |
|
|
init_enter <= 1'b0;
|
| 334 |
|
|
refresh_enter <= 1'b0;
|
| 335 |
|
|
dma_enter <= 1'b0;
|
| 336 |
|
|
write_enter <= 1'b0;
|
| 337 |
|
|
read_enter <= 1'b0;
|
| 338 |
|
|
//
|
| 339 |
|
|
init_exit <= 1'b0;
|
| 340 |
|
|
refresh_exit <= 1'b0;
|
| 341 |
|
|
dma_exit <= 1'b0;
|
| 342 |
|
|
write_exit <= 1'b0;
|
| 343 |
|
|
read_exit <= 1'b0;
|
| 344 |
|
|
end
|
| 345 |
|
|
else begin
|
| 346 |
|
|
init_enter <= init_syn;
|
| 347 |
|
|
refresh_enter <= refresh_syn;
|
| 348 |
|
|
dma_enter <= dma_syn;
|
| 349 |
|
|
write_enter <= write_syn;
|
| 350 |
|
|
read_enter <= read_syn;
|
| 351 |
|
|
//
|
| 352 |
|
|
//init_exit <= init_fin; //external bus slow release
|
| 353 |
|
|
//refresh_exit <= refresh_fin; //external bus slow release
|
| 354 |
|
|
//dma_exit <= dma_fin; //external bus slow release
|
| 355 |
|
|
//write_exit <= write_fin; //external bus slow release
|
| 356 |
|
|
//read_exit <= read_fin; //external bus slow release
|
| 357 |
|
|
init_exit <= (! init_req) ? 1'b0: ( init_fin) ? 1'b1: init_exit; //external bus fast release
|
| 358 |
|
|
refresh_exit <= (!refresh_req) ? 1'b0: (refresh_fin) ? 1'b1: refresh_exit; //external bus fast release
|
| 359 |
|
|
dma_exit <= (! dma_req) ? 1'b0: ( dma_fin) ? 1'b1: dma_exit; //external bus fast release
|
| 360 |
|
|
write_exit <= (! write_req) ? 1'b0: ( write_fin) ? 1'b1: write_exit; //external bus fast release
|
| 361 |
|
|
read_exit <= (! read_req) ? 1'b0: ( read_fin) ? 1'b1: read_exit; //external bus fast release
|
| 362 |
|
|
end
|
| 363 |
|
|
assign ctrl_cmd = ini_cmd | ref_cmd | dma_cmd | wri_cmd | rea_cmd;
|
| 364 |
|
|
assign ctrl_cs = ini_cs | ref_cs | dma_cs | wri_cs | rea_cs;
|
| 365 |
|
|
assign ctrl_ba = ini_ba | ref_ba | dma_ba | wri_ba | rea_ba;
|
| 366 |
|
|
assign ctrl_a = ini_adr | ref_adr | dma_adr | wri_adr | rea_adr;
|
| 367 |
|
|
assign dma_valid = dma_val;
|
| 368 |
|
|
assign read_valid = rea_val;
|
| 369 |
|
|
assign write_valid = wri_val;
|
| 370 |
|
|
//
|
| 371 |
|
|
// initilize(0)
|
| 372 |
|
|
//
|
| 373 |
|
|
always @(posedge clk or posedge res)
|
| 374 |
|
|
if (res) timer_enable <= 1'b0;
|
| 375 |
|
|
else timer_enable <= (ini_sta==`S1)||(ini_sta==`S14);
|
| 376 |
|
|
always @(posedge clk or posedge res)
|
| 377 |
|
|
if (res) timer <= 16'd0;
|
| 378 |
|
|
else if (!timer_enable) timer <= 16'd0;
|
| 379 |
|
|
else timer <= timer + 16'd1;
|
| 380 |
|
|
always @(posedge clk or posedge res)
|
| 381 |
|
|
if (res) timer_expire <= 1'b0;
|
| 382 |
|
|
else if (!timer_enable) timer_expire <= 1'b0;
|
| 383 |
|
|
else timer_expire <= (timer==16'd16384);
|
| 384 |
|
|
always @(posedge clk or posedge res)
|
| 385 |
|
|
if (res) begin
|
| 386 |
|
|
ini_cmd <= `COMMAND_RES;
|
| 387 |
|
|
ini_cs <= 2'b11; // all cs
|
| 388 |
|
|
ini_ba <= 2'b00;
|
| 389 |
|
|
ini_adr <= 13'd0;
|
| 390 |
|
|
ini_sta <= `S0;
|
| 391 |
|
|
ini_sub <= `S0;
|
| 392 |
|
|
end
|
| 393 |
|
|
else if (!gnt_execute[0]) begin
|
| 394 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 395 |
|
|
ini_cs <= 2'b00;
|
| 396 |
|
|
ini_ba <= 2'b00;
|
| 397 |
|
|
ini_adr <= 13'd0;
|
| 398 |
|
|
ini_sta <= `S0;
|
| 399 |
|
|
ini_sub <= `S0;
|
| 400 |
|
|
end
|
| 401 |
|
|
else case (ini_sta[3:0])
|
| 402 |
|
|
`S0: begin // power on
|
| 403 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 404 |
|
|
ini_cs <= 2'b11; // all cs
|
| 405 |
|
|
ini_ba <= 2'b00;
|
| 406 |
|
|
ini_adr <= 13'd0;
|
| 407 |
|
|
ini_sta <= ini_sta + 4'd1;
|
| 408 |
|
|
end
|
| 409 |
|
|
`S1: begin
|
| 410 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 411 |
|
|
if (timer_expire) ini_sta <= ini_sta + 4'd1; // wait
|
| 412 |
|
|
end
|
| 413 |
|
|
`S2: begin // init sequence
|
| 414 |
|
|
ini_cmd <= `COMMAND_PAL;
|
| 415 |
|
|
ini_adr[10] <= 1'b1;
|
| 416 |
|
|
ini_sta <= ini_sta + 4'd1;
|
| 417 |
|
|
end
|
| 418 |
|
|
`S3: begin
|
| 419 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 420 |
|
|
//ini_adr[10] <= 1'b0;
|
| 421 |
|
|
ini_sta <= ini_sta + 4'd1;
|
| 422 |
|
|
end
|
| 423 |
|
|
`S4: begin
|
| 424 |
|
|
ini_cmd <= `COMMAND_REF;
|
| 425 |
|
|
ini_sta <= ini_sta + 4'd1;
|
| 426 |
|
|
end
|
| 427 |
|
|
`S5: begin
|
| 428 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 429 |
|
|
ini_sta <= ini_sta + 4'd1;
|
| 430 |
|
|
end
|
| 431 |
|
|
`S6,`S7,`S8: begin
|
| 432 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 433 |
|
|
ini_sta <= ini_sta + 4'd1;
|
| 434 |
|
|
end
|
| 435 |
|
|
`S9: begin
|
| 436 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 437 |
|
|
if (ini_sub==`S7) begin
|
| 438 |
|
|
ini_sub <= `S0;
|
| 439 |
|
|
ini_sta <= ini_sta + 4'd1;
|
| 440 |
|
|
end
|
| 441 |
|
|
else begin
|
| 442 |
|
|
ini_sub <= ini_sub + 3'd1;
|
| 443 |
|
|
ini_sta <= `S4;
|
| 444 |
|
|
end
|
| 445 |
|
|
end
|
| 446 |
|
|
`S10: begin
|
| 447 |
|
|
ini_cmd <= `COMMAND_MRS;
|
| 448 |
|
|
ini_ba <= 2'b00; //Reserved
|
| 449 |
|
|
ini_adr <= {
|
| 450 |
|
|
5'b0_0000, //Reserved
|
| 451 |
|
|
1'b0, //Reserved(0)
|
| 452 |
|
|
//3'b010, //CL(2)
|
| 453 |
|
|
3'b011, //CL(3)
|
| 454 |
|
|
1'b0, //BurstType,
|
| 455 |
|
|
3'b001 //RDModeBurstLength
|
| 456 |
|
|
};
|
| 457 |
|
|
ini_sta <= ini_sta + 4'd1;
|
| 458 |
|
|
end
|
| 459 |
|
|
`S11: begin
|
| 460 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 461 |
|
|
ini_sta <= ini_sta + 4'd1;
|
| 462 |
|
|
end
|
| 463 |
|
|
`S12,`S13: begin
|
| 464 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 465 |
|
|
ini_sta <= ini_sta + 4'd1;
|
| 466 |
|
|
end
|
| 467 |
|
|
`S14: begin
|
| 468 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 469 |
|
|
if (timer_expire) ini_sta <= ini_sta + 4'd1; // wait
|
| 470 |
|
|
end
|
| 471 |
|
|
`S15: begin
|
| 472 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 473 |
|
|
ini_sta <= `S0; //external bus fast releas
|
| 474 |
|
|
//if (!init_req) ini_sta <= `S0; //external bus slow release
|
| 475 |
|
|
end
|
| 476 |
|
|
default: begin
|
| 477 |
|
|
ini_cmd <= `COMMAND_DES;
|
| 478 |
|
|
ini_cs <= 2'b00;
|
| 479 |
|
|
ini_ba <= 2'b00;
|
| 480 |
|
|
ini_adr <= 13'd0;
|
| 481 |
|
|
ini_sta <= `S0;
|
| 482 |
|
|
end
|
| 483 |
|
|
endcase
|
| 484 |
|
|
//
|
| 485 |
|
|
// refresh(1)
|
| 486 |
|
|
//
|
| 487 |
|
|
always @(posedge clk or posedge res)
|
| 488 |
|
|
if (res) begin
|
| 489 |
|
|
ref_cmd <= `COMMAND_RES;
|
| 490 |
|
|
ref_cs <= 2'b11; // all cs
|
| 491 |
|
|
ref_ba <= 2'b00;
|
| 492 |
|
|
ref_adr <= 13'd0;
|
| 493 |
|
|
ref_sta <= `S0;
|
| 494 |
|
|
end
|
| 495 |
|
|
else if (!gnt_execute[1]) begin
|
| 496 |
|
|
ref_cmd <= `COMMAND_DES;
|
| 497 |
|
|
ref_cs <= 2'b00;
|
| 498 |
|
|
ref_ba <= 2'b00;
|
| 499 |
|
|
ref_adr <= 13'd0;
|
| 500 |
|
|
ref_sta <= `S0;
|
| 501 |
|
|
end
|
| 502 |
|
|
else case (ref_sta[3:0])
|
| 503 |
|
|
`S0: begin
|
| 504 |
|
|
ref_cmd <= `COMMAND_PAL;
|
| 505 |
|
|
ref_cs <= 2'b11; // all cs
|
| 506 |
|
|
//ref_ba <= 2'b00;
|
| 507 |
|
|
ref_adr <= {2'b00,1'b1,10'b00_0000_0000}; // all bank
|
| 508 |
|
|
ref_sta <= ref_sta + 4'd1;
|
| 509 |
|
|
end
|
| 510 |
|
|
`S1: begin
|
| 511 |
|
|
ref_cmd <= `COMMAND_DES; // tRP
|
| 512 |
|
|
ref_sta <= ref_sta + 4'd1;
|
| 513 |
|
|
end
|
| 514 |
|
|
`S2: begin
|
| 515 |
|
|
ref_cmd <= `COMMAND_REF;
|
| 516 |
|
|
ref_sta <= ref_sta + 4'd1;
|
| 517 |
|
|
end
|
| 518 |
|
|
`S3,`S4,`S5: begin // tRC
|
| 519 |
|
|
ref_cmd <= `COMMAND_DES;
|
| 520 |
|
|
ref_sta <= ref_sta + 4'd1;
|
| 521 |
|
|
end
|
| 522 |
|
|
`S6: begin
|
| 523 |
|
|
ref_cmd <= `COMMAND_DES;
|
| 524 |
|
|
ref_sta <= `S0; //external bus fast releas
|
| 525 |
|
|
//if (!refresh_req) ref_sta <= `S0; //external bus slow release
|
| 526 |
|
|
end
|
| 527 |
|
|
default: begin
|
| 528 |
|
|
ref_cmd <= `COMMAND_DES;
|
| 529 |
|
|
ref_cs <= 2'b00;
|
| 530 |
|
|
ref_ba <= 2'b00;
|
| 531 |
|
|
ref_adr <= 13'd0;
|
| 532 |
|
|
ref_sta <= `S0;
|
| 533 |
|
|
end
|
| 534 |
|
|
endcase
|
| 535 |
|
|
//
|
| 536 |
|
|
// dma(2)
|
| 537 |
|
|
//
|
| 538 |
|
|
always @(posedge clk or posedge res)
|
| 539 |
|
|
if (res) begin
|
| 540 |
|
|
dma_cmd <= `COMMAND_RES;
|
| 541 |
|
|
dma_cs <= 2'b11; // all cs
|
| 542 |
|
|
dma_ba <= 2'b00;
|
| 543 |
|
|
dma_adr <= 13'd0;
|
| 544 |
|
|
dma_sta <= `S0;
|
| 545 |
|
|
dma_sub <= `S0;
|
| 546 |
|
|
dma_val <= 1'b0;
|
| 547 |
|
|
end
|
| 548 |
|
|
else if (!gnt_execute[2]) begin
|
| 549 |
|
|
dma_cmd <= `COMMAND_DES;
|
| 550 |
|
|
dma_cs <= 2'b00;
|
| 551 |
|
|
dma_ba <= 2'b00;
|
| 552 |
|
|
dma_adr <= 13'd0;
|
| 553 |
|
|
dma_sta <= `S0;
|
| 554 |
|
|
dma_sub <= `S0;
|
| 555 |
|
|
dma_val <= 1'b0;
|
| 556 |
|
|
end
|
| 557 |
|
|
else case (dma_sta[3:0])
|
| 558 |
|
|
`S0: begin
|
| 559 |
|
|
dma_cmd <= `COMMAND_ACT;
|
| 560 |
|
|
dma_cs <= next_dma_cs; // only target cs
|
| 561 |
|
|
dma_ba <= next_dma_ba;
|
| 562 |
|
|
dma_adr <= next_dma_adr_row;
|
| 563 |
|
|
dma_sta <= dma_sta + 4'd1;
|
| 564 |
|
|
end
|
| 565 |
|
|
`S1: begin
|
| 566 |
|
|
dma_cmd <= `COMMAND_DES; // tRCD
|
| 567 |
|
|
dma_sta <= dma_sta + 4'd1;
|
| 568 |
|
|
dma_val <= 1'b1;
|
| 569 |
|
|
end
|
| 570 |
|
|
`S2: begin // r1
|
| 571 |
|
|
dma_cmd <= `COMMAND_REA;
|
| 572 |
|
|
//dma_adr <= {next_dma_adr_col[11:10],(dma_sub==`S7),next_dma_adr_col[9:4],dma_sub[2:0],1'b0}; // 8times&auto-precharge(last)
|
| 573 |
|
|
dma_adr <= {next_dma_adr_col[11:10],(dma_sub==`S15),next_dma_adr_col[9:5],dma_sub[3:0],1'b0}; // 16times&auto-precharge(last)
|
| 574 |
|
|
dma_sta <= dma_sta + 4'd1;
|
| 575 |
|
|
end
|
| 576 |
|
|
`S3: begin
|
| 577 |
|
|
dma_cmd <= `COMMAND_DES;
|
| 578 |
|
|
//if (dma_sub==`S7) begin
|
| 579 |
|
|
if (dma_sub==`S15) begin
|
| 580 |
|
|
dma_sub <= `S0;
|
| 581 |
|
|
dma_sta <= dma_sta + 4'd1;
|
| 582 |
|
|
dma_val <= 1'b0;
|
| 583 |
|
|
end
|
| 584 |
|
|
else begin
|
| 585 |
|
|
dma_sub <= dma_sub + 4'd1;
|
| 586 |
|
|
dma_sta <= `S2;
|
| 587 |
|
|
end
|
| 588 |
|
|
end
|
| 589 |
|
|
`S4,`S5: begin
|
| 590 |
|
|
dma_cmd <= `COMMAND_DES;
|
| 591 |
|
|
dma_sta <= dma_sta + 4'd1;
|
| 592 |
|
|
end
|
| 593 |
|
|
`S6: begin
|
| 594 |
|
|
dma_cmd <= `COMMAND_DES;
|
| 595 |
|
|
dma_sta <= `S0; //external bus fast releas
|
| 596 |
|
|
//if (!dma_req) dma_sta <= `S0; //external bus slow release
|
| 597 |
|
|
end
|
| 598 |
|
|
default: begin
|
| 599 |
|
|
dma_cmd <= `COMMAND_DES;
|
| 600 |
|
|
dma_cs <= 2'b00;
|
| 601 |
|
|
dma_ba <= 2'b00;
|
| 602 |
|
|
dma_adr <= 13'd0;
|
| 603 |
|
|
dma_sta <= `S0;
|
| 604 |
|
|
dma_sub <= `S0;
|
| 605 |
|
|
dma_val <= 1'b0;
|
| 606 |
|
|
end
|
| 607 |
|
|
endcase
|
| 608 |
|
|
//
|
| 609 |
|
|
// write(3)
|
| 610 |
|
|
//
|
| 611 |
|
|
always @(posedge clk or posedge res)
|
| 612 |
|
|
if (res) begin
|
| 613 |
|
|
wri_cmd <= `COMMAND_RES;
|
| 614 |
|
|
wri_cs <= 2'b11; // all cs
|
| 615 |
|
|
wri_ba <= 2'b00;
|
| 616 |
|
|
wri_adr <= 13'd0;
|
| 617 |
|
|
wri_sta <= `S0;
|
| 618 |
|
|
wri_sub <= `S0;
|
| 619 |
|
|
wri_val <= 1'b0;
|
| 620 |
|
|
end
|
| 621 |
|
|
else if (!gnt_execute[3]) begin
|
| 622 |
|
|
wri_cmd <= `COMMAND_DES;
|
| 623 |
|
|
wri_cs <= 2'b00;
|
| 624 |
|
|
wri_ba <= 2'b00;
|
| 625 |
|
|
wri_adr <= 13'd0;
|
| 626 |
|
|
wri_sta <= `S0;
|
| 627 |
|
|
wri_sub <= `S0;
|
| 628 |
|
|
wri_val <= 1'b0;
|
| 629 |
|
|
end
|
| 630 |
|
|
else case (wri_sta[3:0])
|
| 631 |
|
|
`S0: begin
|
| 632 |
|
|
wri_cmd <= `COMMAND_ACT;
|
| 633 |
|
|
wri_cs <= next_wri_cs; // only target cs
|
| 634 |
|
|
wri_ba <= next_wri_ba;
|
| 635 |
|
|
wri_adr <= next_wri_adr_row;
|
| 636 |
|
|
wri_sta <= wri_sta + 4'd1;
|
| 637 |
|
|
end
|
| 638 |
|
|
`S1: begin
|
| 639 |
|
|
wri_cmd <= `COMMAND_DES; // tRCD
|
| 640 |
|
|
wri_sta <= wri_sta + 4'd1;
|
| 641 |
|
|
wri_val <= 1'b1;
|
| 642 |
|
|
end
|
| 643 |
|
|
`S2: begin
|
| 644 |
|
|
wri_cmd <= `COMMAND_WRI;
|
| 645 |
|
|
//wri_adr <= {next_wri_adr_col[11:10],1'b1,next_wri_adr_col[9:2],2'b00};
|
| 646 |
|
|
wri_adr <= {next_wri_adr_col[11:10],1'b1,next_wri_adr_col[9:0]};
|
| 647 |
|
|
wri_sta <= wri_sta + 4'd1;
|
| 648 |
|
|
end
|
| 649 |
|
|
`S3: begin
|
| 650 |
|
|
wri_cmd <= `COMMAND_DES;
|
| 651 |
|
|
if (wri_sub==`S0) begin
|
| 652 |
|
|
wri_sub <= `S0;
|
| 653 |
|
|
wri_sta <= wri_sta + 4'd1;
|
| 654 |
|
|
wri_val <= 1'b0;
|
| 655 |
|
|
end
|
| 656 |
|
|
else begin
|
| 657 |
|
|
wri_sub <= wri_sub + 4'd1;
|
| 658 |
|
|
wri_sta <= `S2;
|
| 659 |
|
|
end
|
| 660 |
|
|
end
|
| 661 |
|
|
`S4,`S5: begin
|
| 662 |
|
|
wri_cmd <= `COMMAND_DES;
|
| 663 |
|
|
wri_sta <= wri_sta + 4'd1;
|
| 664 |
|
|
end
|
| 665 |
|
|
`S6: begin
|
| 666 |
|
|
wri_cmd <= `COMMAND_DES;
|
| 667 |
|
|
wri_sta <= `S0; //external bus fast releas
|
| 668 |
|
|
//if (!write_req) wri_sta <= `S0; //external bus slow release
|
| 669 |
|
|
end
|
| 670 |
|
|
default: begin
|
| 671 |
|
|
wri_cmd <= `COMMAND_DES;
|
| 672 |
|
|
wri_cs <= 2'b00;
|
| 673 |
|
|
wri_ba <= 2'b00;
|
| 674 |
|
|
wri_adr <= 13'd0;
|
| 675 |
|
|
wri_sta <= `S0;
|
| 676 |
|
|
wri_sub <= `S0;
|
| 677 |
|
|
wri_val <= 1'b0;
|
| 678 |
|
|
end
|
| 679 |
|
|
endcase
|
| 680 |
|
|
//
|
| 681 |
|
|
// read(4)
|
| 682 |
|
|
//
|
| 683 |
|
|
always @(posedge clk or posedge res)
|
| 684 |
|
|
if (res) begin
|
| 685 |
|
|
rea_cmd <= `COMMAND_RES;
|
| 686 |
|
|
rea_cs <= 2'b11; // all cs
|
| 687 |
|
|
rea_ba <= 2'b00;
|
| 688 |
|
|
rea_adr <= 13'd0;
|
| 689 |
|
|
rea_sta <= `S0;
|
| 690 |
|
|
rea_sub <= `S0;
|
| 691 |
|
|
rea_val <= 1'b0;
|
| 692 |
|
|
end
|
| 693 |
|
|
else if (!gnt_execute[4]) begin
|
| 694 |
|
|
rea_cmd <= `COMMAND_DES;
|
| 695 |
|
|
rea_cs <= 2'b00;
|
| 696 |
|
|
rea_ba <= 2'b00;
|
| 697 |
|
|
rea_adr <= 13'd0;
|
| 698 |
|
|
rea_sta <= `S0;
|
| 699 |
|
|
rea_sub <= `S0;
|
| 700 |
|
|
rea_val <= 1'b0;
|
| 701 |
|
|
end
|
| 702 |
|
|
else case (rea_sta[3:0])
|
| 703 |
|
|
`S0: begin
|
| 704 |
|
|
rea_cmd <= `COMMAND_ACT;
|
| 705 |
|
|
rea_cs <= next_rea_cs; // only target cs
|
| 706 |
|
|
rea_ba <= next_rea_ba;
|
| 707 |
|
|
rea_adr <= next_rea_adr_row;
|
| 708 |
|
|
rea_sta <= rea_sta + 4'd1;
|
| 709 |
|
|
end
|
| 710 |
|
|
`S1: begin
|
| 711 |
|
|
rea_cmd <= `COMMAND_DES; // tRCD
|
| 712 |
|
|
rea_sta <= rea_sta + 4'd1;
|
| 713 |
|
|
rea_val <= 1'b1;
|
| 714 |
|
|
end
|
| 715 |
|
|
`S2: begin
|
| 716 |
|
|
rea_cmd <= `COMMAND_REA;
|
| 717 |
|
|
//rea_adr <= {next_rea_adr_col[11:10],1'b1,next_rea_adr_col[9:2],2'b00};
|
| 718 |
|
|
rea_adr <= {next_rea_adr_col[11:10],1'b1,next_rea_adr_col[9:0]};
|
| 719 |
|
|
rea_sta <= rea_sta + 4'd1;
|
| 720 |
|
|
end
|
| 721 |
|
|
`S3: begin
|
| 722 |
|
|
rea_cmd <= `COMMAND_DES;
|
| 723 |
|
|
if (rea_sub==`S0) begin
|
| 724 |
|
|
rea_sub <= `S0;
|
| 725 |
|
|
rea_sta <= rea_sta + 4'd1;
|
| 726 |
|
|
rea_val <= 1'b0;
|
| 727 |
|
|
end
|
| 728 |
|
|
else begin
|
| 729 |
|
|
rea_sub <= rea_sub + 4'd1;
|
| 730 |
|
|
rea_sta <= `S2;
|
| 731 |
|
|
end
|
| 732 |
|
|
end
|
| 733 |
|
|
`S4,`S5: begin
|
| 734 |
|
|
rea_cmd <= `COMMAND_DES;
|
| 735 |
|
|
rea_sta <= rea_sta + 4'd1;
|
| 736 |
|
|
end
|
| 737 |
|
|
`S6: begin
|
| 738 |
|
|
rea_cmd <= `COMMAND_DES;
|
| 739 |
|
|
rea_sta <= `S0; //external bus fast release
|
| 740 |
|
|
//if (!read_req) rea_sta <= `S0; //external bus slow release
|
| 741 |
|
|
end
|
| 742 |
|
|
default: begin
|
| 743 |
|
|
rea_cmd <= `COMMAND_DES;
|
| 744 |
|
|
rea_cs <= 2'b00;
|
| 745 |
|
|
rea_ba <= 2'b00;
|
| 746 |
|
|
rea_adr <= 13'd0;
|
| 747 |
|
|
rea_sta <= `S0;
|
| 748 |
|
|
rea_sub <= `S0;
|
| 749 |
|
|
rea_val <= 1'b0;
|
| 750 |
|
|
end
|
| 751 |
|
|
endcase
|
| 752 |
|
|
|
| 753 |
|
|
endmodule
|
| 754 |
|
|
|
| 755 |
|
|
module tessera_sdram_core (
|
| 756 |
|
|
res,
|
| 757 |
|
|
clk,
|
| 758 |
|
|
write_req,
|
| 759 |
|
|
write_byte,
|
| 760 |
|
|
write_address,
|
| 761 |
|
|
write_data,
|
| 762 |
|
|
write_ack,
|
| 763 |
|
|
read_req,
|
| 764 |
|
|
read_byte,
|
| 765 |
|
|
read_address,
|
| 766 |
|
|
read_data,
|
| 767 |
|
|
read_ack,
|
| 768 |
|
|
dma_req,
|
| 769 |
|
|
dma_address,
|
| 770 |
|
|
dma_ack,
|
| 771 |
|
|
dma_exist,
|
| 772 |
|
|
dma_data,
|
| 773 |
|
|
sdram_clk,
|
| 774 |
|
|
sdram_cke,
|
| 775 |
|
|
sdram_cs_n,
|
| 776 |
|
|
sdram_ras_n,
|
| 777 |
|
|
sdram_cas_n,
|
| 778 |
|
|
sdram_we_n,
|
| 779 |
|
|
sdram_dqm,
|
| 780 |
|
|
sdram_ba,
|
| 781 |
|
|
sdram_adr,
|
| 782 |
|
|
sdram_d_i,
|
| 783 |
|
|
sdram_d_oe,
|
| 784 |
|
|
sdram_d_o,
|
| 785 |
|
|
//
|
| 786 |
|
|
option
|
| 787 |
|
|
);
|
| 788 |
|
|
input res;
|
| 789 |
|
|
input clk;
|
| 790 |
|
|
input write_req;
|
| 791 |
|
|
input [3:0] write_byte;
|
| 792 |
|
|
input [31:0] write_address;
|
| 793 |
|
|
input [31:0] write_data;
|
| 794 |
|
|
output write_ack;
|
| 795 |
|
|
input read_req;
|
| 796 |
|
|
input [3:0] read_byte;
|
| 797 |
|
|
input [31:0] read_address;
|
| 798 |
|
|
output [31:0] read_data;
|
| 799 |
|
|
output read_ack;
|
| 800 |
|
|
input dma_req;
|
| 801 |
|
|
input [31:0] dma_address;
|
| 802 |
|
|
output dma_ack;
|
| 803 |
|
|
output dma_exist;
|
| 804 |
|
|
output [15:0] dma_data;
|
| 805 |
|
|
output sdram_clk;
|
| 806 |
|
|
output sdram_cke;
|
| 807 |
|
|
output [1:0] sdram_cs_n;
|
| 808 |
|
|
output sdram_ras_n;
|
| 809 |
|
|
output sdram_cas_n;
|
| 810 |
|
|
output sdram_we_n;
|
| 811 |
|
|
output [1:0] sdram_dqm;
|
| 812 |
|
|
output [1:0] sdram_ba;
|
| 813 |
|
|
output [12:0] sdram_adr;
|
| 814 |
|
|
input [15:0] sdram_d_i;
|
| 815 |
|
|
output [15:0] sdram_d_oe;
|
| 816 |
|
|
output [15:0] sdram_d_o;
|
| 817 |
|
|
input option;
|
| 818 |
|
|
|
| 819 |
|
|
// init requester
|
| 820 |
|
|
reg init_req;
|
| 821 |
|
|
wire init_exit;
|
| 822 |
|
|
always @(posedge clk or posedge res)
|
| 823 |
|
|
if (res) init_req <= 1'b1;
|
| 824 |
|
|
else if (init_exit) init_req <= 1'b0;
|
| 825 |
|
|
|
| 826 |
|
|
// refresh requester
|
| 827 |
|
|
reg [7:0] refresh_timer;
|
| 828 |
|
|
wire refresh_timer_expire;
|
| 829 |
|
|
reg refresh_req;
|
| 830 |
|
|
wire refresh_exit;
|
| 831 |
|
|
assign refresh_timer_expire = (refresh_timer==8'd255);
|
| 832 |
|
|
//assign refresh_timer_expire = (refresh_timer==8'd127);
|
| 833 |
|
|
//assign refresh_timer_expire = (refresh_timer==8'd64);
|
| 834 |
|
|
|
| 835 |
|
|
always @(posedge clk or posedge res)
|
| 836 |
|
|
if (res) refresh_timer <= 8'd0;
|
| 837 |
|
|
else if (refresh_timer_expire) refresh_timer <= 8'd0;
|
| 838 |
|
|
else refresh_timer <= refresh_timer + 8'd1;
|
| 839 |
|
|
always @(posedge clk or posedge res)
|
| 840 |
|
|
if (res) refresh_req <= 1'b1;
|
| 841 |
|
|
else if (refresh_exit) refresh_req <= 1'b0;
|
| 842 |
|
|
else if (refresh_timer_expire) refresh_req <= 1'b1; // test is 0
|
| 843 |
|
|
|
| 844 |
|
|
// input pre_rgiter(must include IOB)
|
| 845 |
|
|
reg [15:0] ctrl_rd;
|
| 846 |
|
|
always @(posedge clk or posedge res)
|
| 847 |
|
|
if (res) begin
|
| 848 |
|
|
ctrl_rd <= {2{8'h00}};
|
| 849 |
|
|
end
|
| 850 |
|
|
else begin
|
| 851 |
|
|
ctrl_rd <= sdram_d_i;
|
| 852 |
|
|
end
|
| 853 |
|
|
|
| 854 |
|
|
// sdram_ctrl
|
| 855 |
|
|
wire write_enter;
|
| 856 |
|
|
wire write_exit;
|
| 857 |
|
|
wire write_valid;
|
| 858 |
|
|
wire read_enter;
|
| 859 |
|
|
wire read_valid;
|
| 860 |
|
|
wire read_exit;
|
| 861 |
|
|
wire dma_enter;
|
| 862 |
|
|
wire dma_exit;
|
| 863 |
|
|
wire dma_valid;
|
| 864 |
|
|
wire [4:0] ctrl_cmd;
|
| 865 |
|
|
wire [1:0] ctrl_cs;
|
| 866 |
|
|
wire [1:0] ctrl_ba;
|
| 867 |
|
|
wire [12:0] ctrl_a;
|
| 868 |
|
|
tessera_sdram_ctrl i_tessera_sdram_ctrl (
|
| 869 |
|
|
.res( res),
|
| 870 |
|
|
.clk( clk),
|
| 871 |
|
|
.init_req( init_req),
|
| 872 |
|
|
.init_enter( /* not used */),
|
| 873 |
|
|
.init_exit( init_exit),
|
| 874 |
|
|
.refresh_req( refresh_req),
|
| 875 |
|
|
.refresh_enter( /* not used */),
|
| 876 |
|
|
.refresh_exit( refresh_exit),
|
| 877 |
|
|
.write_req( write_req),
|
| 878 |
|
|
.write_enter( write_enter),
|
| 879 |
|
|
.write_valid( /* not used */),
|
| 880 |
|
|
.write_exit( write_exit),
|
| 881 |
|
|
.write_address( write_address),
|
| 882 |
|
|
.read_req( read_req),
|
| 883 |
|
|
.read_enter( read_enter),
|
| 884 |
|
|
.read_valid( read_valid),
|
| 885 |
|
|
.read_exit( read_exit),
|
| 886 |
|
|
.read_address( read_address),
|
| 887 |
|
|
.dma_req( dma_req),
|
| 888 |
|
|
.dma_enter( dma_enter),
|
| 889 |
|
|
.dma_exit( dma_exit),
|
| 890 |
|
|
.dma_valid( dma_valid),
|
| 891 |
|
|
.dma_address( dma_address),
|
| 892 |
|
|
.ctrl_cmd( ctrl_cmd),
|
| 893 |
|
|
.ctrl_cs( ctrl_cs),
|
| 894 |
|
|
.ctrl_ba( ctrl_ba),
|
| 895 |
|
|
.ctrl_a( ctrl_a),
|
| 896 |
|
|
.option( option)
|
| 897 |
|
|
);
|
| 898 |
|
|
|
| 899 |
|
|
reg [3:0] read_exit_z;
|
| 900 |
|
|
always @(posedge clk or posedge res)
|
| 901 |
|
|
if (res) read_exit_z <= 4'b0000;
|
| 902 |
|
|
else read_exit_z <= {read_exit_z[2:0],read_exit};
|
| 903 |
|
|
//assign read_ack = read_exit_z[2]; // when latency 2 data&ack just
|
| 904 |
|
|
assign read_ack = read_exit_z[3]; // when latency 3 data&ack just
|
| 905 |
|
|
assign write_ack = write_exit; // is ff_signal
|
| 906 |
|
|
assign dma_ack = dma_exit; // is ff_signal
|
| 907 |
|
|
|
| 908 |
|
|
// input valiad signal
|
| 909 |
|
|
reg [5:0] dma_valid_z;
|
| 910 |
|
|
reg [5:0] read_valid_z;
|
| 911 |
|
|
always @(posedge clk or posedge res)
|
| 912 |
|
|
if (res) begin
|
| 913 |
|
|
dma_valid_z <= 6'b0_0000;
|
| 914 |
|
|
read_valid_z <= 6'b0_0000;
|
| 915 |
|
|
end
|
| 916 |
|
|
else begin
|
| 917 |
|
|
dma_valid_z <= {dma_valid_z[4:0],dma_valid};
|
| 918 |
|
|
read_valid_z <= {read_valid_z[4:0],read_valid};
|
| 919 |
|
|
end
|
| 920 |
|
|
|
| 921 |
|
|
// enter signals
|
| 922 |
|
|
reg write_enter_z;
|
| 923 |
|
|
reg [8:0] read_enter_z;
|
| 924 |
|
|
reg [8:0] dma_enter_z;
|
| 925 |
|
|
always @(posedge clk or posedge res)
|
| 926 |
|
|
if (res) begin
|
| 927 |
|
|
write_enter_z <= 1'b0;
|
| 928 |
|
|
read_enter_z <= {9{1'b0}};
|
| 929 |
|
|
dma_enter_z <= {9{1'b0}};
|
| 930 |
|
|
end
|
| 931 |
|
|
else begin
|
| 932 |
|
|
write_enter_z <= write_enter;
|
| 933 |
|
|
read_enter_z <= {read_enter_z[7:0],read_enter};
|
| 934 |
|
|
dma_enter_z <= {dma_enter_z[7:0],dma_enter};
|
| 935 |
|
|
end
|
| 936 |
|
|
|
| 937 |
|
|
// WRITE BUFFER(LongAccess)
|
| 938 |
|
|
reg [3:0] write_byte_temp;
|
| 939 |
|
|
reg [31:0] write_data_temp;
|
| 940 |
|
|
always @(posedge clk or posedge res)
|
| 941 |
|
|
if (res) begin
|
| 942 |
|
|
write_byte_temp <= {4{1'b0}};
|
| 943 |
|
|
write_data_temp <= {4{8'h00}};
|
| 944 |
|
|
end
|
| 945 |
|
|
else begin
|
| 946 |
|
|
write_byte_temp <= (write_enter_z) ? write_byte: {write_byte_temp[1:0],2'b00}; // write_dqm is none-latehcy(always)
|
| 947 |
|
|
write_data_temp <= (write_enter_z) ? write_data: {write_data_temp[15:0],16'h00_00};
|
| 948 |
|
|
end
|
| 949 |
|
|
|
| 950 |
|
|
// READ BUFFER(LongAccess)
|
| 951 |
|
|
reg [3:0] read_byte_temp;
|
| 952 |
|
|
reg [31:0] read_data_temp;
|
| 953 |
|
|
always @(posedge clk or posedge res)
|
| 954 |
|
|
if (res) begin
|
| 955 |
|
|
read_byte_temp <= {4{1'b0}};
|
| 956 |
|
|
read_data_temp <= {4{8'h00}};
|
| 957 |
|
|
end
|
| 958 |
|
|
else begin
|
| 959 |
|
|
//read_byte_temp <= (read_enter_z[0]) ? read_byte: {read_byte_temp[1:0],2'b00}; // read_dqm is 2latency
|
| 960 |
|
|
read_byte_temp <= (read_enter_z[1]) ? read_byte: {read_byte_temp[1:0],2'b00}; // read_dqm is 3latency
|
| 961 |
|
|
//read_data_temp <= (read_valid_z[4]) ? {read_data_temp[15:0],ctrl_rd}: read_data_temp; // latch data(2latency)
|
| 962 |
|
|
read_data_temp <= (read_valid_z[5]) ? {read_data_temp[15:0],ctrl_rd}: read_data_temp; // latch data(3latency)
|
| 963 |
|
|
end
|
| 964 |
|
|
assign read_data = read_data_temp;
|
| 965 |
|
|
|
| 966 |
|
|
// DMA BUFFER(8 x LongInt)
|
| 967 |
|
|
reg [63:0] dma_byte_temp;
|
| 968 |
|
|
reg [15:0] dma_data_temp;
|
| 969 |
|
|
reg dma_exist_temp;
|
| 970 |
|
|
always @(posedge clk or posedge res)
|
| 971 |
|
|
if (res) begin
|
| 972 |
|
|
dma_byte_temp <= {64{1'b0}};
|
| 973 |
|
|
dma_data_temp <= {2{8'h00}};
|
| 974 |
|
|
dma_exist_temp <= 1'b0;
|
| 975 |
|
|
end
|
| 976 |
|
|
else begin
|
| 977 |
|
|
//dma_byte_temp <= (dma_enter_z[0]) ? 64'hffff_ffff_ffff_ffff: {dma_byte_temp[61:0],2'b00}; // read_dqm is 2latency
|
| 978 |
|
|
dma_byte_temp <= (dma_enter_z[1]) ? 64'hffff_ffff_ffff_ffff: {dma_byte_temp[61:0],2'b00}; // read_dqm is 3latency
|
| 979 |
|
|
//dma_data_temp <= (dma_valid_z[4]) ? ctrl_rd: dma_data_temp; // latch data(2latency)
|
| 980 |
|
|
//dma_exist_temp <= dma_valid_z[4]; // flag(2latency)
|
| 981 |
|
|
dma_data_temp <= (dma_valid_z[5]) ? ctrl_rd: dma_data_temp; // latch data(3latency)
|
| 982 |
|
|
dma_exist_temp <= dma_valid_z[5]; // flag(3latency)
|
| 983 |
|
|
end
|
| 984 |
|
|
assign dma_exist = dma_exist_temp;
|
| 985 |
|
|
assign dma_data = dma_data_temp;
|
| 986 |
|
|
|
| 987 |
|
|
// output final regiter(must include IOB)
|
| 988 |
|
|
reg sdram_cke;
|
| 989 |
|
|
reg [1:0] sdram_cs_n;
|
| 990 |
|
|
reg sdram_ras_n;
|
| 991 |
|
|
reg sdram_cas_n;
|
| 992 |
|
|
reg sdram_we_n;
|
| 993 |
|
|
reg [1:0] sdram_dqm;
|
| 994 |
|
|
reg [1:0] sdram_ba;
|
| 995 |
|
|
reg [12:0] sdram_adr;
|
| 996 |
|
|
reg [15:0] sdram_d_oe;
|
| 997 |
|
|
reg [15:0] sdram_d_o;
|
| 998 |
|
|
assign sdram_clk = clk;
|
| 999 |
|
|
always @(posedge clk or posedge res)
|
| 1000 |
|
|
if (res) begin
|
| 1001 |
|
|
sdram_cke <= 1'b0;
|
| 1002 |
|
|
sdram_cs_n <= 1'b0;
|
| 1003 |
|
|
sdram_ras_n <= 1'b1;
|
| 1004 |
|
|
sdram_cas_n <= 1'b1;
|
| 1005 |
|
|
sdram_we_n <= 1'b1;
|
| 1006 |
|
|
sdram_dqm <= {2{1'b1}};
|
| 1007 |
|
|
sdram_ba <= 2'b00;
|
| 1008 |
|
|
sdram_adr <= 13'd0;
|
| 1009 |
|
|
sdram_d_oe <= {2{8'h00}};
|
| 1010 |
|
|
sdram_d_o <= {2{8'h00}};
|
| 1011 |
|
|
end
|
| 1012 |
|
|
else begin
|
| 1013 |
|
|
sdram_cke <= ctrl_cmd[4];
|
| 1014 |
|
|
sdram_cs_n <= ~(ctrl_cs&{2{ctrl_cmd[3]}});
|
| 1015 |
|
|
sdram_ras_n <= !ctrl_cmd[2];
|
| 1016 |
|
|
sdram_cas_n <= !ctrl_cmd[1];
|
| 1017 |
|
|
sdram_we_n <= !ctrl_cmd[0];
|
| 1018 |
|
|
sdram_dqm <= ~( {(write_byte_temp[3]||read_byte_temp[3]||dma_byte_temp[63]),(write_byte_temp[2]||read_byte_temp[2]||dma_byte_temp[62])} );
|
| 1019 |
|
|
sdram_ba <= ctrl_ba&{2{ctrl_cmd[3]}};
|
| 1020 |
|
|
sdram_adr <= ctrl_a&{13{ctrl_cmd[3]}};
|
| 1021 |
|
|
sdram_d_oe <= { {8{write_byte_temp[3]}},{8{write_byte_temp[2]}} };
|
| 1022 |
|
|
sdram_d_o <= write_data_temp[31:16];
|
| 1023 |
|
|
end
|
| 1024 |
|
|
endmodule
|
| 1025 |
|
|
|
| 1026 |
|
|
module tessera_sdram_wbif (
|
| 1027 |
|
|
res,
|
| 1028 |
|
|
clk,
|
| 1029 |
|
|
wb_cyc_i,
|
| 1030 |
|
|
wb_stb_i,
|
| 1031 |
|
|
wb_adr_i,
|
| 1032 |
|
|
wb_sel_i,
|
| 1033 |
|
|
wb_we_i,
|
| 1034 |
|
|
wb_dat_i,
|
| 1035 |
|
|
wb_cab_i,
|
| 1036 |
|
|
wb_dat_o,
|
| 1037 |
|
|
wb_ack_o,
|
| 1038 |
|
|
wb_err_o,
|
| 1039 |
|
|
write_req,
|
| 1040 |
|
|
write_byte,
|
| 1041 |
|
|
write_address,
|
| 1042 |
|
|
write_data,
|
| 1043 |
|
|
write_ack,
|
| 1044 |
|
|
read_req,
|
| 1045 |
|
|
read_byte,
|
| 1046 |
|
|
read_address,
|
| 1047 |
|
|
read_data,
|
| 1048 |
|
|
read_ack
|
| 1049 |
|
|
);
|
| 1050 |
|
|
input res;
|
| 1051 |
|
|
input clk;
|
| 1052 |
|
|
input wb_cyc_i;
|
| 1053 |
|
|
input wb_stb_i;
|
| 1054 |
|
|
input [31:0] wb_adr_i;
|
| 1055 |
|
|
input [3:0] wb_sel_i;
|
| 1056 |
|
|
input wb_we_i;
|
| 1057 |
|
|
input [31:0] wb_dat_i;
|
| 1058 |
|
|
input wb_cab_i;
|
| 1059 |
|
|
output [31:0] wb_dat_o;
|
| 1060 |
|
|
output wb_ack_o;
|
| 1061 |
|
|
output wb_err_o;
|
| 1062 |
|
|
output write_req;
|
| 1063 |
|
|
output [3:0] write_byte;
|
| 1064 |
|
|
output [31:0] write_address;
|
| 1065 |
|
|
output [31:0] write_data;
|
| 1066 |
|
|
input write_ack;
|
| 1067 |
|
|
output read_req;
|
| 1068 |
|
|
output [3:0] read_byte;
|
| 1069 |
|
|
output [31:0] read_address;
|
| 1070 |
|
|
input [31:0] read_data;
|
| 1071 |
|
|
input read_ack;
|
| 1072 |
|
|
//
|
| 1073 |
|
|
//
|
| 1074 |
|
|
//
|
| 1075 |
|
|
assign wb_err_o = 1'b0;
|
| 1076 |
|
|
//
|
| 1077 |
|
|
//
|
| 1078 |
|
|
//
|
| 1079 |
|
|
reg write_ack_z;
|
| 1080 |
|
|
reg read_ack_z;
|
| 1081 |
|
|
reg wb_ack;
|
| 1082 |
|
|
always @(posedge clk or posedge res)
|
| 1083 |
|
|
if (res) write_ack_z <= 1'b0;
|
| 1084 |
|
|
else write_ack_z <= write_ack;
|
| 1085 |
|
|
always @(posedge clk or posedge res)
|
| 1086 |
|
|
if (res) read_ack_z <= 1'b0;
|
| 1087 |
|
|
else read_ack_z <= read_ack;
|
| 1088 |
|
|
always @(posedge clk or posedge res)
|
| 1089 |
|
|
if (res) wb_ack <= 1'b0;
|
| 1090 |
|
|
//else wb_ack <= (write_ack_z&&!write_ack)||(read_ack_z&&!read_ack); // release negedge ack(late)
|
| 1091 |
|
|
else wb_ack <= (!write_ack_z&&write_ack)||(!read_ack_z&&read_ack); // release posedge ack(fast)
|
| 1092 |
|
|
assign wb_ack_o = (wb_cyc_i&&wb_stb_i) ? wb_ack: 1'b0;
|
| 1093 |
|
|
//
|
| 1094 |
|
|
//
|
| 1095 |
|
|
//
|
| 1096 |
|
|
reg [31:0] wb_dat;
|
| 1097 |
|
|
always @(posedge clk or posedge res)
|
| 1098 |
|
|
if (res) wb_dat <= {4{8'h00}};
|
| 1099 |
|
|
else wb_dat <= read_data;
|
| 1100 |
|
|
assign wb_dat_o = (wb_cyc_i&&wb_stb_i) ? wb_dat[31:0]: {4{8'h00}};
|
| 1101 |
|
|
//
|
| 1102 |
|
|
//
|
| 1103 |
|
|
//
|
| 1104 |
|
|
reg [3:0] write_byte;
|
| 1105 |
|
|
reg [31:0] write_address;
|
| 1106 |
|
|
reg [31:0] write_data;
|
| 1107 |
|
|
//
|
| 1108 |
|
|
reg [3:0] read_byte;
|
| 1109 |
|
|
reg [31:0] read_address;
|
| 1110 |
|
|
always @(posedge clk or posedge res)
|
| 1111 |
|
|
if (res) begin
|
| 1112 |
|
|
write_byte <= {4{1'b0}};
|
| 1113 |
|
|
write_address <= 32'd0;
|
| 1114 |
|
|
write_data <= {4{8'h00}};
|
| 1115 |
|
|
//
|
| 1116 |
|
|
read_byte <= {4{1'b0}};
|
| 1117 |
|
|
read_address <= 32'd0;
|
| 1118 |
|
|
end
|
| 1119 |
|
|
else begin
|
| 1120 |
|
|
write_byte <= wb_sel_i;
|
| 1121 |
|
|
write_address <= wb_adr_i; // masking controler,{8'd0,wb_adr_i[23:0]};
|
| 1122 |
|
|
write_data <= wb_dat_i;
|
| 1123 |
|
|
//
|
| 1124 |
|
|
read_byte <= wb_sel_i;
|
| 1125 |
|
|
read_address <= wb_adr_i; // masking controler,{8'd0,wb_adr_i[23:0]};
|
| 1126 |
|
|
end
|
| 1127 |
|
|
//
|
| 1128 |
|
|
//
|
| 1129 |
|
|
//
|
| 1130 |
|
|
reg write_req;
|
| 1131 |
|
|
reg read_req;
|
| 1132 |
|
|
always @(posedge clk or posedge res)
|
| 1133 |
|
|
if (res) write_req <= 1'b0;
|
| 1134 |
|
|
else if (write_ack) write_req <= 1'b0;
|
| 1135 |
|
|
else if (wb_cyc_i && wb_stb_i && !wb_ack_o && !write_ack_z && wb_we_i) write_req <= 1'b1; // wait ack low
|
| 1136 |
|
|
|
| 1137 |
|
|
always @(posedge clk or posedge res)
|
| 1138 |
|
|
if (res) read_req <= 1'b0;
|
| 1139 |
|
|
else if (read_ack) read_req <= 1'b0;
|
| 1140 |
|
|
else if (wb_cyc_i && wb_stb_i && !wb_ack_o && !read_ack_z && !wb_we_i) read_req <= 1'b1; // wait ack low
|
| 1141 |
|
|
|
| 1142 |
|
|
endmodule
|
| 1143 |
|
|
|
| 1144 |
|
|
module tessera_sdram (
|
| 1145 |
|
|
sys_wb_res,
|
| 1146 |
|
|
sys_wb_clk,
|
| 1147 |
|
|
sys_sdram_res,
|
| 1148 |
|
|
sys_sdram_clk,
|
| 1149 |
|
|
wb_cyc_i,
|
| 1150 |
|
|
wb_stb_i,
|
| 1151 |
|
|
wb_adr_i,
|
| 1152 |
|
|
wb_sel_i,
|
| 1153 |
|
|
wb_we_i,
|
| 1154 |
|
|
wb_dat_i,
|
| 1155 |
|
|
wb_cab_i,
|
| 1156 |
|
|
wb_dat_o,
|
| 1157 |
|
|
wb_ack_o,
|
| 1158 |
|
|
wb_err_o,
|
| 1159 |
|
|
dma_req,
|
| 1160 |
|
|
dma_address,
|
| 1161 |
|
|
dma_ack,
|
| 1162 |
|
|
dma_exist,
|
| 1163 |
|
|
dma_data,
|
| 1164 |
|
|
sdram_clk,
|
| 1165 |
|
|
sdram_cke,
|
| 1166 |
|
|
sdram_cs_n,
|
| 1167 |
|
|
sdram_ras_n,
|
| 1168 |
|
|
sdram_cas_n,
|
| 1169 |
|
|
sdram_we_n,
|
| 1170 |
|
|
sdram_dqm,
|
| 1171 |
|
|
sdram_ba,
|
| 1172 |
|
|
sdram_a,
|
| 1173 |
|
|
sdram_d_i,
|
| 1174 |
|
|
sdram_d_oe,
|
| 1175 |
|
|
sdram_d_o,
|
| 1176 |
|
|
//
|
| 1177 |
|
|
option
|
| 1178 |
|
|
);
|
| 1179 |
|
|
// system
|
| 1180 |
|
|
input sys_wb_res;
|
| 1181 |
|
|
input sys_wb_clk;
|
| 1182 |
|
|
input sys_sdram_res;
|
| 1183 |
|
|
input sys_sdram_clk;
|
| 1184 |
|
|
// WishBone Slave
|
| 1185 |
|
|
input wb_cyc_i;
|
| 1186 |
|
|
input wb_stb_i;
|
| 1187 |
|
|
input [31:0] wb_adr_i;
|
| 1188 |
|
|
input [3:0] wb_sel_i;
|
| 1189 |
|
|
input wb_we_i;
|
| 1190 |
|
|
input [31:0] wb_dat_i;
|
| 1191 |
|
|
input wb_cab_i;
|
| 1192 |
|
|
output [31:0] wb_dat_o;
|
| 1193 |
|
|
output wb_ack_o;
|
| 1194 |
|
|
output wb_err_o;
|
| 1195 |
|
|
// Dma
|
| 1196 |
|
|
input dma_req;
|
| 1197 |
|
|
input [31:0] dma_address;
|
| 1198 |
|
|
output dma_ack;
|
| 1199 |
|
|
output dma_exist;
|
| 1200 |
|
|
output [15:0] dma_data;
|
| 1201 |
|
|
// External SDRAM
|
| 1202 |
|
|
output sdram_clk;
|
| 1203 |
|
|
output sdram_cke;
|
| 1204 |
|
|
output [1:0] sdram_cs_n;
|
| 1205 |
|
|
output sdram_ras_n;
|
| 1206 |
|
|
output sdram_cas_n;
|
| 1207 |
|
|
output sdram_we_n;
|
| 1208 |
|
|
output [1:0] sdram_dqm;
|
| 1209 |
|
|
output [1:0] sdram_ba;
|
| 1210 |
|
|
output [12:0] sdram_a;
|
| 1211 |
|
|
input [15:0] sdram_d_i;
|
| 1212 |
|
|
output [15:0] sdram_d_oe;
|
| 1213 |
|
|
output [15:0] sdram_d_o;
|
| 1214 |
|
|
// test
|
| 1215 |
|
|
input option;
|
| 1216 |
|
|
|
| 1217 |
|
|
// sdram_wbif
|
| 1218 |
|
|
wire wbif_write_req;
|
| 1219 |
|
|
wire [3:0] wbif_write_byte;
|
| 1220 |
|
|
wire [31:0] wbif_write_address;
|
| 1221 |
|
|
wire [31:0] wbif_write_data;
|
| 1222 |
|
|
//wire wbif_write_ack;
|
| 1223 |
|
|
reg wbif_write_ack;
|
| 1224 |
|
|
wire wbif_read_req;
|
| 1225 |
|
|
wire [3:0] wbif_read_byte;
|
| 1226 |
|
|
wire [31:0] wbif_read_address;
|
| 1227 |
|
|
wire [31:0] wbif_read_data;
|
| 1228 |
|
|
//wire wbif_read_ack;
|
| 1229 |
|
|
reg wbif_read_ack;
|
| 1230 |
|
|
|
| 1231 |
|
|
// sdram_core
|
| 1232 |
|
|
//wire core_write_req;
|
| 1233 |
|
|
reg core_write_req;
|
| 1234 |
|
|
wire [3:0] core_write_byte;
|
| 1235 |
|
|
wire [31:0] core_write_address;
|
| 1236 |
|
|
wire [31:0] core_write_data;
|
| 1237 |
|
|
wire core_write_ack;
|
| 1238 |
|
|
//wire core_read_req;
|
| 1239 |
|
|
reg core_read_req;
|
| 1240 |
|
|
wire [3:0] core_read_byte;
|
| 1241 |
|
|
wire [31:0] core_read_address;
|
| 1242 |
|
|
wire [31:0] core_read_data;
|
| 1243 |
|
|
wire core_read_ack;
|
| 1244 |
|
|
|
| 1245 |
|
|
// sdram_wbif(DOMAIN WinsboneClock)
|
| 1246 |
|
|
tessera_sdram_wbif i_tessera_sdram_wbif (
|
| 1247 |
|
|
.res( sys_wb_res),
|
| 1248 |
|
|
.clk( sys_wb_clk),
|
| 1249 |
|
|
.wb_cyc_i( wb_cyc_i),
|
| 1250 |
|
|
.wb_stb_i( wb_stb_i),
|
| 1251 |
|
|
.wb_adr_i( wb_adr_i),
|
| 1252 |
|
|
.wb_sel_i( wb_sel_i),
|
| 1253 |
|
|
.wb_we_i( wb_we_i),
|
| 1254 |
|
|
.wb_dat_i( wb_dat_i),
|
| 1255 |
|
|
.wb_cab_i( wb_cab_i),
|
| 1256 |
|
|
.wb_dat_o( wb_dat_o),
|
| 1257 |
|
|
.wb_ack_o( wb_ack_o),
|
| 1258 |
|
|
.wb_err_o( wb_err_o),
|
| 1259 |
|
|
.write_req( wbif_write_req), // is ff
|
| 1260 |
|
|
.write_byte( wbif_write_byte), // is ff
|
| 1261 |
|
|
.write_address( wbif_write_address), // is ff
|
| 1262 |
|
|
.write_data( wbif_write_data), // is ff
|
| 1263 |
|
|
.write_ack( wbif_write_ack),
|
| 1264 |
|
|
.read_req( wbif_read_req), // is ff
|
| 1265 |
|
|
.read_byte( wbif_read_byte), // is ff
|
| 1266 |
|
|
.read_address( wbif_read_address), // is ff
|
| 1267 |
|
|
.read_data( wbif_read_data),
|
| 1268 |
|
|
.read_ack( wbif_read_ack)
|
| 1269 |
|
|
);
|
| 1270 |
|
|
|
| 1271 |
|
|
//
|
| 1272 |
|
|
// no-mt1-mt2(TYPE A:same clock)
|
| 1273 |
|
|
//
|
| 1274 |
|
|
// sync (sys_wbif_clk<=>sys_sdram_clk) , small & fastpath , danger
|
| 1275 |
|
|
/*
|
| 1276 |
|
|
// sd to wb
|
| 1277 |
|
|
assign wbif_write_ack = core_write_ack;
|
| 1278 |
|
|
assign wbif_read_data = core_read_data;
|
| 1279 |
|
|
assign wbif_read_ack = core_read_ack;
|
| 1280 |
|
|
// wb to sd
|
| 1281 |
|
|
assign core_write_req = wbif_write_req;
|
| 1282 |
|
|
assign core_write_byte = wbif_write_byte;
|
| 1283 |
|
|
assign core_write_address = wbif_write_address;
|
| 1284 |
|
|
assign core_write_data = wbif_write_data;
|
| 1285 |
|
|
assign core_read_req = wbif_read_req;
|
| 1286 |
|
|
assign core_read_byte = wbif_read_byte;
|
| 1287 |
|
|
assign core_read_address = wbif_read_address;
|
| 1288 |
|
|
*/
|
| 1289 |
|
|
//
|
| 1290 |
|
|
// only startpoint(TYPE B:same clock,pos<->neg,timeing is safety)
|
| 1291 |
|
|
//
|
| 1292 |
|
|
// sync
|
| 1293 |
|
|
// sd to wb
|
| 1294 |
|
|
/*
|
| 1295 |
|
|
reg mt_write_ack;
|
| 1296 |
|
|
reg [31:0] mt_read_data;
|
| 1297 |
|
|
reg mt_read_ack;
|
| 1298 |
|
|
always @(posedge sys_wb_clk or posedge sys_wb_res)
|
| 1299 |
|
|
if (sys_wb_res) begin
|
| 1300 |
|
|
mt_write_ack <= 1'b0;
|
| 1301 |
|
|
mt_read_data <= {4{8'h00}};
|
| 1302 |
|
|
mt_read_ack <= 1'b0;
|
| 1303 |
|
|
end
|
| 1304 |
|
|
else begin
|
| 1305 |
|
|
mt_write_ack <= core_write_ack;
|
| 1306 |
|
|
mt_read_data <= core_read_data;
|
| 1307 |
|
|
mt_read_ack <= core_read_ack;
|
| 1308 |
|
|
end
|
| 1309 |
|
|
reg mt_write_req;
|
| 1310 |
|
|
reg [3:0] mt_write_byte;
|
| 1311 |
|
|
reg [31:0] mt_write_address;
|
| 1312 |
|
|
reg [31:0] mt_write_data;
|
| 1313 |
|
|
reg mt_read_req;
|
| 1314 |
|
|
reg [3:0] mt_read_byte;
|
| 1315 |
|
|
reg [31:0] mt_read_address;
|
| 1316 |
|
|
always @(posedge sys_sdram_clk or posedge sys_sdram_res)
|
| 1317 |
|
|
if (sys_sdram_res) begin
|
| 1318 |
|
|
mt_write_req <= 1'b0;
|
| 1319 |
|
|
mt_write_byte <= {4{1'b0}};
|
| 1320 |
|
|
mt_write_address <= 32'd0;
|
| 1321 |
|
|
mt_write_data <= {4{8'h00}};
|
| 1322 |
|
|
mt_read_req <= 1'b0;
|
| 1323 |
|
|
mt_read_byte <= {4{1'b0}};
|
| 1324 |
|
|
mt_read_address <= 32'd0;
|
| 1325 |
|
|
end
|
| 1326 |
|
|
else begin
|
| 1327 |
|
|
mt_write_req <= wbif_write_req;
|
| 1328 |
|
|
mt_write_byte <= wbif_write_byte;
|
| 1329 |
|
|
mt_write_address <= wbif_write_address;
|
| 1330 |
|
|
mt_write_data <= wbif_write_data;
|
| 1331 |
|
|
mt_read_req <= wbif_read_req;
|
| 1332 |
|
|
mt_read_byte <= wbif_read_byte;
|
| 1333 |
|
|
mt_read_address <= wbif_read_address;
|
| 1334 |
|
|
end
|
| 1335 |
|
|
// sd to wb
|
| 1336 |
|
|
assign wbif_write_ack = mt_write_ack;
|
| 1337 |
|
|
assign wbif_read_data = mt_read_data;
|
| 1338 |
|
|
assign wbif_read_ack = mt_read_ack;
|
| 1339 |
|
|
// wb to sd
|
| 1340 |
|
|
assign core_write_req = mt_write_req;
|
| 1341 |
|
|
assign core_write_byte = mt_write_byte;
|
| 1342 |
|
|
assign core_write_address = mt_write_address;
|
| 1343 |
|
|
assign core_write_data = mt_write_data;
|
| 1344 |
|
|
assign core_read_req = mt_read_req;
|
| 1345 |
|
|
assign core_read_byte = mt_read_byte;
|
| 1346 |
|
|
assign core_read_address = mt_read_address;
|
| 1347 |
|
|
*/
|
| 1348 |
|
|
//
|
| 1349 |
|
|
// mt1 mt2(TYPE C:other clock)
|
| 1350 |
|
|
//
|
| 1351 |
|
|
// not need to sync (sys_wbif_clk<=>sys_sdram_clk)
|
| 1352 |
|
|
// sd to wb
|
| 1353 |
|
|
reg mt1_write_ack;
|
| 1354 |
|
|
reg [31:0] mt1_read_data;
|
| 1355 |
|
|
reg mt1_read_ack;
|
| 1356 |
|
|
always @(posedge sys_wb_clk or posedge sys_wb_res)
|
| 1357 |
|
|
if (sys_wb_res) begin
|
| 1358 |
|
|
mt1_write_ack <= 1'b0;
|
| 1359 |
|
|
mt1_read_data <= {4{8'h00}};
|
| 1360 |
|
|
mt1_read_ack <= 1'b0;
|
| 1361 |
|
|
end
|
| 1362 |
|
|
else begin
|
| 1363 |
|
|
mt1_write_ack <= core_write_ack;
|
| 1364 |
|
|
mt1_read_data <= core_read_data;
|
| 1365 |
|
|
mt1_read_ack <= core_read_ack;
|
| 1366 |
|
|
end
|
| 1367 |
|
|
reg mt2_write_ack;
|
| 1368 |
|
|
reg [31:0] mt2_read_data;
|
| 1369 |
|
|
reg mt2_read_ack;
|
| 1370 |
|
|
always @(posedge sys_wb_clk or posedge sys_wb_res)
|
| 1371 |
|
|
if (sys_wb_res) begin
|
| 1372 |
|
|
mt2_write_ack <= 1'b0;
|
| 1373 |
|
|
mt2_read_data <= {4{8'h00}};
|
| 1374 |
|
|
mt2_read_ack <= 1'b0;
|
| 1375 |
|
|
end
|
| 1376 |
|
|
else begin
|
| 1377 |
|
|
mt2_write_ack <= mt1_write_ack;
|
| 1378 |
|
|
mt2_read_data <= mt1_read_data;
|
| 1379 |
|
|
mt2_read_ack <= mt1_read_ack;
|
| 1380 |
|
|
end
|
| 1381 |
|
|
reg mt1_write_req;
|
| 1382 |
|
|
reg [3:0] mt1_write_byte;
|
| 1383 |
|
|
reg [31:0] mt1_write_address;
|
| 1384 |
|
|
reg [31:0] mt1_write_data;
|
| 1385 |
|
|
reg mt1_read_req;
|
| 1386 |
|
|
reg [3:0] mt1_read_byte;
|
| 1387 |
|
|
reg [31:0] mt1_read_address;
|
| 1388 |
|
|
always @(posedge sys_sdram_clk or posedge sys_sdram_res)
|
| 1389 |
|
|
if (sys_sdram_res) begin
|
| 1390 |
|
|
mt1_write_req <= 1'b0;
|
| 1391 |
|
|
mt1_write_byte <= {4{1'b0}};
|
| 1392 |
|
|
mt1_write_address <= 32'd0;
|
| 1393 |
|
|
mt1_write_data <= {4{8'h00}};
|
| 1394 |
|
|
mt1_read_req <= 1'b0;
|
| 1395 |
|
|
mt1_read_byte <= {4{1'b0}};
|
| 1396 |
|
|
mt1_read_address <= 32'd0;
|
| 1397 |
|
|
end
|
| 1398 |
|
|
else begin
|
| 1399 |
|
|
mt1_write_req <= wbif_write_req;
|
| 1400 |
|
|
mt1_write_byte <= wbif_write_byte;
|
| 1401 |
|
|
mt1_write_address <= wbif_write_address;
|
| 1402 |
|
|
mt1_write_data <= wbif_write_data;
|
| 1403 |
|
|
mt1_read_req <= wbif_read_req;
|
| 1404 |
|
|
mt1_read_byte <= wbif_read_byte;
|
| 1405 |
|
|
mt1_read_address <= wbif_read_address;
|
| 1406 |
|
|
end
|
| 1407 |
|
|
reg mt2_write_req;
|
| 1408 |
|
|
reg [3:0] mt2_write_byte;
|
| 1409 |
|
|
reg [31:0] mt2_write_address;
|
| 1410 |
|
|
reg [31:0] mt2_write_data;
|
| 1411 |
|
|
reg mt2_read_req;
|
| 1412 |
|
|
reg [3:0] mt2_read_byte;
|
| 1413 |
|
|
reg [31:0] mt2_read_address;
|
| 1414 |
|
|
always @(posedge sys_sdram_clk or posedge sys_sdram_res)
|
| 1415 |
|
|
if (sys_sdram_res) begin
|
| 1416 |
|
|
mt2_write_req <= 1'b0;
|
| 1417 |
|
|
mt2_write_byte <= {4{1'b0}};
|
| 1418 |
|
|
mt2_write_address <= 32'd0;
|
| 1419 |
|
|
mt2_write_data <= {4{8'h00}};
|
| 1420 |
|
|
mt2_read_req <= 1'b0;
|
| 1421 |
|
|
mt2_read_byte <= {4{1'b0}};
|
| 1422 |
|
|
mt2_read_address <= 32'd0;
|
| 1423 |
|
|
end
|
| 1424 |
|
|
else begin
|
| 1425 |
|
|
mt2_write_req <= mt1_write_req;
|
| 1426 |
|
|
mt2_write_byte <= mt1_write_byte;
|
| 1427 |
|
|
mt2_write_address <= mt1_write_address;
|
| 1428 |
|
|
mt2_write_data <= mt1_write_data;
|
| 1429 |
|
|
mt2_read_req <= mt1_read_req;
|
| 1430 |
|
|
mt2_read_byte <= mt1_read_byte;
|
| 1431 |
|
|
mt2_read_address <= mt1_read_address;
|
| 1432 |
|
|
end
|
| 1433 |
|
|
// sd to wb
|
| 1434 |
|
|
//assign wbif_write_ack = mt2_write_ack;
|
| 1435 |
|
|
//assign wbif_read_ack = mt2_read_ack;
|
| 1436 |
|
|
always @(posedge sys_wb_clk or posedge sys_wb_res)
|
| 1437 |
|
|
if (sys_wb_res) begin
|
| 1438 |
|
|
wbif_write_ack <= 1'b0;
|
| 1439 |
|
|
wbif_read_ack <= 1'b0;
|
| 1440 |
|
|
end
|
| 1441 |
|
|
else begin
|
| 1442 |
|
|
wbif_write_ack <= mt2_write_ack; // can not load data, so must +1delay
|
| 1443 |
|
|
wbif_read_ack <= mt2_read_ack; // can not load data, so must +1delay
|
| 1444 |
|
|
end
|
| 1445 |
|
|
assign wbif_read_data = mt2_read_data;
|
| 1446 |
|
|
|
| 1447 |
|
|
// wb to sd
|
| 1448 |
|
|
//assign core_write_req = mt2_write_req;
|
| 1449 |
|
|
//assign core_read_req = mt2_read_req;
|
| 1450 |
|
|
always @(posedge sys_sdram_clk or posedge sys_sdram_res)
|
| 1451 |
|
|
if (sys_sdram_res) begin
|
| 1452 |
|
|
core_write_req <= 1'b0;
|
| 1453 |
|
|
core_read_req <= 1'b0;
|
| 1454 |
|
|
end
|
| 1455 |
|
|
else begin
|
| 1456 |
|
|
core_write_req <= mt2_write_req; // can not load data, so must +1delay
|
| 1457 |
|
|
core_read_req <= mt2_read_req; // can not load data, so must +1delay
|
| 1458 |
|
|
end
|
| 1459 |
|
|
assign core_write_byte = mt2_write_byte;
|
| 1460 |
|
|
assign core_write_address = mt2_write_address;
|
| 1461 |
|
|
assign core_write_data = mt2_write_data;
|
| 1462 |
|
|
assign core_read_byte = mt2_read_byte;
|
| 1463 |
|
|
assign core_read_address = mt2_read_address;
|
| 1464 |
|
|
|
| 1465 |
|
|
// inst
|
| 1466 |
|
|
tessera_sdram_core i_tessera_sdram_core (
|
| 1467 |
|
|
.res( sys_sdram_res),
|
| 1468 |
|
|
.clk( sys_sdram_clk),
|
| 1469 |
|
|
.write_req( core_write_req),
|
| 1470 |
|
|
.write_byte( core_write_byte),
|
| 1471 |
|
|
.write_address( core_write_address),
|
| 1472 |
|
|
.write_data( core_write_data),
|
| 1473 |
|
|
.write_ack( core_write_ack), // is ff signal
|
| 1474 |
|
|
.read_req( core_read_req),
|
| 1475 |
|
|
.read_byte( core_read_byte),
|
| 1476 |
|
|
.read_address( core_read_address),
|
| 1477 |
|
|
.read_data( core_read_data), // is ff signal
|
| 1478 |
|
|
.read_ack( core_read_ack), // is ff signal
|
| 1479 |
|
|
.dma_req( dma_req),
|
| 1480 |
|
|
.dma_address( dma_address),
|
| 1481 |
|
|
.dma_ack( dma_ack),
|
| 1482 |
|
|
.dma_exist( dma_exist),
|
| 1483 |
|
|
.dma_data( dma_data),
|
| 1484 |
|
|
.sdram_clk( sdram_clk),
|
| 1485 |
|
|
.sdram_cke( sdram_cke),
|
| 1486 |
|
|
.sdram_cs_n( sdram_cs_n),
|
| 1487 |
|
|
.sdram_ras_n( sdram_ras_n),
|
| 1488 |
|
|
.sdram_cas_n( sdram_cas_n),
|
| 1489 |
|
|
.sdram_we_n( sdram_we_n),
|
| 1490 |
|
|
.sdram_dqm( sdram_dqm),
|
| 1491 |
|
|
.sdram_ba( sdram_ba),
|
| 1492 |
|
|
.sdram_adr( sdram_a),
|
| 1493 |
|
|
.sdram_d_i( sdram_d_i),
|
| 1494 |
|
|
.sdram_d_oe( sdram_d_oe),
|
| 1495 |
|
|
.sdram_d_o( sdram_d_o),
|
| 1496 |
|
|
.option( option)
|
| 1497 |
|
|
);
|
| 1498 |
|
|
|
| 1499 |
|
|
endmodule
|
| 1500 |
|
|
|
