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[/] [kiss-board/] [tags/] [initial/] [kiss-board_soc/] [src/] [tessera_tic.v] - Blame information for rev 11

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`timescale 1ps/1ps
 
module tessera_tic (
        wb_rst,
        wb_clk,
        wb_cyc_o,
        wb_adr_o,
        wb_dat_i,
        wb_dat_o,
        wb_sel_o,
        wb_ack_i,
        wb_err_i,
        wb_rty_i,
        wb_we_o,
        wb_stb_o,
        wb_cab_o
);
        input           wb_rst;
        input           wb_clk;
        output          wb_cyc_o;
        output  [31:0]   wb_adr_o;
        input   [31:0]   wb_dat_i;
        output  [31:0]   wb_dat_o;
        output  [3:0]    wb_sel_o;
        input           wb_ack_i;
        input           wb_err_i;
        input           wb_rty_i;
        output          wb_we_o;
        output          wb_stb_o;
        output          wb_cab_o;
`ifdef SIM
        reg             r_wb_cyc_o;
        reg     [31:0]   r_wb_adr_o;
        reg     [31:0]   r_wb_dat_o;
        reg     [31:0]   r_wb_sel_o;
        reg             r_wb_we_o;
        reg             r_wb_stb_o;
        reg             r_wb_cab_o;
        initial begin
                r_wb_cyc_o = 1'b0;
                r_wb_adr_o = 32'h0000_0000;
                r_wb_dat_o = 32'h0000_0000;
                r_wb_sel_o = 4'b0000;
                r_wb_we_o  = 1'b0;
                r_wb_stb_o = 1'b0;
                r_wb_cab_o = 1'b0;
        end
`define MISC_OFFSET 1
        assign #(`MISC_OFFSET) wb_cyc_o = r_wb_cyc_o;
        assign #(`MISC_OFFSET) wb_adr_o = r_wb_adr_o;
        assign #(`MISC_OFFSET) wb_dat_o = r_wb_dat_o;
        assign #(`MISC_OFFSET) wb_sel_o = r_wb_sel_o;
        assign #(`MISC_OFFSET) wb_we_o  = r_wb_we_o;
        assign #(`MISC_OFFSET) wb_stb_o = r_wb_stb_o;
        assign #(`MISC_OFFSET) wb_cab_o = r_wb_cab_o;
        task task_wr_ext;
                input           cab;
                input   [31:0]   adr;
                input   [3:0]    sel;
                input   [31:0]   data;
        begin
                begin
                        r_wb_cyc_o <= 1'b1;
                        r_wb_adr_o <= adr;
                        r_wb_dat_o <= data;
                        r_wb_sel_o <= sel;
                        r_wb_we_o  <= 1'b1;
                        r_wb_stb_o <= 1'b1;
                        r_wb_cab_o <= cab;
                end
                begin : label_detect_wr_ext_ack
                        forever @(posedge wb_clk) if (wb_ack_i==1'b1) disable label_detect_wr_ext_ack;
                end
                begin
                        r_wb_cyc_o <= 1'b0;
                        r_wb_adr_o <= adr;
                        r_wb_dat_o <= data;
                        r_wb_sel_o <= sel;
                        r_wb_we_o  <= 1'b0;
                        r_wb_stb_o <= 1'b0;
                        r_wb_cab_o <= 1'b0;
                end
                @(posedge wb_clk);
        end
        endtask
 
        task task_rd_ext;
                input           cab;
                input   [31:0]   adr;
                input   [3:0]    sel;
                input   [31:0]   data;
        begin
                begin
                        r_wb_cyc_o <= 1'b1;
                        r_wb_adr_o <= adr;
                        r_wb_dat_o <= data;
                        r_wb_sel_o <= sel;
                        r_wb_we_o  <= 1'b0;
                        r_wb_stb_o <= 1'b1;
                        r_wb_cab_o <= cab;
                end
                begin : label_detect_rd_ext_ack
                        forever @(posedge wb_clk) if (wb_ack_i==1'b1) disable label_detect_rd_ext_ack;
                end
                begin
                        r_wb_cyc_o <= 1'b0;
                        r_wb_adr_o <= adr;
                        r_wb_dat_o <= data;
                        r_wb_sel_o <= sel;
                        r_wb_we_o  <= 1'b0;
                        r_wb_stb_o <= 1'b0;
                        r_wb_cab_o <= 1'b0;
                end
                @(posedge wb_clk);
        end
        endtask
`else
        assign wb_cyc_o = 1'b0;
        assign wb_adr_o = 32'h0000_0000;
        assign wb_dat_o = 32'h0000_0000;
        assign wb_sel_o = 4'b0000;
        assign wb_we_o  = 1'b0;
        assign wb_stb_o = 1'b0;
        assign wb_cab_o = 1'b0;
`endif
 
endmodule
 

Line No.	Rev	Author	Line
1	2	fukuchi
2			`timescale 1ps/1ps
3
4			`module tessera_tic (`
5			`wb_rst,`
6			`wb_clk,`
7			`wb_cyc_o,`
8			`wb_adr_o,`
9			`wb_dat_i,`
10			`wb_dat_o,`
11			`wb_sel_o,`
12			`wb_ack_i,`
13			`wb_err_i,`
14			`wb_rty_i,`
15			`wb_we_o,`
16			`wb_stb_o,`
17			`wb_cab_o`
18			`);`
19			`input wb_rst;`
20			`input wb_clk;`
21			`output wb_cyc_o;`
22			`output [31:0] wb_adr_o;`
23			`input [31:0] wb_dat_i;`
24			`output [31:0] wb_dat_o;`
25			`output [3:0] wb_sel_o;`
26			`input wb_ack_i;`
27			`input wb_err_i;`
28			`input wb_rty_i;`
29			`output wb_we_o;`
30			`output wb_stb_o;`
31			`output wb_cab_o;`
32			`ifdef SIM
33			`reg r_wb_cyc_o;`
34			`reg [31:0] r_wb_adr_o;`
35			`reg [31:0] r_wb_dat_o;`
36			`reg [31:0] r_wb_sel_o;`
37			`reg r_wb_we_o;`
38			`reg r_wb_stb_o;`
39			`reg r_wb_cab_o;`
40			`initial begin`
41			`r_wb_cyc_o = 1'b0;`
42			`r_wb_adr_o = 32'h0000_0000;`
43			`r_wb_dat_o = 32'h0000_0000;`
44			`r_wb_sel_o = 4'b0000;`
45			`r_wb_we_o = 1'b0;`
46			`r_wb_stb_o = 1'b0;`
47			`r_wb_cab_o = 1'b0;`
48			`end`
49			`define MISC_OFFSET 1
50			assign #(`MISC_OFFSET) wb_cyc_o = r_wb_cyc_o;
51			assign #(`MISC_OFFSET) wb_adr_o = r_wb_adr_o;
52			assign #(`MISC_OFFSET) wb_dat_o = r_wb_dat_o;
53			assign #(`MISC_OFFSET) wb_sel_o = r_wb_sel_o;
54			assign #(`MISC_OFFSET) wb_we_o = r_wb_we_o;
55			assign #(`MISC_OFFSET) wb_stb_o = r_wb_stb_o;
56			assign #(`MISC_OFFSET) wb_cab_o = r_wb_cab_o;
57			`task task_wr_ext;`
58			`input cab;`
59			`input [31:0] adr;`
60			`input [3:0] sel;`
61			`input [31:0] data;`
62			`begin`
63			`begin`
64			`r_wb_cyc_o <= 1'b1;`
65			`r_wb_adr_o <= adr;`
66			`r_wb_dat_o <= data;`
67			`r_wb_sel_o <= sel;`
68			`r_wb_we_o <= 1'b1;`
69			`r_wb_stb_o <= 1'b1;`
70			`r_wb_cab_o <= cab;`
71			`end`
72			`begin : label_detect_wr_ext_ack`
73			`forever @(posedge wb_clk) if (wb_ack_i==1'b1) disable label_detect_wr_ext_ack;`
74			`end`
75			`begin`
76			`r_wb_cyc_o <= 1'b0;`
77			`r_wb_adr_o <= adr;`
78			`r_wb_dat_o <= data;`
79			`r_wb_sel_o <= sel;`
80			`r_wb_we_o <= 1'b0;`
81			`r_wb_stb_o <= 1'b0;`
82			`r_wb_cab_o <= 1'b0;`
83			`end`
84			`@(posedge wb_clk);`
85			`end`
86			`endtask`
87
88			`task task_rd_ext;`
89			`input cab;`
90			`input [31:0] adr;`
91			`input [3:0] sel;`
92			`input [31:0] data;`
93			`begin`
94			`begin`
95			`r_wb_cyc_o <= 1'b1;`
96			`r_wb_adr_o <= adr;`
97			`r_wb_dat_o <= data;`
98			`r_wb_sel_o <= sel;`
99			`r_wb_we_o <= 1'b0;`
100			`r_wb_stb_o <= 1'b1;`
101			`r_wb_cab_o <= cab;`
102			`end`
103			`begin : label_detect_rd_ext_ack`
104			`forever @(posedge wb_clk) if (wb_ack_i==1'b1) disable label_detect_rd_ext_ack;`
105			`end`
106			`begin`
107			`r_wb_cyc_o <= 1'b0;`
108			`r_wb_adr_o <= adr;`
109			`r_wb_dat_o <= data;`
110			`r_wb_sel_o <= sel;`
111			`r_wb_we_o <= 1'b0;`
112			`r_wb_stb_o <= 1'b0;`
113			`r_wb_cab_o <= 1'b0;`
114			`end`
115			`@(posedge wb_clk);`
116			`end`
117			`endtask`
118			`else
119			`assign wb_cyc_o = 1'b0;`
120			`assign wb_adr_o = 32'h0000_0000;`
121			`assign wb_dat_o = 32'h0000_0000;`
122			`assign wb_sel_o = 4'b0000;`
123			`assign wb_we_o = 1'b0;`
124			`assign wb_stb_o = 1'b0;`
125			`assign wb_cab_o = 1'b0;`
126			`endif
127
128			`endmodule`
129

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[/] [kiss-board/] [tags/] [initial/] [kiss-board_soc/] [src/] [tessera_tic.v] - Blame information for rev 11