| 1 |
2 |
fukuchi |
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| 2 |
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#############################################################
|
| 3 |
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### (ALLNoWAVE,NotSupportSDF(not-check))
|
| 4 |
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#############################################################
|
| 5 |
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INCCMD = +incdir+
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| 6 |
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VLOG = ./csh/vlog.csh
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| 7 |
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VSIM = ./csh/vsim.csh
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| 8 |
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| 9 |
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#############################################################
|
| 10 |
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### NCVERILOG(ALLNoWAVE,NotSupportSDF(not-check))
|
| 11 |
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#############################################################
|
| 12 |
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#INCCMD = -INCDIR
|
| 13 |
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#VLOG = ./csh/ncvlog.csh
|
| 14 |
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#VSIM = ./csh/ncvsim.csh
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| 15 |
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| 16 |
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#############################################################
|
| 17 |
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### MODELSIM(VSIMRTLEXTisNowave)
|
| 18 |
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#############################################################
|
| 19 |
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MODEL_INC = $(INCCMD)./mod
|
| 20 |
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MODEL_SRC = ./mod
|
| 21 |
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#XILINX_INC = $(INCCMD)../../../orp/orp_soc/lib/xilinx
|
| 22 |
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#XILINX_SRC = ../../../orp/orp_soc/lib/xilinx
|
| 23 |
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#MEM_IF_INC = $(INCCMD)../../../orp/orp_soc/rtl/verilog/mem_if
|
| 24 |
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#MEM_IF_SRC = ../../../orp/orp_soc/rtl/verilog/mem_if
|
| 25 |
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#SSVGA_INC = $(INCCMD)../../../orp/orp_soc/rtl/verilog/ssvga
|
| 26 |
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#SSVGA_SRC = ../../../orp/orp_soc/rtl/verilog/ssvga
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| 27 |
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#VGA_LCD_INC = $(INCCMD)../../../../vga_lcd/rtl/verilog
|
| 28 |
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#VGA_LCD_SRC = ../../../../vga_lcd/rtl/verilog
|
| 29 |
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UART_INC = $(INCCMD)../src/extend/uart16550
|
| 30 |
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UART_SRC = ../src/extend/uart16550
|
| 31 |
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DBG_INTERFACE_INC = $(INCCMD)../src/extend/dbg_interface
|
| 32 |
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DBG_INTERFACE_SRC = ../src/extend/dbg_interface
|
| 33 |
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TC_INC = $(INCCMD)../src/extend/tc
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| 34 |
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TC_SRC = ../src/extend/tc
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| 35 |
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WB_DMA_INC = $(INCCMD)../src/extend/wb_dma
|
| 36 |
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WB_DMA_SRC = ../src/extend/wb_dma
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| 37 |
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OR1200_INC = $(INCCMD)../src/extend/or1200
|
| 38 |
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OR1200_SRC = ../src/extend/or1200
|
| 39 |
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TESSERA_INC = $(INCCMD)../src
|
| 40 |
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TESSERA_SRC = ../src
|
| 41 |
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|
| 42 |
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|
| 43 |
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test_rtl: clean model altera uart16550 dbg_interface wb_dma tc or1200 tessera
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| 44 |
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$(VLOG) $(INCCMD). ./pat/test.v
|
| 45 |
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$(VSIM) test test
|
| 46 |
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test_gate: clean model altera gate
|
| 47 |
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$(VLOG) $(INCCMD). ./pat/test.v
|
| 48 |
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$(VSIM) test test
|
| 49 |
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|
| 50 |
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clean:
|
| 51 |
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rm -rf ./*.log
|
| 52 |
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#################################
|
| 53 |
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### modelsim
|
| 54 |
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#################################
|
| 55 |
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rm -rf ./work
|
| 56 |
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vlib work
|
| 57 |
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rm -rf ./wav
|
| 58 |
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mkdir wav
|
| 59 |
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#################################
|
| 60 |
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### ncverilog
|
| 61 |
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#################################
|
| 62 |
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#rm -rf ./*.txt
|
| 63 |
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#rm -rf ./lib
|
| 64 |
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#rm -rf ./work
|
| 65 |
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#mkdir ./lib
|
| 66 |
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#mkdir ./work
|
| 67 |
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model:
|
| 68 |
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/ram.v
|
| 69 |
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/sdram4m8br12c8.v
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| 70 |
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/sdram8m8br12c9.v
|
| 71 |
|
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/mt48lc4m16a2.v
|
| 72 |
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/mt48lc16m16a2.v
|
| 73 |
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/mt48lc32m16a2.v
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| 74 |
|
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/512Kx8.v
|
| 75 |
|
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/dbg_if_model.v
|
| 76 |
|
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#$(VLOG) $(MODEL_INC) +define+DBG_IF_COMM $(MODEL_SRC)/dbg_comm2.v
|
| 77 |
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/wb_master.v
|
| 78 |
|
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#$(VLOG) $(MODEL_INC)/28f016s3 $(MODEL_SRC)/28f016s3/bwsvff.v
|
| 79 |
|
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/cycloneii_atoms.v
|
| 80 |
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#$(VLOG) $(MODEL_INC) $(MODEL_SRC)/verilog_k4s281632f_0401.v
|
| 81 |
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$(VLOG) $(MODEL_INC) $(MODEL_SRC)/rom.v
|
| 82 |
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$(VLOG) $(MODEL_INC) $(MODEL_SRC)/mt48lc8m16a2.v
|
| 83 |
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$(VLOG) $(MODEL_INC) $(MODEL_SRC)/altera_mf.v
|
| 84 |
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$(VLOG) $(MODEL_INC) $(MODEL_SRC)/220model.v
|
| 85 |
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mem_if:
|
| 86 |
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#$(VLOG) $(MEM_IF_INC) $(MEM_IF_SRC)/flash_top.v
|
| 87 |
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#$(VLOG) $(MEM_IF_INC) $(MEM_IF_SRC)/sram_top.v
|
| 88 |
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ssvga:
|
| 89 |
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#$(VLOG) $(SSVGA_INC) $(SSVGA_SRC)/ssvga_crtc.v
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| 90 |
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#$(VLOG) $(SSVGA_INC) $(SSVGA_SRC)/ssvga_fifo.v
|
| 91 |
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#$(VLOG) $(SSVGA_INC) $(SSVGA_SRC)/ssvga_wbm_if.v
|
| 92 |
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#$(VLOG) $(SSVGA_INC) $(SSVGA_SRC)/ssvga_wbs_if.v
|
| 93 |
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#$(VLOG) $(SSVGA_INC) $(SSVGA_SRC)/ssvga_top.v
|
| 94 |
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vga_lcd:
|
| 95 |
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_clkgen.v
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| 96 |
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_colproc.v
|
| 97 |
|
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_csm_pb.v
|
| 98 |
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_cur_cregs.v
|
| 99 |
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_curproc.v
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| 100 |
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_enh_top.v
|
| 101 |
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_fifo.v
|
| 102 |
|
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_fifo_dc.v
|
| 103 |
|
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_pgen.v
|
| 104 |
|
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_tgen.v
|
| 105 |
|
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_vtim.v
|
| 106 |
|
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_wb_master.v
|
| 107 |
|
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/vga_wb_slave.v
|
| 108 |
|
|
#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/generic_dpram.v
|
| 109 |
|
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#$(VLOG) $(VGA_LCD_INC) $(VGA_LCD_SRC)/generic_spram.v
|
| 110 |
|
|
xilinx:
|
| 111 |
|
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#$(VLOG) $(XILINX_INC)/coregen $(XILINX_SRC)/coregen/XilinxCoreLib/async_fifo_v3_0.v
|
| 112 |
|
|
#$(VLOG) $(XILINX_INC)/unisims $(XILINX_SRC)/unisims/RAMB4_S16.v
|
| 113 |
|
|
#$(VLOG) $(XILINX_INC)/unisims $(XILINX_SRC)/unisims/RAMB4_S8.v
|
| 114 |
|
|
#$(VLOG) $(XILINX_INC)/unisims $(XILINX_SRC)/unisims/RAMB4_S4.v
|
| 115 |
|
|
#$(VLOG) $(XILINX_INC)/unisims $(XILINX_SRC)/unisims/RAMB4_S2.v
|
| 116 |
|
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#$(VLOG) $(XILINX_INC)/unisims $(XILINX_SRC)/unisims/RAMB4_S16_S16.v
|
| 117 |
|
|
#$(VLOG) $(XILINX_INC)/unisims $(XILINX_SRC)/unisims/RAM32X1D.v
|
| 118 |
|
|
#$(VLOG) $(XILINX_INC)/unisims $(XILINX_SRC)/unisims/RAMB4_S8_S16.v
|
| 119 |
|
|
#$(VLOG) $(XILINX_INC)/unisims $(XILINX_SRC)/unisims/IBUFG.v
|
| 120 |
|
|
#$(VLOG) $(XILINX_INC)/unisims $(XILINX_SRC)/unisims/BUFG.v
|
| 121 |
|
|
#$(VLOG) $(XILINX_INC)/unisims $(XILINX_SRC)/unisims/CLKDLL.v
|
| 122 |
|
|
altera:
|
| 123 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/RAMB4_S8_S16.v
|
| 124 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/RAMB4_S8_S64.v
|
| 125 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/RAMB4_S8_S128.v
|
| 126 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/RAMB4_S16_S16.v
|
| 127 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/RAM_256.v
|
| 128 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/RAM_512.v
|
| 129 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/RAM_1024.v
|
| 130 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/RAM_2048.v
|
| 131 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/FIFO_LINE.v
|
| 132 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/FIFO_SB.v
|
| 133 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx7per8_20to17_50.v
|
| 134 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx1_20to20.v
|
| 135 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx5per4_20to25.v
|
| 136 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx3per2_20to30.v
|
| 137 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx7per4_20to35.v
|
| 138 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx2_20to40.v
|
| 139 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx5per2_20to50.v
|
| 140 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx3_20to60.v
|
| 141 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx7per2_20to70.v
|
| 142 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx4_20to80.v
|
| 143 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pllx6_20to120.v
|
| 144 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/plletc.v
|
| 145 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pll_20to25AND50.v
|
| 146 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pll_20to30AND50.v
|
| 147 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pll_20to25AND60.v
|
| 148 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pll_20to20AND40.v
|
| 149 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pll_20to17P5AND35.v
|
| 150 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pll_20to20.v
|
| 151 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/pll_20to40.v
|
| 152 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/altera/div.v
|
| 153 |
|
|
gate:
|
| 154 |
|
|
$(VLOG) $(TESSERA_INC) ./tessera_top.vo
|
| 155 |
|
|
dbg_interface:
|
| 156 |
|
|
$(VLOG) $(DBG_INTERFACE_INC) $(DBG_INTERFACE_SRC)/dbg_crc8_d1.v
|
| 157 |
|
|
$(VLOG) $(DBG_INTERFACE_INC) $(DBG_INTERFACE_SRC)/dbg_defines.v
|
| 158 |
|
|
$(VLOG) $(DBG_INTERFACE_INC) $(DBG_INTERFACE_SRC)/dbg_register.v
|
| 159 |
|
|
$(VLOG) $(DBG_INTERFACE_INC) $(DBG_INTERFACE_SRC)/dbg_registers.v
|
| 160 |
|
|
$(VLOG) $(DBG_INTERFACE_INC) $(DBG_INTERFACE_SRC)/dbg_sync_clk1_clk2.v
|
| 161 |
|
|
$(VLOG) $(DBG_INTERFACE_INC) $(DBG_INTERFACE_SRC)/dbg_top.v
|
| 162 |
|
|
$(VLOG) $(DBG_INTERFACE_INC) $(DBG_INTERFACE_SRC)/dbg_trace.v
|
| 163 |
|
|
uart16550:
|
| 164 |
|
|
$(VLOG) $(UART_INC) $(UART_SRC)/raminfr.v
|
| 165 |
|
|
$(VLOG) $(UART_INC) $(UART_SRC)/uart_sync_flops.v
|
| 166 |
|
|
$(VLOG) $(UART_INC) $(UART_SRC)/uart_debug_if.v
|
| 167 |
|
|
$(VLOG) $(UART_INC) $(UART_SRC)/uart_tfifo.v
|
| 168 |
|
|
$(VLOG) $(UART_INC) $(UART_SRC)/uart_rfifo.v
|
| 169 |
|
|
$(VLOG) $(UART_INC) $(UART_SRC)/uart_receiver.v
|
| 170 |
|
|
$(VLOG) $(UART_INC) $(UART_SRC)/uart_regs.v
|
| 171 |
|
|
$(VLOG) $(UART_INC) $(UART_SRC)/uart_transmitter.v
|
| 172 |
|
|
$(VLOG) $(UART_INC) $(UART_SRC)/uart_wb.v
|
| 173 |
|
|
$(VLOG) $(UART_INC) $(UART_SRC)/uart_top.v
|
| 174 |
|
|
tc:
|
| 175 |
|
|
$(VLOG) $(TC_INC) $(TC_SRC)/tc_top.v
|
| 176 |
|
|
wb_dma:
|
| 177 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_top.v
|
| 178 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_rf.v
|
| 179 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_ch_rf.v
|
| 180 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_ch_sel.v
|
| 181 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_ch_pri_enc.v
|
| 182 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_ch_arb.v
|
| 183 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_de.v
|
| 184 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_inc30r.v
|
| 185 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_pri_enc_sub.v
|
| 186 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_wb_if.v
|
| 187 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_wb_mast.v
|
| 188 |
|
|
$(VLOG) $(WB_DMA_INC) $(WB_DMA_SRC)/wb_dma_wb_slv.v
|
| 189 |
|
|
or1200:
|
| 190 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_iwb_biu.v
|
| 191 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_wb_biu.v
|
| 192 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_ctrl.v
|
| 193 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_cpu.v
|
| 194 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_rf.v
|
| 195 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_rfram_generic.v
|
| 196 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_alu.v
|
| 197 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_lsu.v
|
| 198 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_operandmuxes.v
|
| 199 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_wbmux.v
|
| 200 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_genpc.v
|
| 201 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_if.v
|
| 202 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_freeze.v
|
| 203 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_sprs.v
|
| 204 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_top.v
|
| 205 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_pic.v
|
| 206 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_pm.v
|
| 207 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_tt.v
|
| 208 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_except.v
|
| 209 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_dc_top.v
|
| 210 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_dc_fsm.v
|
| 211 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_reg2mem.v
|
| 212 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_mem2reg.v
|
| 213 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_dc_tag.v
|
| 214 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_dc_ram.v
|
| 215 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_ic_top.v
|
| 216 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_ic_fsm.v
|
| 217 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_ic_tag.v
|
| 218 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_ic_ram.v
|
| 219 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_immu_top.v
|
| 220 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_immu_tlb.v
|
| 221 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_dmmu_top.v
|
| 222 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_dmmu_tlb.v
|
| 223 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_amultp2_32x32.v
|
| 224 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_gmultp2_32x32.v
|
| 225 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_cfgr.v
|
| 226 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_du.v
|
| 227 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_sb.v
|
| 228 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_sb_fifo.v
|
| 229 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_mult_mac.v
|
| 230 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_qmem_top.v
|
| 231 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_dpram_32x32.v
|
| 232 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_2048x32.v
|
| 233 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_2048x32_bw.v
|
| 234 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_2048x8.v
|
| 235 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_512x20.v
|
| 236 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_256x21.v
|
| 237 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_1024x8.v
|
| 238 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_1024x32.v
|
| 239 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_1024x32_bw.v
|
| 240 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_64x14.v
|
| 241 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_64x22.v
|
| 242 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_64x24.v
|
| 243 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_xcv_ram32x8d.v
|
| 244 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_128x32.v
|
| 245 |
|
|
$(VLOG) $(OR1200_INC) $(OR1200_SRC)/or1200_spram_32x24.v
|
| 246 |
|
|
tessera:
|
| 247 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/tessera_vga.v
|
| 248 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/tessera_ram_data.v
|
| 249 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/tessera_ram_vect.v
|
| 250 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/tessera_ram_tiny.v
|
| 251 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/tessera_sdram.v
|
| 252 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/tessera_mem.v
|
| 253 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/tessera_core.v
|
| 254 |
|
|
#$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/tessera_tic.v
|
| 255 |
|
|
$(VLOG) $(TESSERA_INC) +define+SIM $(TESSERA_SRC)/tessera_tic.v
|
| 256 |
|
|
$(VLOG) $(TESSERA_INC) $(TESSERA_SRC)/tessera_top.v
|
| 257 |
|
|
|
| 258 |
|
|
|
