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[/] [klc32/] [trunk/] [bench/] [KLC32_tb.v] - Blame information for rev 14

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1 8 robfinch
// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// KLC32 - 32 bit CPU
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// KLC32_tb - testbench for KLC32
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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module KLC32_tb();
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reg clk;
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reg rst;
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wire sys_inta;
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wire [2:0] sys_fc;
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wire sys_cyc;
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wire sys_stb;
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wire sys_we;
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wire [3:0] sys_sel;
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wire [31:0] sys_adr;
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wire [31:0] sys_dbo;
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wire [31:0] sys_dbi;
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wire sys_rst;
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reg [31:0] romout;
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wire sys_ack;
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wire [31:0] ram_dbo;
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wire [31:0] stk_dbo;
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reg nmi;
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assign sys_ack = sys_stb;
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wire ram_cs = sys_adr < 32'h0010000 || sys_adr[32:16]==16'hFFD0;
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wire stk_cs = sys_adr[31:16]==16'hFFFE;
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initial begin
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        clk = 1;
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        rst = 0;
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        #100 rst = 1;
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        #100 rst = 0;
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end
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always #6.8 clk = ~clk; //  73.529 MHz
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always @(sys_adr)
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casex(sys_adr & 32'hFFFFFFFC)
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32'h00000000:   romout <= 32'hFFFE_07FC;        // initial SP   
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32'h00000004:   romout <= 32'hFFFF_0000;        // initial PC
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32'h0000xxxx:   romout <= ram_dbo;
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32'hFFFF0000:   romout <= 32'h00000034;         // RST
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32'hFFFF0004:   romout <= 32'h24018000;         // ORI R1,R0,#$FFD00000
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32'hFFFF0008:   romout <= 32'hFFD00000;
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32'hFFFF000C:   romout <= 32'h24020005;         // ORI R2,R0,#5
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32'hFFFF0010:   romout <= 32'h24030020;         // ORI R3,R0,#32
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// J1:
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32'hFFFF0014:   romout <= 32'hE4230000;         // SH R3,(R1)
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32'hFFFF0018:   romout <= 32'h10210002;         // ADDI R1,R1,#2
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32'hFFFF001C:   romout <= 32'h14420001;         // SUBI R2,R2,#1
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32'hFFFF0020:   romout <= 32'h4006FFF0;         // BNE CR0,J1
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32'hFFFExxxx:   romout <= stk_dbo;
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endcase
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assign sys_dbi = romout;
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KLC32 u1
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(
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        .rst_i(rst),
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        .clk_i(clk),
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        .halt_i(1'b0),
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        .ipl_i(3'b000),
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        .vpa_i(1'b0),
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        .err_i(1'b0),
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        .inta_o(sys_inta),
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        .fc_o(sys_fc),
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        .rst_o(sys_rst),
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        .cyc_o(sys_cyc),
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        .stb_o(sys_stb),
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        .ack_i(sys_ack),
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        .we_o(sys_we),
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        .sel_o(sys_sel),
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        .adr_o(sys_adr),
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        .dat_i(sys_dbi),
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        .dat_o(sys_dbo)
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);
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fict_ram u2 (clk, ram_cs, sys_we, sys_sel, sys_adr[17:0],sys_dbo,ram_dbo);
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fict_ram u3 (clk, stk_cs, sys_we, sys_sel, sys_adr[17:0],sys_dbo,stk_dbo);
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endmodule
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module fict_ram(clk, cs, we, sel_i, adr, dat_i, dat_o);
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input clk;
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input cs;
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input we;
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input [3:0] sel_i;
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input [17:0] adr;
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input [31:0] dat_i;
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output [31:0] dat_o;
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reg [31:0] mem [65535:0];
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always @(posedge clk)
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begin
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        if (cs & we) begin
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                $display("Wrote mem[%h] with %h", adr, dat_i);
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                if (sel_i[0]) mem[adr[17:2]][ 7: 0] <= dat_i[ 7: 0];
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                if (sel_i[1]) mem[adr[17:2]][15: 8] <= dat_i[15: 8];
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                if (sel_i[2]) mem[adr[17:2]][23:16] <= dat_i[23:16];
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                if (sel_i[3]) mem[adr[17:2]][31:24] <= dat_i[31:24];
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        end
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end
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assign dat_o = mem[adr[17:2]];
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endmodule
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