OpenCores
URL https://opencores.org/ocsvn/klc32/klc32/trunk

Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [BCDMath.v] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 robfinch
 
2
 
3
module BCDAdd(ci,a,b,o,c);
4
input ci;               // carry input
5
input [7:0] a;
6
input [7:0] b;
7
output [7:0] o;
8
output c;
9
 
10
wire c0,c1;
11
 
12
wire [4:0] hsN0 = a[3:0] + b[3:0] + ci;
13
wire [4:0] hsN1 = a[7:4] + b[7:4] + c0;
14
 
15
BCDAddAdjust u1 (hsN0,o[3:0],c0);
16
BCDAddAdjust u2 (hsN1,o[7:4],c);
17
 
18
endmodule
19
 
20
module BCDSub(ci,a,b,o,c);
21
input ci;               // carry input
22
input [7:0] a;
23
input [7:0] b;
24
output [7:0] o;
25
output c;
26
 
27
wire c0,c1;
28
 
29
wire [4:0] hdN0 = a[3:0] - b[3:0] - ci;
30
wire [4:0] hdN1 = a[7:4] - b[7:4] - c0;
31
 
32
BCDSubAdjust u1 (hdN0,o[3:0],c0);
33
BCDSubAdjust u2 (hdN1,o[7:4],c);
34
 
35
endmodule
36
 
37
module BCDAddAdjust(i,o,c);
38
input [4:0] i;
39
output [3:0] o;
40
reg [3:0] o;
41
output c;
42
reg c;
43
always @(i)
44
case(i)
45
5'h0: begin o = 4'h0; c = 1'b0; end
46
5'h1: begin o = 4'h1; c = 1'b0; end
47
5'h2: begin o = 4'h2; c = 1'b0; end
48
5'h3: begin o = 4'h3; c = 1'b0; end
49
5'h4: begin o = 4'h4; c = 1'b0; end
50
5'h5: begin o = 4'h5; c = 1'b0; end
51
5'h6: begin o = 4'h6; c = 1'b0; end
52
5'h7: begin o = 4'h7; c = 1'b0; end
53
5'h8: begin o = 4'h8; c = 1'b0; end
54
5'h9: begin o = 4'h9; c = 1'b0; end
55
5'hA: begin o = 4'h0; c = 1'b1; end
56
5'hB: begin o = 4'h1; c = 1'b1; end
57
5'hC: begin o = 4'h2; c = 1'b1; end
58
5'hD: begin o = 4'h3; c = 1'b1; end
59
5'hE: begin o = 4'h4; c = 1'b1; end
60
5'hF: begin o = 4'h5; c = 1'b1; end
61
5'h10:  begin o = 4'h6; c = 1'b1; end
62
5'h11:  begin o = 4'h7; c = 1'b1; end
63
5'h12:  begin o = 4'h8; c = 1'b1; end
64
default:        begin o = 4'h9; c = 1'b1; end
65
endcase
66
endmodule
67
 
68
module BCDSubAdjust(i,o,c);
69
input [4:0] i;
70
output [3:0] o;
71
reg [3:0] o;
72
output c;
73
reg c;
74
always @(i)
75
case(i)
76
5'h0: begin o = 4'h0; c = 1'b0; end
77
5'h1: begin o = 4'h1; c = 1'b0; end
78
5'h2: begin o = 4'h2; c = 1'b0; end
79
5'h3: begin o = 4'h3; c = 1'b0; end
80
5'h4: begin o = 4'h4; c = 1'b0; end
81
5'h5: begin o = 4'h5; c = 1'b0; end
82
5'h6: begin o = 4'h6; c = 1'b0; end
83
5'h7: begin o = 4'h7; c = 1'b0; end
84
5'h8: begin o = 4'h8; c = 1'b0; end
85
5'h9: begin o = 4'h9; c = 1'b0; end
86
5'h17: begin o = 4'h1; c = 1'b1; end
87
5'h18: begin o = 4'h2; c = 1'b1; end
88
5'h19: begin o = 4'h3; c = 1'b1; end
89
5'h1A: begin o = 4'h4; c = 1'b1; end
90
5'h1B: begin o = 4'h5; c = 1'b1; end
91
5'h1C: begin o = 4'h6; c = 1'b1; end
92
5'h1D: begin o = 4'h7; c = 1'b1; end
93
5'h1E: begin o = 4'h8; c = 1'b1; end
94
5'h1F: begin o = 4'h9; c = 1'b1; end
95
default: begin o = 4'h9; c = 1'b1; end
96
endcase
97
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.