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https://opencores.org/ocsvn/klc32/klc32/trunk
[/] [klc32/] [trunk/] [rtl/] [verilog/] [IFETCH.v] - Blame information for rev 2
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robfinch |
// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// KLC32 - 32 bit CPU
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// IFETCH.v - fetch instructions
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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IFETCH:
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if (!cyc_o) begin
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if (halt_i) begin
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// empty - do nothing until non-halted
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end
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else if (nmi_edge) begin
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sr1 <= sr;
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im <= ipl_i;
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tf <= 1'b0;
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sf <= 1'b1;
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iplr <= 3'd7;
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nmi_edge <= 1'b0;
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state <= INTA;
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end
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else if (ipl_i > im) begin
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sr1 <= sr;
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im <= ipl_i;
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tf <= 1'b0;
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sf <= 1'b1;
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iplr <= ipl_i;
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state <= INTA;
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end
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else if (tf) begin
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sr1 <= sr;
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tf <= 1'b0;
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sf <= 1'b1;
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vector <= `TRACE_VECTOR;
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state <= TRAP;
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end
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else begin
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fc_o <= {sf,2'b10};
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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sel_o <= 4'b1111;
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adr_o <= pc;
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end
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end
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else if (ack_i) begin
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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pc <= pc + 32'd4;
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ir <= dat_i;
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Rn <= dat_i[25:21];
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state <= REGFETCHA;
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end
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else if (err_i) begin
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'b0000;
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vector <= `BUS_ERR_VECTOR;
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state <= TRAP;
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end
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