URL
https://opencores.org/ocsvn/klc32/klc32/trunk
[/] [klc32/] [trunk/] [rtl/] [verilog/] [JSR.v] - Blame information for rev 2
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
2 |
robfinch |
// ============================================================================
|
| 2 |
|
|
// (C) 2011 Robert Finch
|
| 3 |
|
|
// All Rights Reserved.
|
| 4 |
|
|
// robfinch<remove>@opencores.org
|
| 5 |
|
|
//
|
| 6 |
|
|
// KLC32 - 32 bit CPU
|
| 7 |
|
|
// JSR.v - jump to subroutine
|
| 8 |
|
|
//
|
| 9 |
|
|
// This source file is free software: you can redistribute it and/or modify
|
| 10 |
|
|
// it under the terms of the GNU Lesser General Public License as published
|
| 11 |
|
|
// by the Free Software Foundation, either version 3 of the License, or
|
| 12 |
|
|
// (at your option) any later version.
|
| 13 |
|
|
//
|
| 14 |
|
|
// This source file is distributed in the hope that it will be useful,
|
| 15 |
|
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 16 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 17 |
|
|
// GNU General Public License for more details.
|
| 18 |
|
|
//
|
| 19 |
|
|
// You should have received a copy of the GNU General Public License
|
| 20 |
|
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
| 21 |
|
|
//
|
| 22 |
|
|
// ============================================================================
|
| 23 |
|
|
//
|
| 24 |
|
|
JSR32:
|
| 25 |
|
|
if (!cyc_o) begin
|
| 26 |
|
|
fc_o <= {sf,2'b10};
|
| 27 |
|
|
cyc_o <= 1'b1;
|
| 28 |
|
|
stb_o <= 1'b1;
|
| 29 |
|
|
sel_o <= 4'b1111;
|
| 30 |
|
|
adr_o <= pc;
|
| 31 |
|
|
end
|
| 32 |
|
|
else if (ack_i) begin
|
| 33 |
|
|
cyc_o <= 1'b0;
|
| 34 |
|
|
stb_o <= 1'b0;
|
| 35 |
|
|
sel_o <= 4'b0000;
|
| 36 |
|
|
pc <= pc + 32'd4;
|
| 37 |
|
|
tgt <= dat_i;
|
| 38 |
|
|
state <= JSR1;
|
| 39 |
|
|
end
|
| 40 |
|
|
else if (err_i) begin
|
| 41 |
|
|
cyc_o <= 1'b0;
|
| 42 |
|
|
stb_o <= 1'b0;
|
| 43 |
|
|
sel_o <= 4'b0000;
|
| 44 |
|
|
vector <= `BUS_ERR_VECTOR;
|
| 45 |
|
|
state <= TRAP;
|
| 46 |
|
|
end
|
| 47 |
|
|
JSR1:
|
| 48 |
|
|
if (!cyc_o) begin
|
| 49 |
|
|
fc_o <= {sf,2'b01};
|
| 50 |
|
|
cyc_o <= 1'b1;
|
| 51 |
|
|
stb_o <= 1'b1;
|
| 52 |
|
|
we_o <= 1'b1;
|
| 53 |
|
|
sel_o <= 4'b1111;
|
| 54 |
|
|
if (sf)
|
| 55 |
|
|
adr_o <= ssp - 32'd4;
|
| 56 |
|
|
else
|
| 57 |
|
|
adr_o <= usp - 32'd4;
|
| 58 |
|
|
dat_o <= pc;
|
| 59 |
|
|
end
|
| 60 |
|
|
else if (ack_i) begin
|
| 61 |
|
|
cyc_o <= 1'b0;
|
| 62 |
|
|
stb_o <= 1'b0;
|
| 63 |
|
|
we_o <= 1'b0;
|
| 64 |
|
|
sel_o <= 4'b0000;
|
| 65 |
|
|
if (sf)
|
| 66 |
|
|
ssp <= ssp - 32'd4;
|
| 67 |
|
|
else
|
| 68 |
|
|
usp <= usp - 32'd4;
|
| 69 |
|
|
pc <= tgt;
|
| 70 |
|
|
state <= IFETCH;
|
| 71 |
|
|
end
|
| 72 |
|
|
else if (err_i) begin
|
| 73 |
|
|
cyc_o <= 1'b0;
|
| 74 |
|
|
stb_o <= 1'b0;
|
| 75 |
|
|
we_o <= 1'b0;
|
| 76 |
|
|
sel_o <= 4'b0000;
|
| 77 |
|
|
vector <= `BUS_ERR_VECTOR;
|
| 78 |
|
|
state <= TRAP;
|
| 79 |
|
|
end
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.