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[/] [klc32/] [trunk/] [rtl/] [verilog/] [KLC32.v] - Blame information for rev 10

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// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// KLC32.v
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//  - 32 bit CPU
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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`define STACK_VECTOR    32'h00000000
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`define RESET_VECTOR    32'h00000004
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`define NMI_VECTOR              32'h0000007C
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`define IRQ_VECTOR              32'h00000064
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`define TRAP_VECTOR             32'h00000080
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`define TRAPV_VECTOR    32'h0000001C
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`define TRACE_VECTOR    32'h00000024
31
`define BUS_ERR_VECTOR  32'h00000008
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`define ILLEGAL_INSN    32'h00000010
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`define PRIVILEGE_VIOLATION     32'h00000020
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35
`define MISC    6'd0
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`define JMP32           6'd32
37
`define JSR32           6'd33
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`define RTS                     6'd34
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`define RTI                     6'd35
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`define TRACE_ON        6'd48
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`define TRACE_OFF       6'd49
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`define USER_MODE       6'd50
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`define SET_IM          6'd51
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`define RST                     6'd52
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`define STOP            6'd53
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`define R               6'd1
47 10 robfinch
`define ABS                     6'd1
48 2 robfinch
`define SGN                     6'd2
49
`define NEG                     6'd3
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`define NOT                     6'd4
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`define EXTB            6'd5
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`define EXTH            6'd6
53 10 robfinch
`define UNLK            6'd24
54
`define MTSPR           6'd32
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`define MFSPR           6'd33
56 2 robfinch
`define MOV_CRn2CRn     6'd48
57
`define MOV_CRn2REG     6'd49
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`define MOV_REG2CRn     6'd50
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`define EXEC            6'd63
60
`define RR              6'd2
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`define ADD                     6'd4
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`define SUB                     6'd5
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`define CMP                     6'd6
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`define AND                     6'd8
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`define OR                      6'd9
66
`define EOR                     6'd10
67 10 robfinch
`define ANDC            6'd11
68 2 robfinch
`define NAND            6'd12
69
`define NOR                     6'd13
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`define ENOR            6'd14
71 10 robfinch
`define ORC                     6'd15
72 2 robfinch
`define SHL                     6'd16
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`define SHR                     6'd17
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`define ROL                     6'd18
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`define ROR                     6'd19
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`define JMP_RR          6'd20
77
`define JSR_RR          6'd21
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`define MAX                     6'd22
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`define MIN                     6'd23
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`define MULU            6'd24
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`define MULUH           6'd25
82 10 robfinch
`define MULS            6'd26
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`define MULSH           6'd27
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`define DIVU            6'd28
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`define DIVS            6'd29
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`define MODU            6'd30
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`define MODS            6'd31
88 2 robfinch
`define LWX                     6'd48
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`define LHX                     6'd49
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`define LBX                     6'd50
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`define LHUX            6'd51
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`define LBUX            6'd52
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`define SWX                     6'd56
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`define SHX                     6'd57
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`define SBX                     6'd58
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`define BCDADD          6'd60
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`define BCDSUB          6'd61
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`define RRR             6'd3
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`define ADDI    6'd4
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`define SUBI    6'd5
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`define CMPI    6'd6
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`define ANDI    6'd8
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`define ORI             6'd9
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`define EORI    6'd10
105 10 robfinch
`define MULUI   6'd12
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`define MULSI   6'd13
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`define DIVUI   6'd14
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`define DIVSI   6'd15
109 2 robfinch
`define Bcc             6'd16
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`define BRA                     4'd0
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`define BRN                     4'd1
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`define BHI                     4'd2
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`define BLS                     4'd3
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`define BHS                     4'd4
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`define BLO                     4'd5
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`define BNE                     4'd6
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`define BEQ                     4'd7
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`define BVC                     4'd8
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`define BVS                     4'd9
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`define BPL                     4'd10
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`define BMI                     4'd11
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`define BGE                     4'd12
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`define BLT                     4'd13
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`define BGT                     4'd14
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`define BLE                     4'd15
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`define TRAPcc  6'd17
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`define TRAP            4'd0
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`define TRN                     4'd1
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`define THI                     4'd2
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`define TLS                     4'd3
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`define THS                     4'd4
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`define TLO                     4'd5
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`define TNE                     4'd6
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`define TEQ                     4'd7
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`define TVC                     4'd8
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`define TVS                     4'd9
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`define TPL                     4'd10
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`define TMI                     4'd11
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`define TGE                     4'd12
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`define TLT                     4'd13
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`define TGT                     4'd14
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`define TLE                     4'd15
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`define SETcc   6'd18
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`define SET                     4'd0
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`define STN                     4'd1
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`define SHI                     4'd2
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`define SLS                     4'd3
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`define SHS                     4'd4
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`define SLO                     4'd5
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`define SNE                     4'd6
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`define SEQ                     4'd7
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`define SVC                     4'd8
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`define SVS                     4'd9
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`define SPL                     4'd10
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`define SMI                     4'd11
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`define SGE                     4'd12
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`define SLT                     4'd13
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`define SGT                     4'd14
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`define SLE                     4'd15
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`define CRxx    6'd19
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`define ANDI_CCR        5'd8
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`define ORI_CCR         5'd9
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`define EORI_CCR        5'd10
164 10 robfinch
`define CROR            10'd449
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`define CRORC           10'd417
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`define CRAND           10'd257
167
`define CRANDC          10'd129
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`define CRXOR           10'd193
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`define CRNOR           10'd33
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`define CRNAND          10'd225
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`define CRXNOR          10'd289
172 2 robfinch
`define JMP             6'd20
173
`define JSR             6'd21
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175
`define TAS             6'd46
176
`define LW              6'd48
177
`define LH              6'd49
178
`define LB              6'd50
179
`define LHU             6'd51
180
`define LBU             6'd52
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`define POP             6'd53
182
`define LINK    6'd54
183
`define PEA             6'd55
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`define SW              6'd56
185
`define SH              6'd57
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`define SB              6'd58
187
`define PUSH    6'd59
188
`define NOP             6'd60
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190
module KLC32(rst_i, clk_i, ipl_i, vpa_i, halt_i, inta_o, fc_o, rst_o, cyc_o, stb_o, ack_i, err_i, sel_o, we_o, adr_o, dat_i, dat_o);
191
parameter IFETCH = 8'd1;
192
parameter REGFETCHA = 8'd2;
193
parameter REGFETCHB = 8'd3;
194
parameter EXECUTE = 8'd4;
195
parameter MEMORY1 = 8'd5;
196
parameter MEMORY1_ACK = 8'd6;
197
parameter WRITEBACK = 8'd7;
198
parameter JSR1 = 8'd10;
199
parameter JSR2 = 8'd11;
200
parameter JSRShort = 8'd12;
201
parameter RTS = 8'd13;
202
parameter JMP = 8'd14;
203
parameter LOAD_SP = 8'd15;
204
parameter VECTOR = 8'd16;
205
parameter INTA = 8'd20;
206
parameter FETCH_VECTOR = 8'd21;
207
parameter TRAP1 = 8'd22;
208
parameter TRAP2 = 8'd23;
209
parameter TRAP3 = 8'd24;
210
parameter RTI1 = 8'd25;
211
parameter RTI2 = 8'd26;
212
parameter RTI3 = 8'd27;
213
parameter TRAP = 8'd28;
214
parameter RESET = 8'd29;
215
parameter JSR32 = 8'd30;
216
parameter JMP32 = 8'd31;
217
parameter WRITE_FLAGS = 8'd32;
218
parameter FETCH_IMM32 = 8'd33;
219
parameter REGFETCHC = 8'd34;
220
parameter PUSH1 = 8'd35;
221
parameter PUSH2 = 8'd36;
222
parameter PUSH3 = 8'd37;
223
parameter POP1 = 8'd38;
224
parameter POP2 = 8'd39;
225
parameter POP3 = 8'd40;
226
parameter LINK = 8'd41;
227
parameter UNLK = 8'd42;
228
parameter TAS = 8'd43;
229
parameter TAS2 = 8'd44;
230
parameter PEA = 8'd45;
231 10 robfinch
parameter MULTDIV1 = 8'd49;
232
parameter MULTDIV2 = 8'd50;
233
parameter MULT1 = 8'd51;
234
parameter MULT2 = 8'd52;
235
parameter MULT3 = 8'd53;
236
parameter MULT4 = 8'd54;
237
parameter MULT5 = 8'd55;
238
parameter MULT6 = 8'd56;
239
parameter MULT7 = 8'd57;
240
parameter DIV1 = 8'd61;
241
parameter DIV2 = 8'd62;
242 2 robfinch
input rst_i;
243
input clk_i;
244
input [2:0] ipl_i;
245
input vpa_i;
246
input halt_i;
247
output inta_o;
248
reg inta_o;
249
output [2:0] fc_o;
250
reg [2:0] fc_o;
251
output rst_o;
252
output cyc_o;
253
reg cyc_o;
254
output stb_o;
255
reg stb_o;
256
input ack_i;
257
input err_i;
258
output we_o;
259
reg we_o;
260
output [3:0] sel_o;
261
reg [3:0] sel_o;
262
output [31:0] adr_o;
263
reg [31:0] adr_o;
264
input [31:0] dat_i;
265
output [31:0] dat_o;
266
reg [31:0] dat_o;
267
 
268 10 robfinch
reg cpu_clk_en;
269
reg clk_en;
270
wire clk;
271
 
272 2 robfinch
reg [7:0] state;
273
reg [31:0] ir;
274
reg tf,sf;
275
reg [31:0] pc;
276
reg [31:0] usp,ssp;
277 10 robfinch
reg [31:0] ctr;
278 2 robfinch
wire [5:0] opcode=ir[31:26];
279 10 robfinch
reg Rcbit;
280 2 robfinch
reg [5:0] mopcode;
281
wire [5:0] func=ir[5:0];
282 10 robfinch
wire [9:0] func1=ir[10:1];
283 2 robfinch
wire [3:0] cond=ir[19:16];
284
wire [31:0] brdisp = {{16{ir[15]}},ir[15:2],2'b0};
285
reg [4:0] Rn;
286
reg [31:0] regfile [31:0];
287
wire [31:0] rfo1 = regfile[Rn];
288
wire [31:0] rfo = (Rn==5'd0) ? 32'd0 : (Rn==5'd31) ? (sf ? ssp : usp) : rfo1;
289
reg vf,nf,cf,zf;
290 10 robfinch
reg xer_ov,xer_ca,xer_so;
291 2 robfinch
reg [2:0] im;
292
reg [2:0] iplr;
293
reg [7:0] vecnum;
294
reg [31:0] vector;
295
reg [31:0] ea;
296 10 robfinch
reg [15:0] rstsh;
297
assign rst_o = rstsh[15];
298 2 robfinch
reg prev_nmi;
299
reg nmi_edge;
300
reg [31:0] sr1;
301
reg [31:0] tgt;
302 10 robfinch
reg [31:0] a,b,c,imm,aa,bb;
303 2 robfinch
wire signed [31:0] as = a;
304
wire signed [31:0] bs = b;
305
reg [31:0] res;
306
reg [3:0] cr0,cr1,cr2,cr3,cr4,cr5,cr6,cr7;
307
wire [31:0] cr = {cr7,cr6,cr5,cr4,cr3,cr2,cr1,cr0};
308
wire [31:0] sr = {tf,1'b0,sf,2'b00,im,16'd0};
309
reg [31:0] tick;
310 10 robfinch
 
311
reg [5:0] cnt;
312
reg [31:0] div_r0;
313
reg [31:0] div_q0;
314
reg [31:0] div_q,div_r;
315
wire [32:0] div_dif = div_r0 - bb;
316
 
317 2 robfinch
wire IsSubi = opcode==`SUBI;
318
wire IsCmpi = opcode==`CMPI;
319
wire IsSub = opcode==`RR && func==`SUB;
320
wire IsCmp = opcode==`RR && func==`CMP;
321
wire IsNeg = opcode==`R && func==`NEG;
322 10 robfinch
wire IsDivi = opcode==`DIVUI || opcode==`DIVSI;
323
wire IsDivu = opcode==`DIVUI || (opcode==`RR && (func==`DIVU || func==`MODU));
324
wire IsMult = opcode==`MULUI || opcode==`MULSI || (opcode==`RR && (func==`MULU || func==`MULS || func==`MULUH || func==`MULSH));
325
wire IsDiv = opcode==`DIVUI || opcode==`DIVSI || (opcode==`RR && (func==`DIVU || func==`DIVS || func==`MODU || func==`MODS));
326 2 robfinch
 
327
wire hasConst16 =
328
        opcode==`ADDI || opcode==`SUBI || opcode==`CMPI ||
329
        opcode==`ANDI || opcode==`ORI || opcode==`EORI ||
330
        opcode==`LW || opcode==`LH || opcode==`LB || opcode==`LHU || opcode==`LBU ||
331
        opcode==`SW || opcode==`SH || opcode==`SB ||
332
        opcode==`PEA || opcode==`TAS || opcode==`LINK
333
        ;
334
wire isStop =
335
        opcode==`MISC && (func==`STOP)
336
        ;
337
 
338
wire c_ri,c_rr;
339
wire v_ri,v_rr;
340
carry u1 (.op(IsSubi|IsCmpi), .a(a[31]), .b(imm[31]), .s(res[31]), .c(c_ri));
341
carry u2 (.op(IsSub|IsCmp|IsNeg), .a(a[31]), .b(b[31]), .s(res[31]), .c(c_rr));
342
overflow u3 (.op(IsSubi|IsCmpi), .a(a[31]), .b(imm[31]), .s(res[31]), .v(v_ri));
343
overflow u4 (.op(IsSub|IsCmp|IsNeg), .a(a[31]), .b(b[31]), .s(res[31]), .v(v_rr));
344
 
345
wire [7:0] bcdaddo,bcdsubo;
346
wire bcdaddc,bcdsubc;
347
BCDAdd u5 (.ci(cr0[0]),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c(bcdaddc));
348
BCDSub u6 (.ci(cr0[0]),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c(bcdsubc));
349
 
350
wire [63:0] shlo = {32'd0,a} << b[4:0];
351
wire [63:0] shro = {a,32'd0} >> b[4:0];
352
 
353 10 robfinch
reg res_sgn;
354
wire [31:0] mp0 = aa[15:0] * bb[15:0];
355
wire [31:0] mp1 = aa[15:0] * bb[31:16];
356
wire [31:0] mp2 = aa[31:16] * bb[15:0];
357
wire [31:0] mp3 = aa[31:16] * bb[31:16];
358
reg [63:0] prod;
359
wire divByZero;
360
 
361 2 robfinch
function GetCrBit;
362
input [4:0] Rn;
363
begin
364
        case(Rn[4:2])
365
        3'd0:   GetCrBit = cr0[Rn[1:0]];
366
        3'd1:   GetCrBit = cr1[Rn[1:0]];
367
        3'd2:   GetCrBit = cr2[Rn[1:0]];
368
        3'd3:   GetCrBit = cr3[Rn[1:0]];
369
        3'd4:   GetCrBit = cr4[Rn[1:0]];
370
        3'd5:   GetCrBit = cr5[Rn[1:0]];
371
        3'd6:   GetCrBit = cr6[Rn[1:0]];
372
        3'd7:   GetCrBit = cr7[Rn[1:0]];
373
        endcase
374
end
375
endfunction
376
 
377
function [3:0] GetCr;
378
input [2:0] Rn;
379
begin
380
        case(Rn)
381
        3'd0:   GetCr = cr0;
382
        3'd1:   GetCr = cr1;
383
        3'd2:   GetCr = cr2;
384
        3'd3:   GetCr = cr3;
385
        3'd4:   GetCr = cr4;
386
        3'd5:   GetCr = cr5;
387
        3'd6:   GetCr = cr6;
388
        3'd7:   GetCr = cr7;
389
        endcase
390
end
391
endfunction
392
 
393 10 robfinch
wire [3:0] crc = GetCr(Rn[4:2]);
394 2 robfinch
wire cr_zf = crc[2];
395
wire cr_nf = crc[3];
396
wire cr_cf = crc[0];
397
wire cr_vf = crc[1];
398
 
399
//-----------------------------------------------------------------------------
400
// Clock control
401
// - reset or NMI reenables the clock
402
// - this circuit must be under the clk_i domain
403
//-----------------------------------------------------------------------------
404
//
405
BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );
406
 
407
always @(posedge clk_i)
408
if (rst_i) begin
409
        cpu_clk_en <= 1'b1;
410
end
411
else begin
412
        if (ipl_i==3'd7)
413
                cpu_clk_en <= 1'b1;
414
        else
415
                cpu_clk_en <= clk_en;
416
end
417
 
418
 
419
//-----------------------------------------------------------------------------
420
//-----------------------------------------------------------------------------
421
 
422
always @(posedge clk)
423
if (rst_i) begin
424
        prev_nmi <= 1'b0;
425
        nmi_edge <= 1'b0;
426
        state <= RESET;
427
        im <= 3'b111;
428
        sf <= 1'b1;
429
        tf <= 1'b0;
430
        inta_o <= 1'b0;
431
        cyc_o <= 1'b0;
432
        stb_o <= 1'b0;
433
        sel_o <= 4'b0000;
434
        we_o <= 1'b0;
435
        clk_en <= 1'b1;
436
        tick <= 32'd0;
437 10 robfinch
        rstsh <= 16'hFFFF;
438 2 robfinch
end
439
else begin
440
tick <= tick + 32'd1;
441
clk_en <= 1'b1;
442 10 robfinch
rstsh <= {rstsh,1'b0};
443 2 robfinch
prev_nmi <= ipl_i==3'd7;
444
if (!prev_nmi && (ipl_i==3'd7))
445
        nmi_edge <= 1'b1;
446
 
447
case(state)
448
`include "RESET.v"
449
`include "VECTOR.v"
450
`include "IFETCH.v"
451
 
452
`include "REGFETCHA.v"
453
`include "REGFETCHB.v"
454
`include "REGFETCHC.v"
455
`include "FETCH_IMM32.v"
456
`include "EXECUTE.v"
457
`include "MEMORY.v"
458
`include "PUSH.v"
459
`include "POP.v"
460
`include "WRITEBACK.v"
461
`include "WRITE_FLAGS.v"
462
 
463
`include "JMP.v"
464
`include "JSR.v"
465
`include "RTS.v"
466
`include "INTA.v"
467
`include "TRAP.v"
468
`include "RTI.v"
469
 
470 10 robfinch
`include "MULTDIV.v"
471
 
472 2 robfinch
endcase
473
end
474
 
475
endmodule

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