OpenCores
URL https://opencores.org/ocsvn/klc32/klc32/trunk

Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [KLC32.v] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch
// ============================================================================
2
// (C) 2011 Robert Finch
3
// All Rights Reserved.
4
// robfinch<remove>@opencores.org
5
//
6
// KLC32.v
7
//  - 32 bit CPU
8
//
9
// This source file is free software: you can redistribute it and/or modify 
10
// it under the terms of the GNU Lesser General Public License as published 
11
// by the Free Software Foundation, either version 3 of the License, or     
12
// (at your option) any later version.                                      
13
//                                                                          
14
// This source file is distributed in the hope that it will be useful,      
15
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
16
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
17
// GNU General Public License for more details.                             
18
//                                                                          
19
// You should have received a copy of the GNU General Public License        
20
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
21
//                                                                          
22
// ============================================================================
23
//
24
`define STACK_VECTOR    32'h00000000
25
`define RESET_VECTOR    32'h00000004
26
`define NMI_VECTOR              32'h0000007C
27
`define IRQ_VECTOR              32'h00000064
28
`define TRAP_VECTOR             32'h00000080
29
`define TRAPV_VECTOR    32'h0000001C
30
`define TRACE_VECTOR    32'h00000024
31
`define BUS_ERR_VECTOR  32'h00000008
32
`define ILLEGAL_INSN    32'h00000010
33
`define PRIVILEGE_VIOLATION     32'h00000020
34
 
35
`define MISC    6'd0
36
`define JMP32           6'd32
37
`define JSR32           6'd33
38
`define RTS                     6'd34
39
`define RTI                     6'd35
40
`define TRACE_ON        6'd48
41
`define TRACE_OFF       6'd49
42
`define USER_MODE       6'd50
43
`define SET_IM          6'd51
44
`define RST                     6'd52
45
`define STOP            6'd53
46
`define R               6'd1
47
`define ABS                     6'd4
48
`define SGN                     6'd2
49
`define NEG                     6'd3
50
`define NOT                     6'd4
51
`define EXTB            6'd5
52
`define EXTH            6'd6
53
`define MOV_REG2USP     6'd32
54
`define MOV_USP2REG     6'd33
55
`define MOV_CRn2CRn     6'd48
56
`define MOV_CRn2REG     6'd49
57
`define MOV_REG2CRn     6'd50
58
`define MOV_REG2CR      6'd51
59
`define MOV_CR2REG      6'd52
60
`define MOV_REG2IM      6'd53
61
`define MOV_IM2REG      6'd54
62
`define MFTICK          6'd55
63
`define MTLC            6'd56
64
`define MFLC            6'd57
65
`define EXEC            6'd63
66
`define RR              6'd2
67
`define ADD                     6'd4
68
`define SUB                     6'd5
69
`define CMP                     6'd6
70
`define AND                     6'd8
71
`define OR                      6'd9
72
`define EOR                     6'd10
73
`define NAND            6'd12
74
`define NOR                     6'd13
75
`define ENOR            6'd14
76
`define SHL                     6'd16
77
`define SHR                     6'd17
78
`define ROL                     6'd18
79
`define ROR                     6'd19
80
`define JMP_RR          6'd20
81
`define JSR_RR          6'd21
82
`define MAX                     6'd22
83
`define MIN                     6'd23
84
`define MULU            6'd24
85
`define MULUH           6'd25
86
`define CROR            6'd32
87
`define CRAND           6'd33
88
`define CRXOR           6'd34
89
`define CRNOR           6'd35
90
`define CRNAND          6'd36
91
`define CRXNOR          6'd37
92
`define LWX                     6'd48
93
`define LHX                     6'd49
94
`define LBX                     6'd50
95
`define LHUX            6'd51
96
`define LBUX            6'd52
97
`define SWX                     6'd56
98
`define SHX                     6'd57
99
`define SBX                     6'd58
100
`define BCDADD          6'd60
101
`define BCDSUB          6'd61
102
`define RRR             6'd3
103
`define ADDI    6'd4
104
`define SUBI    6'd5
105
`define CMPI    6'd6
106
`define ANDI    6'd8
107
`define ORI             6'd9
108
`define EORI    6'd10
109
`define Bcc             6'd16
110
`define BRA                     4'd0
111
`define BRN                     4'd1
112
`define BHI                     4'd2
113
`define BLS                     4'd3
114
`define BHS                     4'd4
115
`define BLO                     4'd5
116
`define BNE                     4'd6
117
`define BEQ                     4'd7
118
`define BVC                     4'd8
119
`define BVS                     4'd9
120
`define BPL                     4'd10
121
`define BMI                     4'd11
122
`define BGE                     4'd12
123
`define BLT                     4'd13
124
`define BGT                     4'd14
125
`define BLE                     4'd15
126
`define TRAPcc  6'd17
127
`define TRAP            4'd0
128
`define TRN                     4'd1
129
`define THI                     4'd2
130
`define TLS                     4'd3
131
`define THS                     4'd4
132
`define TLO                     4'd5
133
`define TNE                     4'd6
134
`define TEQ                     4'd7
135
`define TVC                     4'd8
136
`define TVS                     4'd9
137
`define TPL                     4'd10
138
`define TMI                     4'd11
139
`define TGE                     4'd12
140
`define TLT                     4'd13
141
`define TGT                     4'd14
142
`define TLE                     4'd15
143
`define SETcc   6'd18
144
`define SET                     4'd0
145
`define STN                     4'd1
146
`define SHI                     4'd2
147
`define SLS                     4'd3
148
`define SHS                     4'd4
149
`define SLO                     4'd5
150
`define SNE                     4'd6
151
`define SEQ                     4'd7
152
`define SVC                     4'd8
153
`define SVS                     4'd9
154
`define SPL                     4'd10
155
`define SMI                     4'd11
156
`define SGE                     4'd12
157
`define SLT                     4'd13
158
`define SGT                     4'd14
159
`define SLE                     4'd15
160
`define CRxx    6'd19
161
`define ANDI_CCR        5'd8
162
`define ORI_CCR         5'd9
163
`define EORI_CCR        5'd10
164
`define JMP             6'd20
165
`define JSR             6'd21
166
 
167
`define TAS             6'd46
168
`define UNLK    6'd47
169
`define LW              6'd48
170
`define LH              6'd49
171
`define LB              6'd50
172
`define LHU             6'd51
173
`define LBU             6'd52
174
`define POP             6'd53
175
`define LINK    6'd54
176
`define PEA             6'd55
177
`define SW              6'd56
178
`define SH              6'd57
179
`define SB              6'd58
180
`define PUSH    6'd59
181
`define NOP             6'd60
182
 
183
 
184
module KLC32(rst_i, clk_i, ipl_i, vpa_i, halt_i, inta_o, fc_o, rst_o, cyc_o, stb_o, ack_i, err_i, sel_o, we_o, adr_o, dat_i, dat_o);
185
parameter IFETCH = 8'd1;
186
parameter REGFETCHA = 8'd2;
187
parameter REGFETCHB = 8'd3;
188
parameter EXECUTE = 8'd4;
189
parameter MEMORY1 = 8'd5;
190
parameter MEMORY1_ACK = 8'd6;
191
parameter WRITEBACK = 8'd7;
192
parameter JSR1 = 8'd10;
193
parameter JSR2 = 8'd11;
194
parameter JSRShort = 8'd12;
195
parameter RTS = 8'd13;
196
parameter JMP = 8'd14;
197
parameter LOAD_SP = 8'd15;
198
parameter VECTOR = 8'd16;
199
parameter INTA = 8'd20;
200
parameter FETCH_VECTOR = 8'd21;
201
parameter TRAP1 = 8'd22;
202
parameter TRAP2 = 8'd23;
203
parameter TRAP3 = 8'd24;
204
parameter RTI1 = 8'd25;
205
parameter RTI2 = 8'd26;
206
parameter RTI3 = 8'd27;
207
parameter TRAP = 8'd28;
208
parameter RESET = 8'd29;
209
parameter JSR32 = 8'd30;
210
parameter JMP32 = 8'd31;
211
parameter WRITE_FLAGS = 8'd32;
212
parameter FETCH_IMM32 = 8'd33;
213
parameter REGFETCHC = 8'd34;
214
parameter PUSH1 = 8'd35;
215
parameter PUSH2 = 8'd36;
216
parameter PUSH3 = 8'd37;
217
parameter POP1 = 8'd38;
218
parameter POP2 = 8'd39;
219
parameter POP3 = 8'd40;
220
parameter LINK = 8'd41;
221
parameter UNLK = 8'd42;
222
parameter TAS = 8'd43;
223
parameter TAS2 = 8'd44;
224
parameter PEA = 8'd45;
225
input rst_i;
226
input clk_i;
227
input [2:0] ipl_i;
228
input vpa_i;
229
input halt_i;
230
output inta_o;
231
reg inta_o;
232
output [2:0] fc_o;
233
reg [2:0] fc_o;
234
output rst_o;
235
reg rst_o;
236
output cyc_o;
237
reg cyc_o;
238
output stb_o;
239
reg stb_o;
240
input ack_i;
241
input err_i;
242
output we_o;
243
reg we_o;
244
output [3:0] sel_o;
245
reg [3:0] sel_o;
246
output [31:0] adr_o;
247
reg [31:0] adr_o;
248
input [31:0] dat_i;
249
output [31:0] dat_o;
250
reg [31:0] dat_o;
251
 
252
reg [7:0] state;
253
reg [31:0] ir;
254
reg tf,sf;
255
reg [31:0] pc;
256
reg [31:0] usp,ssp;
257
reg [31:0] lc;
258
wire [5:0] opcode=ir[31:26];
259
reg [5:0] mopcode;
260
wire [5:0] func=ir[5:0];
261
wire [3:0] cond=ir[19:16];
262
wire [31:0] brdisp = {{16{ir[15]}},ir[15:2],2'b0};
263
reg [4:0] Rn;
264
reg [31:0] regfile [31:0];
265
wire [31:0] rfo1 = regfile[Rn];
266
wire [31:0] rfo = (Rn==5'd0) ? 32'd0 : (Rn==5'd31) ? (sf ? ssp : usp) : rfo1;
267
reg vf,nf,cf,zf;
268
reg [2:0] im;
269
reg [2:0] iplr;
270
reg [7:0] vecnum;
271
reg [31:0] vector;
272
reg [31:0] ea;
273
reg prev_nmi;
274
reg nmi_edge;
275
reg [31:0] sr1;
276
reg [31:0] tgt;
277
reg [31:0] a,b,c,imm;
278
wire signed [31:0] as = a;
279
wire signed [31:0] bs = b;
280
wire [63:0] muluo = a * b;
281
reg [31:0] res;
282
reg [3:0] cr0,cr1,cr2,cr3,cr4,cr5,cr6,cr7;
283
wire [31:0] cr = {cr7,cr6,cr5,cr4,cr3,cr2,cr1,cr0};
284
wire [31:0] sr = {tf,1'b0,sf,2'b00,im,16'd0};
285
reg [31:0] tick;
286
wire IsSubi = opcode==`SUBI;
287
wire IsCmpi = opcode==`CMPI;
288
wire IsSub = opcode==`RR && func==`SUB;
289
wire IsCmp = opcode==`RR && func==`CMP;
290
wire IsNeg = opcode==`R && func==`NEG;
291
 
292
wire hasConst16 =
293
        opcode==`ADDI || opcode==`SUBI || opcode==`CMPI ||
294
        opcode==`ANDI || opcode==`ORI || opcode==`EORI ||
295
        opcode==`LW || opcode==`LH || opcode==`LB || opcode==`LHU || opcode==`LBU ||
296
        opcode==`SW || opcode==`SH || opcode==`SB ||
297
        opcode==`PEA || opcode==`TAS || opcode==`LINK
298
        ;
299
wire isStop =
300
        opcode==`MISC && (func==`STOP)
301
        ;
302
wire isIllegalOpcode =
303
        (opcode >= 6'd22 && opcode <= 6'd45) || opcode==6'd7 ||
304
        (opcode >= 6'd12 && opcode <= 6'd15)
305
        ;
306
 
307
wire c_ri,c_rr;
308
wire v_ri,v_rr;
309
carry u1 (.op(IsSubi|IsCmpi), .a(a[31]), .b(imm[31]), .s(res[31]), .c(c_ri));
310
carry u2 (.op(IsSub|IsCmp|IsNeg), .a(a[31]), .b(b[31]), .s(res[31]), .c(c_rr));
311
overflow u3 (.op(IsSubi|IsCmpi), .a(a[31]), .b(imm[31]), .s(res[31]), .v(v_ri));
312
overflow u4 (.op(IsSub|IsCmp|IsNeg), .a(a[31]), .b(b[31]), .s(res[31]), .v(v_rr));
313
 
314
wire [7:0] bcdaddo,bcdsubo;
315
wire bcdaddc,bcdsubc;
316
BCDAdd u5 (.ci(cr0[0]),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c(bcdaddc));
317
BCDSub u6 (.ci(cr0[0]),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c(bcdsubc));
318
 
319
wire [63:0] shlo = {32'd0,a} << b[4:0];
320
wire [63:0] shro = {a,32'd0} >> b[4:0];
321
 
322
function GetCrBit;
323
input [4:0] Rn;
324
begin
325
        case(Rn[4:2])
326
        3'd0:   GetCrBit = cr0[Rn[1:0]];
327
        3'd1:   GetCrBit = cr1[Rn[1:0]];
328
        3'd2:   GetCrBit = cr2[Rn[1:0]];
329
        3'd3:   GetCrBit = cr3[Rn[1:0]];
330
        3'd4:   GetCrBit = cr4[Rn[1:0]];
331
        3'd5:   GetCrBit = cr5[Rn[1:0]];
332
        3'd6:   GetCrBit = cr6[Rn[1:0]];
333
        3'd7:   GetCrBit = cr7[Rn[1:0]];
334
        endcase
335
end
336
endfunction
337
 
338
function [3:0] GetCr;
339
input [2:0] Rn;
340
begin
341
        case(Rn)
342
        3'd0:   GetCr = cr0;
343
        3'd1:   GetCr = cr1;
344
        3'd2:   GetCr = cr2;
345
        3'd3:   GetCr = cr3;
346
        3'd4:   GetCr = cr4;
347
        3'd5:   GetCr = cr5;
348
        3'd6:   GetCr = cr6;
349
        3'd7:   GetCr = cr7;
350
        endcase
351
end
352
endfunction
353
 
354
wire [3:0] crc = GetCr(Rn);
355
wire cr_zf = crc[2];
356
wire cr_nf = crc[3];
357
wire cr_cf = crc[0];
358
wire cr_vf = crc[1];
359
 
360
//-----------------------------------------------------------------------------
361
// Clock control
362
// - reset or NMI reenables the clock
363
// - this circuit must be under the clk_i domain
364
//-----------------------------------------------------------------------------
365
//
366
reg cpu_clk_en;
367
reg clk_en;
368
wire clk;
369
BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );
370
 
371
always @(posedge clk_i)
372
if (rst_i) begin
373
        cpu_clk_en <= 1'b1;
374
end
375
else begin
376
        if (ipl_i==3'd7)
377
                cpu_clk_en <= 1'b1;
378
        else
379
                cpu_clk_en <= clk_en;
380
end
381
 
382
 
383
//-----------------------------------------------------------------------------
384
//-----------------------------------------------------------------------------
385
 
386
always @(posedge clk)
387
if (rst_i) begin
388
        prev_nmi <= 1'b0;
389
        nmi_edge <= 1'b0;
390
        state <= RESET;
391
        im <= 3'b111;
392
        sf <= 1'b1;
393
        tf <= 1'b0;
394
        inta_o <= 1'b0;
395
        cyc_o <= 1'b0;
396
        stb_o <= 1'b0;
397
        sel_o <= 4'b0000;
398
        we_o <= 1'b0;
399
        rst_o <= 1'b0;
400
        clk_en <= 1'b1;
401
        tick <= 32'd0;
402
end
403
else begin
404
tick <= tick + 32'd1;
405
clk_en <= 1'b1;
406
rst_o <= 1'b0;
407
prev_nmi <= ipl_i==3'd7;
408
if (!prev_nmi && (ipl_i==3'd7))
409
        nmi_edge <= 1'b1;
410
 
411
case(state)
412
`include "RESET.v"
413
`include "VECTOR.v"
414
`include "IFETCH.v"
415
 
416
`include "REGFETCHA.v"
417
`include "REGFETCHB.v"
418
`include "REGFETCHC.v"
419
`include "FETCH_IMM32.v"
420
`include "EXECUTE.v"
421
`include "MEMORY.v"
422
`include "PUSH.v"
423
`include "POP.v"
424
`include "WRITEBACK.v"
425
`include "WRITE_FLAGS.v"
426
 
427
`include "JMP.v"
428
`include "JSR.v"
429
`include "RTS.v"
430
`include "INTA.v"
431
`include "TRAP.v"
432
`include "RTI.v"
433
 
434
endcase
435
end
436
 
437
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.