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// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// MEMORY.v - memory operate instructions
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
MEMORY1:
        begin
                case(mopcode)
                `LW:    begin
                                fc_o <= {sf,2'b01};
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                sel_o <= 4'b1111;
                                adr_o <= ea;
                                state <= MEMORY1_ACK;
                                end
                `LH,`LHU:
                                begin
                                fc_o <= {sf,2'b01};
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                sel_o <= ea[1] ? 4'b1100 : 4'b0011;
                                adr_o <= ea;
                                state <= MEMORY1_ACK;
                                end
                `LB,`LBU:
                                begin
                                fc_o <= {sf,2'b01};
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                case(ea[1:0])
                                2'd0:   sel_o <= 4'b0001;
                                2'd1:   sel_o <= 4'b0010;
                                2'd2:   sel_o <= 4'b0100;
                                2'd3:   sel_o <= 4'b1000;
                                endcase
                                adr_o <= ea;
                                state <= MEMORY1_ACK;
                                end
                `SW:    begin
                                fc_o <= {sf,2'b01};
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                sel_o <= 4'b1111;
                                adr_o <= ea;
                                dat_o <= b;
                                state <= MEMORY1_ACK;
                                end
                `SH:    begin
                                fc_o <= {sf,2'b01};
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                sel_o <= ea[1] ? 4'b1100 : 4'b0011;
                                adr_o <= ea;
                                dat_o <= {2{b[15:0]}};
                                state <= MEMORY1_ACK;
                                end
                `SB:    begin
                                fc_o <= {sf,2'b01};
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                case(ea[1:0])
                                2'd0:   sel_o <= 4'b0001;
                                2'd1:   sel_o <= 4'b0010;
                                2'd2:   sel_o <= 4'b0100;
                                2'd3:   sel_o <= 4'b1000;
                                endcase
                                adr_o <= ea;
                                dat_o <= {4{b[7:0]}};
                                state <= MEMORY1_ACK;
                                end
                endcase
        end
MEMORY1_ACK:
        if (ack_i) begin
                case(mopcode)
                `LW:    begin
                                cyc_o <= 1'b0;
                                stb_o <= 1'b0;
                                sel_o <= 4'b0000;
                                res <= dat_i;
                                state <= WRITEBACK;
                                end
                `LH:    begin
                                cyc_o <= 1'b0;
                                stb_o <= 1'b0;
                                sel_o <= 4'b0000;
                                if (sel_o==4'b0011)
                                        res <= {{16{dat_i[15]}},dat_i[15:0]};
                                else
                                        res <= {{16{dat_i[31]}},dat_i[31:16]};
                                state <= WRITEBACK;
                                end
                `LHU:   begin
                                cyc_o <= 1'b0;
                                stb_o <= 1'b0;
                                sel_o <= 4'b0000;
                                if (sel_o==4'b0011)
                                        res <= {16'd0,dat_i[15:0]};
                                else
                                        res <= {16'd0,dat_i[31:16]};
                                state <= WRITEBACK;
                                end
                `LB:    begin
                                cyc_o <= 1'b0;
                                stb_o <= 1'b0;
                                sel_o <= 4'b0000;
                                case(sel_o)
                                4'b0001:        res <= {{24{dat_i[7]}},dat_i[7:0]};
                                4'b0010:        res <= {{24{dat_i[15]}},dat_i[15:8]};
                                4'b0100:        res <= {{24{dat_i[23]}},dat_i[23:16]};
                                4'b1000:        res <= {{24{dat_i[31]}},dat_i[31:24]};
                                endcase
                                state <= WRITEBACK;
                                end
                `LBU:   begin
                                cyc_o <= 1'b0;
                                stb_o <= 1'b0;
                                sel_o <= 4'b0000;
                                case(sel_o)
                                4'b0001:        res <= {24'd0,dat_i[7:0]};
                                4'b0010:        res <= {24'd0,dat_i[15:8]};
                                4'b0100:        res <= {24'd0,dat_i[23:16]};
                                4'b1000:        res <= {24'd0,dat_i[31:24]};
                                endcase
                                state <= WRITEBACK;
                                end
                `SW,`SH,`SB:
                                begin
                                cyc_o <= 1'b0;
                                stb_o <= 1'b0;
                                we_o <= 1'b0;
                                sel_o <= 4'b0000;
                                state <= IFETCH;
                                end
                endcase
        end
        else if (err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                vector <= `BUS_ERR_VECTOR;
                state <= TRAP;
        end
 
TAS:
        if (!cyc_o) begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= ea;
        end
        else if (ack_i) begin
                stb_o <= 1'b0;
                sel_o <= 4'b0000;
                res <= dat_i;
                state <= TAS2;
        end
        else if (err_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                vector <= `BUS_ERR_VECTOR;
                state <= TRAP;
        end
TAS2:
        if (!res[31]) begin
                if (!stb_o) begin
                        fc_o <= {sf,2'b01};
                        cyc_o <= 1'b1;
                        stb_o <= 1'b1;
                        we_o <= 1'b1;
                        sel_o <= 4'b1111;
                        adr_o <= ea;
                        dat_o <= {1'b1,res[30:0]};
                end
                else if (ack_i) begin
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        we_o <= 1'b0;
                        sel_o <= 4'b0000;
                        state <= WRITEBACK;
                end
                else if (err_i) begin
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        we_o <= 1'b0;
                        sel_o <= 4'b0000;
                        vector <= `BUS_ERR_VECTOR;
                        state <= TRAP;
                end
        end
        else begin
                cyc_o <= 1'b0;
                state <= WRITEBACK;
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// MEMORY.v - memory operate instructions`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`// ============================================================================`
23			`//`
24			`MEMORY1:`
25			`begin`
26			`case(mopcode)`
27			`LW: begin
28			`fc_o <= {sf,2'b01};`
29			`cyc_o <= 1'b1;`
30			`stb_o <= 1'b1;`
31			`sel_o <= 4'b1111;`
32			`adr_o <= ea;`
33			`state <= MEMORY1_ACK;`
34			`end`
35			`LH,`LHU:
36			`begin`
37			`fc_o <= {sf,2'b01};`
38			`cyc_o <= 1'b1;`
39			`stb_o <= 1'b1;`
40			`sel_o <= ea[1] ? 4'b1100 : 4'b0011;`
41			`adr_o <= ea;`
42			`state <= MEMORY1_ACK;`
43			`end`
44			`LB,`LBU:
45			`begin`
46			`fc_o <= {sf,2'b01};`
47			`cyc_o <= 1'b1;`
48			`stb_o <= 1'b1;`
49			`case(ea[1:0])`
50			`2'd0: sel_o <= 4'b0001;`
51			`2'd1: sel_o <= 4'b0010;`
52			`2'd2: sel_o <= 4'b0100;`
53			`2'd3: sel_o <= 4'b1000;`
54			`endcase`
55			`adr_o <= ea;`
56			`state <= MEMORY1_ACK;`
57			`end`
58			`SW: begin
59			`fc_o <= {sf,2'b01};`
60			`cyc_o <= 1'b1;`
61			`stb_o <= 1'b1;`
62			`we_o <= 1'b1;`
63			`sel_o <= 4'b1111;`
64			`adr_o <= ea;`
65			`dat_o <= b;`
66			`state <= MEMORY1_ACK;`
67			`end`
68			`SH: begin
69			`fc_o <= {sf,2'b01};`
70			`cyc_o <= 1'b1;`
71			`stb_o <= 1'b1;`
72			`we_o <= 1'b1;`
73			`sel_o <= ea[1] ? 4'b1100 : 4'b0011;`
74			`adr_o <= ea;`
75			`dat_o <= {2{b[15:0]}};`
76			`state <= MEMORY1_ACK;`
77			`end`
78			`SB: begin
79			`fc_o <= {sf,2'b01};`
80			`cyc_o <= 1'b1;`
81			`stb_o <= 1'b1;`
82			`we_o <= 1'b1;`
83			`case(ea[1:0])`
84			`2'd0: sel_o <= 4'b0001;`
85			`2'd1: sel_o <= 4'b0010;`
86			`2'd2: sel_o <= 4'b0100;`
87			`2'd3: sel_o <= 4'b1000;`
88			`endcase`
89			`adr_o <= ea;`
90			`dat_o <= {4{b[7:0]}};`
91			`state <= MEMORY1_ACK;`
92			`end`
93			`endcase`
94			`end`
95			`MEMORY1_ACK:`
96			`if (ack_i) begin`
97			`case(mopcode)`
98			`LW: begin
99			`cyc_o <= 1'b0;`
100			`stb_o <= 1'b0;`
101			`sel_o <= 4'b0000;`
102			`res <= dat_i;`
103			`state <= WRITEBACK;`
104			`end`
105			`LH: begin
106			`cyc_o <= 1'b0;`
107			`stb_o <= 1'b0;`
108			`sel_o <= 4'b0000;`
109			`if (sel_o==4'b0011)`
110			`res <= {{16{dat_i[15]}},dat_i[15:0]};`
111			`else`
112			`res <= {{16{dat_i[31]}},dat_i[31:16]};`
113			`state <= WRITEBACK;`
114			`end`
115			`LHU: begin
116			`cyc_o <= 1'b0;`
117			`stb_o <= 1'b0;`
118			`sel_o <= 4'b0000;`
119			`if (sel_o==4'b0011)`
120			`res <= {16'd0,dat_i[15:0]};`
121			`else`
122			`res <= {16'd0,dat_i[31:16]};`
123			`state <= WRITEBACK;`
124			`end`
125			`LB: begin
126			`cyc_o <= 1'b0;`
127			`stb_o <= 1'b0;`
128			`sel_o <= 4'b0000;`
129			`case(sel_o)`
130			`4'b0001: res <= {{24{dat_i[7]}},dat_i[7:0]};`
131			`4'b0010: res <= {{24{dat_i[15]}},dat_i[15:8]};`
132			`4'b0100: res <= {{24{dat_i[23]}},dat_i[23:16]};`
133			`4'b1000: res <= {{24{dat_i[31]}},dat_i[31:24]};`
134			`endcase`
135			`state <= WRITEBACK;`
136			`end`
137			`LBU: begin
138			`cyc_o <= 1'b0;`
139			`stb_o <= 1'b0;`
140			`sel_o <= 4'b0000;`
141			`case(sel_o)`
142			`4'b0001: res <= {24'd0,dat_i[7:0]};`
143			`4'b0010: res <= {24'd0,dat_i[15:8]};`
144			`4'b0100: res <= {24'd0,dat_i[23:16]};`
145			`4'b1000: res <= {24'd0,dat_i[31:24]};`
146			`endcase`
147			`state <= WRITEBACK;`
148			`end`
149			`SW,`SH,`SB:
150			`begin`
151			`cyc_o <= 1'b0;`
152			`stb_o <= 1'b0;`
153			`we_o <= 1'b0;`
154			`sel_o <= 4'b0000;`
155			`state <= IFETCH;`
156			`end`
157			`endcase`
158			`end`
159			`else if (err_i) begin`
160			`cyc_o <= 1'b0;`
161			`stb_o <= 1'b0;`
162			`we_o <= 1'b0;`
163			`sel_o <= 4'b0000;`
164			vector <= `BUS_ERR_VECTOR;
165			`state <= TRAP;`
166			`end`
167
168			`TAS:`
169			`if (!cyc_o) begin`
170			`fc_o <= {sf,2'b01};`
171			`cyc_o <= 1'b1;`
172			`stb_o <= 1'b1;`
173			`sel_o <= 4'b1111;`
174			`adr_o <= ea;`
175			`end`
176			`else if (ack_i) begin`
177			`stb_o <= 1'b0;`
178			`sel_o <= 4'b0000;`
179			`res <= dat_i;`
180			`state <= TAS2;`
181			`end`
182			`else if (err_i) begin`
183			`cyc_o <= 1'b0;`
184			`stb_o <= 1'b0;`
185			`we_o <= 1'b0;`
186			`sel_o <= 4'b0000;`
187			vector <= `BUS_ERR_VECTOR;
188			`state <= TRAP;`
189			`end`
190			`TAS2:`
191			`if (!res[31]) begin`
192			`if (!stb_o) begin`
193			`fc_o <= {sf,2'b01};`
194			`cyc_o <= 1'b1;`
195			`stb_o <= 1'b1;`
196			`we_o <= 1'b1;`
197			`sel_o <= 4'b1111;`
198			`adr_o <= ea;`
199			`dat_o <= {1'b1,res[30:0]};`
200			`end`
201			`else if (ack_i) begin`
202			`cyc_o <= 1'b0;`
203			`stb_o <= 1'b0;`
204			`we_o <= 1'b0;`
205			`sel_o <= 4'b0000;`
206			`state <= WRITEBACK;`
207			`end`
208			`else if (err_i) begin`
209			`cyc_o <= 1'b0;`
210			`stb_o <= 1'b0;`
211			`we_o <= 1'b0;`
212			`sel_o <= 4'b0000;`
213			vector <= `BUS_ERR_VECTOR;
214			`state <= TRAP;`
215			`end`
216			`end`
217			`else begin`
218			`cyc_o <= 1'b0;`
219			`state <= WRITEBACK;`
220			`end`
221

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[/] [klc32/] [trunk/] [rtl/] [verilog/] [MEMORY.v] - Blame information for rev 5