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[/] [klc32/] [trunk/] [rtl/] [verilog/] [MULTDIV.v] - Blame information for rev 10

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1 10 robfinch
// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// KLC32 - 32 bit CPU
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// MULTDIV.v
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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MULTDIV1:
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        begin
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                state <= IsMult ? MULT1 : DIV1;
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                cnt <= 6'd0;
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                case(opcode)
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                `RR:    // RR
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                        case(func)
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                        `MULS,`MULSH,`DIVS,`MODS:
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                                begin
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                                        aa <= a[31] ? -a : a;
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                                        bb <= b[31] ? -b : b;
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                                        res_sgn <= a[31] ^ b[31];
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                                end
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                        `MULU,`MULUH,`DIVU,`MODU:
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                                begin
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                                        aa <= a;
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                                        bb <= b;
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                                        res_sgn <= 1'b0;
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                                end
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                        endcase
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                `MULSI,`DIVSI:
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                        begin
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                                aa <= a[31] ? -a : a;
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                                bb <= imm[31] ? -imm : imm;
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                                res_sgn <= a[31] ^ imm[31];
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                        end
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                `MULUI,`DIVUI:
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                        begin
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                                aa <= a;
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                                bb <= imm;
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                                res_sgn <= 1'b0;
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                        end
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                endcase
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        end
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MULT1:  begin prod <= {mp3,mp0} + {mp1,16'd0}; state <= MULT2; end
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MULT2:  begin prod <= prod + {mp2,16'd0}; state <= res_sgn ? MULT6 : MULTDIV2; end
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MULT6:
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        begin
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                state <= MULTDIV2;
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                prod <= -prod;
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        end
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// Non-restoring divide
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DIV1:
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        if (cnt <= 32) begin
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                cnt <= cnt + 8'd1;
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                aa[0] <= ~div_dif[31];           // get test result
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                aa[31:1] <= aa[30:0];                    // shift quotient
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                div_r0[0] <= aa[31];                     // shift bit into test area (remainder)
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                if (~div_dif[31])
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                        div_r0[31:1] <= div_dif[31:0];
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                else
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                        div_r0[31:1] <= div_r0[30:0];
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        end
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        else
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                state <= DIV2;
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DIV2:
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        begin
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                state <= MULTDIV2;
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                if (res_sgn) begin
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                        div_q <= -aa;
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                        div_r <= -div_r0;
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                end
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                else begin
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                        div_q <= aa;
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                        div_r <= div_r0;
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                end
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        end
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MULTDIV2:
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        begin
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                state <= WRITEBACK;
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                case(opcode)
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                `RR:
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                        case(func)
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                        `MULU:  begin res <= prod[31:0]; vf <= |prod[63:32]; end
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                        `MULS:  begin res <= prod[31:0]; vf <= prod[31] ? ~&prod[63:32] : |prod[63:32]; end
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                        `MULUH: begin res <= prod[63:32]; end
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                        `MULSH: begin res <= prod[63:32]; end
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                        `DIVS:  res <= div_q;
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                        `DIVU:  res <= div_q;
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                        `MODS:  res <= div_r;
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                        `MODU:  res <= div_r;
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                        endcase
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                `MULSI: begin res <= prod[31:0]; vf <= prod[31] ? ~&prod[63:32] : |prod[63:32]; end
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                `MULUI: begin res <= prod[31:0]; vf <= |prod[63:32]; end
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                `DIVUI: res <= div_q;
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                `DIVSI: res <= div_q;
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                endcase
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        end

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