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[/] [klc32/] [trunk/] [rtl/] [verilog/] [PUSH.v] - Blame information for rev 12

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// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// PUSH.v - push type instructions
// PUSH / PEA / LINK
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
PUSH1:
        if (ir[25:1]==25'd0)
                state <= IFETCH;
        else begin
                Rn <= ir[25:21];
                ir[25:0] <= {ir[20:1],6'b0};
                if (ir[25:21]!=5'd0)
                        state <= PUSH2;
        end
PUSH2:
        begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;
                dat_o <= rfo;
                state <= PUSH3;
        end
PUSH3:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf)
                        ssp <= ssp - 32'd4;
                else
                        usp <= usp - 32'd4;
                state <= PUSH1;
        end
 
PEA:
        if (!cyc_o) begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;
                dat_o <= ea;
        end
        else if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf)
                        ssp <= ssp - 32'd4;
                else
                        usp <= usp - 32'd4;
                state <= IFETCH;
        end
 
LINK:
        if (!cyc_o) begin
                fc_o <= {sf,2'b01};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                sel_o <= 4'b1111;
                adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;
                dat_o <= a;
        end
        else if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'b0000;
                if (sf) begin
                        ssp <= ssp - 32'd4;
                        res <= ssp - 32'd4;
                end
                else begin
                        usp <= usp - 32'd4;
                        res <= usp - 32'd4;
                end
                state <= WRITEBACK;
        end

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// PUSH.v - push type instructions`
8			`// PUSH / PEA / LINK`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`// ============================================================================`
24			`//`
25			`PUSH1:`
26			`if (ir[25:1]==25'd0)`
27			`state <= IFETCH;`
28			`else begin`
29			`Rn <= ir[25:21];`
30			`ir[25:0] <= {ir[20:1],6'b0};`
31	10	robfinch	`if (ir[25:21]!=5'd0)`
32			`state <= PUSH2;`
33	2	robfinch	`end`
34			`PUSH2:`
35			`begin`
36			`fc_o <= {sf,2'b01};`
37			`cyc_o <= 1'b1;`
38			`stb_o <= 1'b1;`
39			`we_o <= 1'b1;`
40			`sel_o <= 4'b1111;`
41			`adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;`
42			`dat_o <= rfo;`
43			`state <= PUSH3;`
44			`end`
45			`PUSH3:`
46			`if (ack_i) begin`
47			`cyc_o <= 1'b0;`
48			`stb_o <= 1'b0;`
49			`we_o <= 1'b0;`
50			`sel_o <= 4'b0000;`
51			`if (sf)`
52			`ssp <= ssp - 32'd4;`
53			`else`
54			`usp <= usp - 32'd4;`
55			`state <= PUSH1;`
56			`end`
57
58			`PEA:`
59			`if (!cyc_o) begin`
60			`fc_o <= {sf,2'b01};`
61			`cyc_o <= 1'b1;`
62			`stb_o <= 1'b1;`
63			`we_o <= 1'b1;`
64			`sel_o <= 4'b1111;`
65			`adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;`
66			`dat_o <= ea;`
67			`end`
68			`else if (ack_i) begin`
69			`cyc_o <= 1'b0;`
70			`stb_o <= 1'b0;`
71			`we_o <= 1'b0;`
72			`sel_o <= 4'b0000;`
73			`if (sf)`
74			`ssp <= ssp - 32'd4;`
75			`else`
76			`usp <= usp - 32'd4;`
77			`state <= IFETCH;`
78			`end`
79
80			`LINK:`
81			`if (!cyc_o) begin`
82			`fc_o <= {sf,2'b01};`
83			`cyc_o <= 1'b1;`
84			`stb_o <= 1'b1;`
85			`we_o <= 1'b1;`
86			`sel_o <= 4'b1111;`
87			`adr_o <= sf ? ssp - 32'd4 : usp - 32'd4;`
88			`dat_o <= a;`
89			`end`
90			`else if (ack_i) begin`
91			`cyc_o <= 1'b0;`
92			`stb_o <= 1'b0;`
93			`we_o <= 1'b0;`
94			`sel_o <= 4'b0000;`
95			`if (sf) begin`
96			`ssp <= ssp - 32'd4;`
97			`res <= ssp - 32'd4;`
98			`end`
99			`else begin`
100			`usp <= usp - 32'd4;`
101			`res <= usp - 32'd4;`
102			`end`
103			`state <= WRITEBACK;`
104			`end`

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[/] [klc32/] [trunk/] [rtl/] [verilog/] [PUSH.v] - Blame information for rev 12