URL https://opencores.org/ocsvn/klc32/klc32/trunk

Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [REGFETCHA.v] - Blame information for rev 10

Details | Compare with Previous | View Log


// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// REGFETCHA.v - fetch register A / execute some instructions
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
REGFETCHA:
        begin
                Rcbit <= 1'b0;
                a <= rfo;
                b <= 32'd0;
                Rn <= ir[20:16];
                // RIX format ?
                if (hasConst16 && ir[15:0]==16'h8000)
                        state <= FETCH_IMM32;
                else begin
                        case(opcode)
                        `ANDI:  imm <= {16'hFFFF,ir[15:0]};
                        `ORI:   imm <= {16'h0000,ir[15:0]};
                        `EORI:  imm <= {16'h0000,ir[15:0]};
                        default:        imm <= {{16{ir[15]}},ir[15:0]};
                        endcase
                        state <= EXECUTE;
                end
                case(opcode)
                `MISC:
                        case(func)
                        `TRACE_ON:
                                        if (!sf) begin
                                                vector <= `PRIVILEGE_VIOLATION;
                                                state <= TRAP;
                                        end
                                        else begin
                                                tf <= 1'b1;
                                                state <= IFETCH;
                                        end
                        `TRACE_OFF:
                                        if (!sf) begin
                                                vector <= `PRIVILEGE_VIOLATION;
                                                state <= TRAP;
                                        end
                                        else begin
                                                tf <= 1'b0;
                                                state <= IFETCH;
                                        end
                        `SET_IM:
                                        if (!sf) begin
                                                vector <= `PRIVILEGE_VIOLATION;
                                                state <= TRAP;
                                        end
                                        else begin
                                                im <= ir[2:0];
                                                state <= IFETCH;
                                        end
                        `USER_MODE: begin sf <= 1'b0; state <= IFETCH; end
                        `JMP32: state <= JMP32;
                        `JSR32: state <= JSR32;
                        `RTS: state <= RTS;
                        `RTI:
                                if (!sf) begin
                                        vector <= `PRIVILEGE_VIOLATION;
                                        state <= TRAP;
                                end
                                else
                                        state <= RTI1;
                        `RST:
                                if (!sf) begin
                                        vector <= `PRIVILEGE_VIOLATION;
                                        state <= TRAP;
                                end
                                else begin
                                        rstsh <= 16'hFFFF;
                                        state <= IFETCH;
                                end
                        `STOP:
                                if (!sf) begin
                                        vector <= `PRIVILEGE_VIOLATION;
                                        state <= TRAP;
                                end
                                else begin
                                        im <= ir[8:6];
                                        tf <= ir[9];
                                        sf <= ir[10];
                                        clk_en <= 1'b0;
                                        state <= IFETCH;
                                end
                        default:
                                begin
                                vector <= `ILLEGAL_INSN;
                                state <= TRAP;
                                end
                        endcase
 
                `R:
                        begin
                                Rcbit <= ir[6];
                                case(func)
                                `UNLK:  state <= UNLK;
                                `ABS,`SGN,`NEG,`NOT,
                                `EXTB,`EXTH,
                                `MFSPR,`MTSPR,
                                `MOV_CRn2CRn,
                                `EXEC:
                                        ;
                                default:
                                        begin
                                        vector <= `ILLEGAL_INSN;
                                        state <= TRAP;
                                        end
                                endcase
                        end
 
                `NOP: state <= IFETCH;
                `JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
                `JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
                `Bcc:
                        case(cond)
                        `BRA:   begin pc <= pc + brdisp; state <= IFETCH; end
                        `BRN:   begin state <= IFETCH; end
                        `BEQ:   begin if ( cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BNE:   begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BMI:   begin if ( cr_nf) pc <= pc + brdisp; state <= IFETCH; end
                        `BPL:   begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BHI:   begin if (!cr_cf & !cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BLS:   begin if (cf |zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BHS:   begin if (!cr_cf) pc <= pc + brdisp; state <= IFETCH; end
                        `BLO:   begin if ( cr_cf) pc <= pc + brdisp; state <= IFETCH; end
                        `BGT:   begin if ((cr_nf & cr_vf & !cr_zf)|(!cr_nf & !cr_vf & !cr_zf)) pc <= pc + brdisp; state <= IFETCH; end
                        `BLE:   begin if (cr_zf | (cr_nf & !cr_vf) | (!cr_nf & cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
                        `BGE:   begin if ((cr_nf & cr_vf)|(!cr_nf & !cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
                        `BLT:   begin if ((cr_nf & !cr_vf)|(!cr_nf & cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
                        `BVS:   begin if ( cr_vf) pc <= pc + brdisp; state <= IFETCH; end
                        `BVC:   begin if (!cr_vf) pc <= pc + brdisp; state <= IFETCH; end
                        endcase
                `TRAPcc:
                        case(cond)
                        `TRAP:  begin vector <= `TRAP_VECTOR + {ir[3:0],2'b00}; state <= TRAP; end
                        `TEQ:   begin if ( cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TNE:   begin if (!cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TMI:   begin if ( cr_nf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TPL:   begin if (!cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `THI:   begin if (!cr_cf & !cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TLS:   begin if (cf |zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `THS:   begin if (!cr_cf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TLO:   begin if ( cr_cf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TGT:   begin if ((cr_nf & cr_vf & !cr_zf)|(!cr_nf & !cr_vf & !cr_zf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TLE:   begin if (cr_zf | (cr_nf & !cr_vf) | (!cr_nf & cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TGE:   begin if ((cr_nf & cr_vf)|(!cr_nf & !cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TLT:   begin if ((cr_nf & !cr_vf)|(!cr_nf & cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TVS:   begin if ( cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TVC:   begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        endcase
                `SETcc: Rn <= ir[15:11];
                `PUSH:  state <= PUSH1;
                `POP:   state <= POP1;
 
                `RR:
                        begin
                                state <= REGFETCHB;
                                Rcbit <= ir[6];
                                case(func)
                                `JSR_RR,`JMP_RR,
                                `ADD,`SUB,`CMP,
                                `BCDADD,`BCDSUB,
                                `AND,`OR,`EOR,`NAND,`NOR,`ENOR,
                                `SHL,`SHR,`ROL,`ROR,
                                `MULU,`MULS,`MULUH,`MULSH,`DIVU,`DIVS,`MODU,`MODS,
                                `LWX,`LHX,`LBX,`LHUX,`LBUX,`SWX,`SHX,`SBX,
                                `MIN,`MAX:
                                        ;
                                default:
                                        begin
                                        vector <= `ILLEGAL_INSN;
                                        state <= TRAP;
                                        end
                                endcase
                        end
 
                `RRR:
                        state <= REGFETCHB;
 
                `CRxx:
                        case(func1)
                        `CROR:
                                begin
                                        state <= IFETCH;
                                        case(ir[15:13])
                                        3'd0:   cr0[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
                                        3'd1:   cr1[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
                                        3'd2:   cr2[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
                                        3'd3:   cr3[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
                                        3'd4:   cr4[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
                                        3'd5:   cr5[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
                                        3'd6:   cr6[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
                                        3'd7:   cr7[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
                                        endcase
                                end
                        `CRORC:
                                begin
                                        state <= IFETCH;
                                        case(ir[15:13])
                                        3'd0:   cr0[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
                                        3'd1:   cr1[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
                                        3'd2:   cr2[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
                                        3'd3:   cr3[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
                                        3'd4:   cr4[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
                                        3'd5:   cr5[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
                                        3'd6:   cr6[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
                                        3'd7:   cr7[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
                                        endcase
                                end
                        `CRAND:
                                begin
                                        state <= IFETCH;
                                        case(ir[15:13])
                                        3'd0:   cr0[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
                                        3'd1:   cr1[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
                                        3'd2:   cr2[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
                                        3'd3:   cr3[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
                                        3'd4:   cr4[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
                                        3'd5:   cr5[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
                                        3'd6:   cr6[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
                                        3'd7:   cr7[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
                                        endcase
                                end
                        `CRANDC:
                                begin
                                        state <= IFETCH;
                                        case(ir[15:13])
                                        3'd0:   cr0[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
                                        3'd1:   cr1[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
                                        3'd2:   cr2[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
                                        3'd3:   cr3[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
                                        3'd4:   cr4[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
                                        3'd5:   cr5[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
                                        3'd6:   cr6[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
                                        3'd7:   cr7[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
                                        endcase
                                end
                        `CRXOR:
                                begin
                                        state <= IFETCH;
                                        case(ir[15:13])
                                        3'd0:   cr0[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
                                        3'd1:   cr1[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
                                        3'd2:   cr2[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
                                        3'd3:   cr3[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
                                        3'd4:   cr4[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
                                        3'd5:   cr5[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
                                        3'd6:   cr6[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
                                        3'd7:   cr7[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
                                        endcase
                                end
                        `CRNOR:
                                begin
                                        state <= IFETCH;
                                        case(ir[15:13])
                                        3'd0:   cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
                                        3'd1:   cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
                                        3'd2:   cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
                                        3'd3:   cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
                                        3'd4:   cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
                                        3'd5:   cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
                                        3'd6:   cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
                                        3'd7:   cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
                                        endcase
                                end
                        `CRNAND:
                                begin
                                        state <= IFETCH;
                                        case(ir[15:13])
                                        3'd0:   cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
                                        3'd1:   cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
                                        3'd2:   cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
                                        3'd3:   cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
                                        3'd4:   cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
                                        3'd5:   cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
                                        3'd6:   cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
                                        3'd7:   cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
                                        endcase
                                end
                        `CRXNOR:
                                begin
                                        state <= IFETCH;
                                        case(ir[15:13])
                                        3'd0:   cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
                                        3'd1:   cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
                                        3'd2:   cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
                                        3'd3:   cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
                                        3'd4:   cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
                                        3'd5:   cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
                                        3'd6:   cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
                                        3'd7:   cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
                                        endcase
                                end
                        default:
                                begin
                                vector <= `ILLEGAL_INSN;
                                state <= TRAP;
                                end
                        endcase
                `ADDI,`SUBI,`CMPI,
                `ANDI,`ORI,`EORI,
                `MULUI,`MULSI,`DIVUI,`DIVSI,
                `PEA,`LINK,`TAS,
                `LB,`LH,`LW,`LBU,`LHU:
                        ;       /* do nothing at this point */
                `SB,`SH,`SW:
                        state <= REGFETCHB;
                default:
                        begin
                        vector <= `ILLEGAL_INSN;
                        state <= TRAP;
                        end
                endcase
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// REGFETCHA.v - fetch register A / execute some instructions`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`// ============================================================================`
23			`//`
24			`REGFETCHA:`
25			`begin`
26	10	robfinch	`Rcbit <= 1'b0;`
27	2	robfinch	`a <= rfo;`
28			`b <= 32'd0;`
29			`Rn <= ir[20:16];`
30	10	robfinch	`// RIX format ?`
31			`if (hasConst16 && ir[15:0]==16'h8000)`
32			`state <= FETCH_IMM32;`
33	2	robfinch	`else begin`
34	10	robfinch	`case(opcode)`
35			`ANDI: imm <= {16'hFFFF,ir[15:0]};
36			`ORI: imm <= {16'h0000,ir[15:0]};
37			`EORI: imm <= {16'h0000,ir[15:0]};
38			`default: imm <= {{16{ir[15]}},ir[15:0]};`
39			`endcase`
40			`state <= EXECUTE;`
41	2	robfinch	`end`
42			`case(opcode)`
43			`MISC:
44			`case(func)`
45			`TRACE_ON:
46			`if (!sf) begin`
47			vector <= `PRIVILEGE_VIOLATION;
48			`state <= TRAP;`
49			`end`
50			`else begin`
51			`tf <= 1'b1;`
52			`state <= IFETCH;`
53			`end`
54			`TRACE_OFF:
55			`if (!sf) begin`
56			vector <= `PRIVILEGE_VIOLATION;
57			`state <= TRAP;`
58			`end`
59			`else begin`
60			`tf <= 1'b0;`
61			`state <= IFETCH;`
62			`end`
63			`SET_IM:
64			`if (!sf) begin`
65			vector <= `PRIVILEGE_VIOLATION;
66			`state <= TRAP;`
67			`end`
68			`else begin`
69			`im <= ir[2:0];`
70			`state <= IFETCH;`
71			`end`
72			`USER_MODE: begin sf <= 1'b0; state <= IFETCH; end
73			`JMP32: state <= JMP32;
74			`JSR32: state <= JSR32;
75			`RTS: state <= RTS;
76			`RTI:
77			`if (!sf) begin`
78			vector <= `PRIVILEGE_VIOLATION;
79			`state <= TRAP;`
80			`end`
81			`else`
82			`state <= RTI1;`
83			`RST:
84			`if (!sf) begin`
85			vector <= `PRIVILEGE_VIOLATION;
86			`state <= TRAP;`
87			`end`
88			`else begin`
89	10	robfinch	`rstsh <= 16'hFFFF;`
90	2	robfinch	`state <= IFETCH;`
91			`end`
92	10	robfinch	`STOP:
93			`if (!sf) begin`
94			vector <= `PRIVILEGE_VIOLATION;
95			`state <= TRAP;`
96			`end`
97			`else begin`
98			`im <= ir[8:6];`
99			`tf <= ir[9];`
100			`sf <= ir[10];`
101			`clk_en <= 1'b0;`
102			`state <= IFETCH;`
103			`end`
104			`default:`
105			`begin`
106			vector <= `ILLEGAL_INSN;
107			`state <= TRAP;`
108			`end`
109	2	robfinch	`endcase`
110	10	robfinch
111	7	robfinch	`R:
112	10	robfinch	`begin`
113			`Rcbit <= ir[6];`
114			`case(func)`
115			`UNLK: state <= UNLK;
116			`ABS,`SGN,`NEG,`NOT,
117			`EXTB,`EXTH,
118			`MFSPR,`MTSPR,
119			`MOV_CRn2CRn,
120			`EXEC:
121			`;`
122			`default:`
123			`begin`
124			vector <= `ILLEGAL_INSN;
125			`state <= TRAP;`
126			`end`
127			`endcase`
128			`end`
129
130	2	robfinch	`NOP: state <= IFETCH;
131			`JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
132			`JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
133			`Bcc:
134			`case(cond)`
135			`BRA: begin pc <= pc + brdisp; state <= IFETCH; end
136	10	robfinch	`BRN: begin state <= IFETCH; end
137	2	robfinch	`BEQ: begin if ( cr_zf) pc <= pc + brdisp; state <= IFETCH; end
138			`BNE: begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
139			`BMI: begin if ( cr_nf) pc <= pc + brdisp; state <= IFETCH; end
140			`BPL: begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
141			`BHI: begin if (!cr_cf & !cr_zf) pc <= pc + brdisp; state <= IFETCH; end
142			`BLS: begin if (cf \|zf) pc <= pc + brdisp; state <= IFETCH; end
143			`BHS: begin if (!cr_cf) pc <= pc + brdisp; state <= IFETCH; end
144			`BLO: begin if ( cr_cf) pc <= pc + brdisp; state <= IFETCH; end
145			`BGT: begin if ((cr_nf & cr_vf & !cr_zf)\|(!cr_nf & !cr_vf & !cr_zf)) pc <= pc + brdisp; state <= IFETCH; end
146			`BLE: begin if (cr_zf \| (cr_nf & !cr_vf) \| (!cr_nf & cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
147			`BGE: begin if ((cr_nf & cr_vf)\|(!cr_nf & !cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
148			`BLT: begin if ((cr_nf & !cr_vf)\|(!cr_nf & cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
149			`BVS: begin if ( cr_vf) pc <= pc + brdisp; state <= IFETCH; end
150			`BVC: begin if (!cr_vf) pc <= pc + brdisp; state <= IFETCH; end
151			`endcase`
152			`TRAPcc:
153			`case(cond)`
154			`TRAP: begin vector <= `TRAP_VECTOR + {ir[3:0],2'b00}; state <= TRAP; end
155			`TEQ: begin if ( cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
156			`TNE: begin if (!cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
157			`TMI: begin if ( cr_nf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
158			`TPL: begin if (!cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
159			`THI: begin if (!cr_cf & !cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
160			`TLS: begin if (cf \|zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
161			`THS: begin if (!cr_cf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
162			`TLO: begin if ( cr_cf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
163			`TGT: begin if ((cr_nf & cr_vf & !cr_zf)\|(!cr_nf & !cr_vf & !cr_zf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
164			`TLE: begin if (cr_zf \| (cr_nf & !cr_vf) \| (!cr_nf & cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
165			`TGE: begin if ((cr_nf & cr_vf)\|(!cr_nf & !cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
166			`TLT: begin if ((cr_nf & !cr_vf)\|(!cr_nf & cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
167			`TVS: begin if ( cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
168			`TVC: begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
169			`endcase`
170			`SETcc: Rn <= ir[15:11];
171			`PUSH: state <= PUSH1;
172			`POP: state <= POP1;
173	10	robfinch
174			`RR:
175			`begin`
176			`state <= REGFETCHB;`
177			`Rcbit <= ir[6];`
178			`case(func)`
179			`JSR_RR,`JMP_RR,
180			`ADD,`SUB,`CMP,
181			`BCDADD,`BCDSUB,
182			`AND,`OR,`EOR,`NAND,`NOR,`ENOR,
183			`SHL,`SHR,`ROL,`ROR,
184			`MULU,`MULS,`MULUH,`MULSH,`DIVU,`DIVS,`MODU,`MODS,
185			`LWX,`LHX,`LBX,`LHUX,`LBUX,`SWX,`SHX,`SBX,
186			`MIN,`MAX:
187			`;`
188			`default:`
189			`begin`
190			vector <= `ILLEGAL_INSN;
191			`state <= TRAP;`
192			`end`
193			`endcase`
194			`end`
195
196			`RRR:
197			`state <= REGFETCHB;`
198
199			`CRxx:
200			`case(func1)`
201			`CROR:
202			`begin`
203			`state <= IFETCH;`
204			`case(ir[15:13])`
205			`3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]);`
206			`3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]);`
207			`3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]);`
208			`3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]);`
209			`3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]);`
210			`3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]);`
211			`3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]);`
212			`3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]);`
213			`endcase`
214			`end`
215			`CRORC:
216			`begin`
217			`state <= IFETCH;`
218			`case(ir[15:13])`
219			`3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])\| ~GetCrBit(ir[20:16]);`
220			`3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])\| ~GetCrBit(ir[20:16]);`
221			`3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])\| ~GetCrBit(ir[20:16]);`
222			`3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])\| ~GetCrBit(ir[20:16]);`
223			`3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])\| ~GetCrBit(ir[20:16]);`
224			`3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])\| ~GetCrBit(ir[20:16]);`
225			`3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])\| ~GetCrBit(ir[20:16]);`
226			`3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])\| ~GetCrBit(ir[20:16]);`
227			`endcase`
228			`end`
229			`CRAND:
230			`begin`
231			`state <= IFETCH;`
232			`case(ir[15:13])`
233			`3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);`
234			`3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);`
235			`3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);`
236			`3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);`
237			`3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);`
238			`3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);`
239			`3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);`
240			`3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);`
241			`endcase`
242			`end`
243			`CRANDC:
244			`begin`
245			`state <= IFETCH;`
246			`case(ir[15:13])`
247			`3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);`
248			`3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);`
249			`3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);`
250			`3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);`
251			`3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);`
252			`3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);`
253			`3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);`
254			`3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);`
255			`endcase`
256			`end`
257			`CRXOR:
258			`begin`
259			`state <= IFETCH;`
260			`case(ir[15:13])`
261			`3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);`
262			`3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);`
263			`3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);`
264			`3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);`
265			`3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);`
266			`3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);`
267			`3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);`
268			`3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);`
269			`endcase`
270			`end`
271			`CRNOR:
272			`begin`
273			`state <= IFETCH;`
274			`case(ir[15:13])`
275			`3'd0: cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]));`
276			`3'd1: cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]));`
277			`3'd2: cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]));`
278			`3'd3: cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]));`
279			`3'd4: cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]));`
280			`3'd5: cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]));`
281			`3'd6: cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]));`
282			`3'd7: cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])\| GetCrBit(ir[20:16]));`
283			`endcase`
284			`end`
285			`CRNAND:
286			`begin`
287			`state <= IFETCH;`
288			`case(ir[15:13])`
289			`3'd0: cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));`
290			`3'd1: cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));`
291			`3'd2: cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));`
292			`3'd3: cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));`
293			`3'd4: cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));`
294			`3'd5: cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));`
295			`3'd6: cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));`
296			`3'd7: cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));`
297			`endcase`
298			`end`
299			`CRXNOR:
300			`begin`
301			`state <= IFETCH;`
302			`case(ir[15:13])`
303			`3'd0: cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));`
304			`3'd1: cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));`
305			`3'd2: cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));`
306			`3'd3: cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));`
307			`3'd4: cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));`
308			`3'd5: cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));`
309			`3'd6: cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));`
310			`3'd7: cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));`
311			`endcase`
312			`end`
313			`default:`
314			`begin`
315			vector <= `ILLEGAL_INSN;
316			`state <= TRAP;`
317			`end`
318			`endcase`
319			`ADDI,`SUBI,`CMPI,
320			`ANDI,`ORI,`EORI,
321			`MULUI,`MULSI,`DIVUI,`DIVSI,
322			`PEA,`LINK,`TAS,
323			`LB,`LH,`LW,`LBU,`LHU:
324			`; /* do nothing at this point */`
325			`SB,`SH,`SW:
326			`state <= REGFETCHB;`
327			`default:`
328			`begin`
329	2	robfinch	vector <= `ILLEGAL_INSN;
330			`state <= TRAP;`
331	10	robfinch	`end`
332			`endcase`
333	2	robfinch	`end`
334

Browse

Tools

Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [REGFETCHA.v] - Blame information for rev 10