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[/] [klc32/] [trunk/] [rtl/] [verilog/] [REGFETCHA.v] - Blame information for rev 4

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// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// REGFETCHA.v - fetch register A / execute some instructions
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
REGFETCHA:
        begin
                a <= rfo;
                b <= 32'd0;
                Rn <= ir[20:16];
                if (opcode==`RR || opcode==`RRR) begin
                        state <= REGFETCHB;
                end
                else begin
                        if ((hasConst16 && ir[15:0]==16'h8000) || (isStop))
                                state <= FETCH_IMM32;
                        else begin
                                imm <= {{16{ir[15]}},ir[15:0]};
                                state <= EXECUTE;
                        end
                end
                case(opcode)
                `MISC:
                        case(func)
                        `TRACE_ON:
                                        if (!sf) begin
                                                vector <= `PRIVILEGE_VIOLATION;
                                                state <= TRAP;
                                        end
                                        else begin
                                                tf <= 1'b1;
                                                state <= IFETCH;
                                        end
                        `TRACE_OFF:
                                        if (!sf) begin
                                                vector <= `PRIVILEGE_VIOLATION;
                                                state <= TRAP;
                                        end
                                        else begin
                                                tf <= 1'b0;
                                                state <= IFETCH;
                                        end
                        `SET_IM:
                                        if (!sf) begin
                                                vector <= `PRIVILEGE_VIOLATION;
                                                state <= TRAP;
                                        end
                                        else begin
                                                im <= ir[2:0];
                                                state <= IFETCH;
                                        end
                        `USER_MODE: begin sf <= 1'b0; state <= IFETCH; end
                        `JMP32: state <= JMP32;
                        `JSR32: state <= JSR32;
                        `RTS: state <= RTS;
                        `RTI:
                                if (!sf) begin
                                        vector <= `PRIVILEGE_VIOLATION;
                                        state <= TRAP;
                                end
                                else
                                        state <= RTI1;
                        `RST:
                                if (!sf) begin
                                        vector <= `PRIVILEGE_VIOLATION;
                                        state <= TRAP;
                                end
                                else begin
                                        rst_o <= 1'b1;
                                        state <= IFETCH;
                                end
                        endcase
                `NOP: state <= IFETCH;
                `JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
                `JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
                `Bcc:
                        case(cond)
                        `BRA:   begin pc <= pc + brdisp; state <= IFETCH; end
                        `BEQ:   begin if ( cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BNE:   begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BMI:   begin if ( cr_nf) pc <= pc + brdisp; state <= IFETCH; end
                        `BPL:   begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BHI:   begin if (!cr_cf & !cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BLS:   begin if (cf |zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BHS:   begin if (!cr_cf) pc <= pc + brdisp; state <= IFETCH; end
                        `BLO:   begin if ( cr_cf) pc <= pc + brdisp; state <= IFETCH; end
                        `BGT:   begin if ((cr_nf & cr_vf & !cr_zf)|(!cr_nf & !cr_vf & !cr_zf)) pc <= pc + brdisp; state <= IFETCH; end
                        `BLE:   begin if (cr_zf | (cr_nf & !cr_vf) | (!cr_nf & cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
                        `BGE:   begin if ((cr_nf & cr_vf)|(!cr_nf & !cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
                        `BLT:   begin if ((cr_nf & !cr_vf)|(!cr_nf & cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
                        `BVS:   begin if ( cr_vf) pc <= pc + brdisp; state <= IFETCH; end
                        `BVC:   begin if (!cr_vf) pc <= pc + brdisp; state <= IFETCH; end
                        endcase
                `TRAPcc:
                        case(cond)
                        `TRAP:  begin vector <= `TRAP_VECTOR + {ir[3:0],2'b00}; state <= TRAP; end
                        `TEQ:   begin if ( cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TNE:   begin if (!cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TMI:   begin if ( cr_nf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TPL:   begin if (!cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `THI:   begin if (!cr_cf & !cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TLS:   begin if (cf |zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `THS:   begin if (!cr_cf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TLO:   begin if ( cr_cf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TGT:   begin if ((cr_nf & cr_vf & !cr_zf)|(!cr_nf & !cr_vf & !cr_zf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TLE:   begin if (cr_zf | (cr_nf & !cr_vf) | (!cr_nf & cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TGE:   begin if ((cr_nf & cr_vf)|(!cr_nf & !cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TLT:   begin if ((cr_nf & !cr_vf)|(!cr_nf & cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TVS:   begin if ( cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TVC:   begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        endcase
                `SETcc: Rn <= ir[15:11];
                `PUSH:  state <= PUSH1;
                `POP:   state <= POP1;
                `UNLK:  state <= UNLK;
                endcase
                if (isIllegalOpcode) begin
                        vector <= `ILLEGAL_INSN;
                        state <= TRAP;
                end
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// REGFETCHA.v - fetch register A / execute some instructions`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`// ============================================================================`
23			`//`
24			`REGFETCHA:`
25			`begin`
26			`a <= rfo;`
27			`b <= 32'd0;`
28			`Rn <= ir[20:16];`
29			if (opcode==`RR \|\| opcode==`RRR) begin
30			`state <= REGFETCHB;`
31			`end`
32			`else begin`
33			`if ((hasConst16 && ir[15:0]==16'h8000) \|\| (isStop))`
34			`state <= FETCH_IMM32;`
35			`else begin`
36			`imm <= {{16{ir[15]}},ir[15:0]};`
37			`state <= EXECUTE;`
38			`end`
39			`end`
40			`case(opcode)`
41			`MISC:
42			`case(func)`
43			`TRACE_ON:
44			`if (!sf) begin`
45			vector <= `PRIVILEGE_VIOLATION;
46			`state <= TRAP;`
47			`end`
48			`else begin`
49			`tf <= 1'b1;`
50			`state <= IFETCH;`
51			`end`
52			`TRACE_OFF:
53			`if (!sf) begin`
54			vector <= `PRIVILEGE_VIOLATION;
55			`state <= TRAP;`
56			`end`
57			`else begin`
58			`tf <= 1'b0;`
59			`state <= IFETCH;`
60			`end`
61			`SET_IM:
62			`if (!sf) begin`
63			vector <= `PRIVILEGE_VIOLATION;
64			`state <= TRAP;`
65			`end`
66			`else begin`
67			`im <= ir[2:0];`
68			`state <= IFETCH;`
69			`end`
70			`USER_MODE: begin sf <= 1'b0; state <= IFETCH; end
71			`JMP32: state <= JMP32;
72			`JSR32: state <= JSR32;
73			`RTS: state <= RTS;
74			`RTI:
75			`if (!sf) begin`
76			vector <= `PRIVILEGE_VIOLATION;
77			`state <= TRAP;`
78			`end`
79			`else`
80			`state <= RTI1;`
81			`RST:
82			`if (!sf) begin`
83			vector <= `PRIVILEGE_VIOLATION;
84			`state <= TRAP;`
85			`end`
86			`else begin`
87			`rst_o <= 1'b1;`
88			`state <= IFETCH;`
89			`end`
90			`endcase`
91			`NOP: state <= IFETCH;
92			`JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
93			`JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
94			`Bcc:
95			`case(cond)`
96			`BRA: begin pc <= pc + brdisp; state <= IFETCH; end
97			`BEQ: begin if ( cr_zf) pc <= pc + brdisp; state <= IFETCH; end
98			`BNE: begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
99			`BMI: begin if ( cr_nf) pc <= pc + brdisp; state <= IFETCH; end
100			`BPL: begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
101			`BHI: begin if (!cr_cf & !cr_zf) pc <= pc + brdisp; state <= IFETCH; end
102			`BLS: begin if (cf \|zf) pc <= pc + brdisp; state <= IFETCH; end
103			`BHS: begin if (!cr_cf) pc <= pc + brdisp; state <= IFETCH; end
104			`BLO: begin if ( cr_cf) pc <= pc + brdisp; state <= IFETCH; end
105			`BGT: begin if ((cr_nf & cr_vf & !cr_zf)\|(!cr_nf & !cr_vf & !cr_zf)) pc <= pc + brdisp; state <= IFETCH; end
106			`BLE: begin if (cr_zf \| (cr_nf & !cr_vf) \| (!cr_nf & cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
107			`BGE: begin if ((cr_nf & cr_vf)\|(!cr_nf & !cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
108			`BLT: begin if ((cr_nf & !cr_vf)\|(!cr_nf & cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
109			`BVS: begin if ( cr_vf) pc <= pc + brdisp; state <= IFETCH; end
110			`BVC: begin if (!cr_vf) pc <= pc + brdisp; state <= IFETCH; end
111			`endcase`
112			`TRAPcc:
113			`case(cond)`
114			`TRAP: begin vector <= `TRAP_VECTOR + {ir[3:0],2'b00}; state <= TRAP; end
115			`TEQ: begin if ( cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
116			`TNE: begin if (!cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
117			`TMI: begin if ( cr_nf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
118			`TPL: begin if (!cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
119			`THI: begin if (!cr_cf & !cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
120			`TLS: begin if (cf \|zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
121			`THS: begin if (!cr_cf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
122			`TLO: begin if ( cr_cf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
123			`TGT: begin if ((cr_nf & cr_vf & !cr_zf)\|(!cr_nf & !cr_vf & !cr_zf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
124			`TLE: begin if (cr_zf \| (cr_nf & !cr_vf) \| (!cr_nf & cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
125			`TGE: begin if ((cr_nf & cr_vf)\|(!cr_nf & !cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
126			`TLT: begin if ((cr_nf & !cr_vf)\|(!cr_nf & cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
127			`TVS: begin if ( cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
128			`TVC: begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
129			`endcase`
130			`SETcc: Rn <= ir[15:11];
131			`PUSH: state <= PUSH1;
132			`POP: state <= POP1;
133			`UNLK: state <= UNLK;
134			`endcase`
135			`if (isIllegalOpcode) begin`
136			vector <= `ILLEGAL_INSN;
137			`state <= TRAP;`
138			`end`
139			`end`
140

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[/] [klc32/] [trunk/] [rtl/] [verilog/] [REGFETCHA.v] - Blame information for rev 4