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[/] [klc32/] [trunk/] [rtl/] [verilog/] [REGFETCHA.v] - Blame information for rev 6

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Line No. Rev Author Line
1 2 robfinch
// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// KLC32 - 32 bit CPU
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// REGFETCHA.v - fetch register A / execute some instructions
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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REGFETCHA:
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        begin
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                a <= rfo;
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                b <= 32'd0;
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                Rn <= ir[20:16];
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                if (opcode==`RR || opcode==`RRR) begin
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                        state <= REGFETCHB;
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                end
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                else begin
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                        if ((hasConst16 && ir[15:0]==16'h8000) || (isStop))
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                                state <= FETCH_IMM32;
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                        else begin
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                                imm <= {{16{ir[15]}},ir[15:0]};
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                                state <= EXECUTE;
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                        end
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                end
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                case(opcode)
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                `MISC:
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                        case(func)
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                        `TRACE_ON:
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                                        if (!sf) begin
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                                                vector <= `PRIVILEGE_VIOLATION;
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                                                state <= TRAP;
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                                        end
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                                        else begin
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                                                tf <= 1'b1;
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                                                state <= IFETCH;
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                                        end
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                        `TRACE_OFF:
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                                        if (!sf) begin
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                                                vector <= `PRIVILEGE_VIOLATION;
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                                                state <= TRAP;
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                                        end
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                                        else begin
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                                                tf <= 1'b0;
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                                                state <= IFETCH;
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                                        end
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                        `SET_IM:
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                                        if (!sf) begin
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                                                vector <= `PRIVILEGE_VIOLATION;
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                                                state <= TRAP;
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                                        end
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                                        else begin
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                                                im <= ir[2:0];
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                                                state <= IFETCH;
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                                        end
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                        `USER_MODE: begin sf <= 1'b0; state <= IFETCH; end
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                        `JMP32: state <= JMP32;
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                        `JSR32: state <= JSR32;
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                        `RTS: state <= RTS;
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                        `RTI:
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                                if (!sf) begin
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                                        vector <= `PRIVILEGE_VIOLATION;
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                                        state <= TRAP;
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                                end
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                                else
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                                        state <= RTI1;
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                        `RST:
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                                if (!sf) begin
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                                        vector <= `PRIVILEGE_VIOLATION;
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                                        state <= TRAP;
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                                end
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                                else begin
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                                        rst_o <= 1'b1;
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                                        state <= IFETCH;
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                                end
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                        endcase
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                `NOP: state <= IFETCH;
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                `JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
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                `JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
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                `Bcc:
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                        case(cond)
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                        `BRA:   begin pc <= pc + brdisp; state <= IFETCH; end
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                        `BEQ:   begin if ( cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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                        `BNE:   begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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                        `BMI:   begin if ( cr_nf) pc <= pc + brdisp; state <= IFETCH; end
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                        `BPL:   begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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                        `BHI:   begin if (!cr_cf & !cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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                        `BLS:   begin if (cf |zf) pc <= pc + brdisp; state <= IFETCH; end
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                        `BHS:   begin if (!cr_cf) pc <= pc + brdisp; state <= IFETCH; end
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                        `BLO:   begin if ( cr_cf) pc <= pc + brdisp; state <= IFETCH; end
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                        `BGT:   begin if ((cr_nf & cr_vf & !cr_zf)|(!cr_nf & !cr_vf & !cr_zf)) pc <= pc + brdisp; state <= IFETCH; end
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                        `BLE:   begin if (cr_zf | (cr_nf & !cr_vf) | (!cr_nf & cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
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                        `BGE:   begin if ((cr_nf & cr_vf)|(!cr_nf & !cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
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                        `BLT:   begin if ((cr_nf & !cr_vf)|(!cr_nf & cr_vf)) pc <= pc + brdisp; state <= IFETCH; end
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                        `BVS:   begin if ( cr_vf) pc <= pc + brdisp; state <= IFETCH; end
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                        `BVC:   begin if (!cr_vf) pc <= pc + brdisp; state <= IFETCH; end
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                        endcase
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                `TRAPcc:
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                        case(cond)
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                        `TRAP:  begin vector <= `TRAP_VECTOR + {ir[3:0],2'b00}; state <= TRAP; end
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                        `TEQ:   begin if ( cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TNE:   begin if (!cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TMI:   begin if ( cr_nf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TPL:   begin if (!cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `THI:   begin if (!cr_cf & !cr_zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TLS:   begin if (cf |zf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `THS:   begin if (!cr_cf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TLO:   begin if ( cr_cf) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TGT:   begin if ((cr_nf & cr_vf & !cr_zf)|(!cr_nf & !cr_vf & !cr_zf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TLE:   begin if (cr_zf | (cr_nf & !cr_vf) | (!cr_nf & cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TGE:   begin if ((cr_nf & cr_vf)|(!cr_nf & !cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TLT:   begin if ((cr_nf & !cr_vf)|(!cr_nf & cr_vf)) begin vector <= `TRAP_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TVS:   begin if ( cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        `TVC:   begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
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                        endcase
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                `SETcc: Rn <= ir[15:11];
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                `PUSH:  state <= PUSH1;
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                `POP:   state <= POP1;
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                `UNLK:  state <= UNLK;
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                endcase
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                if (isIllegalOpcode) begin
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                        vector <= `ILLEGAL_INSN;
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                        state <= TRAP;
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                end
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        end
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