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[/] [klc32/] [trunk/] [rtl/] [verilog/] [REGFETCHB.v] - Blame information for rev 10

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// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// KLC32 - 32 bit CPU
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// REGFETCHB.v - fetch the B side register
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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REGFETCHB:
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        begin
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                b <= rfo;
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                Rn <= ir[15:11];
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                if (opcode==`RRR || (opcode==`RR && (func==`SWX||func==`SHX||func==`SBX)))
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                        state <= REGFETCHC;
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                else begin
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                        // RIX format ?
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                        if (hasConst16 && ir[15:0]==16'h8000)
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                                state <= FETCH_IMM32;
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                        else begin
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                                case(opcode)
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                                `ANDI:  imm <= {16'hFFFF,ir[15:0]};
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                                `ORI:   imm <= {16'h0000,ir[15:0]};
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                                `EORI:  imm <= {16'h0000,ir[15:0]};
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                                default:        imm <= {{16{ir[15]}},ir[15:0]};
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                                endcase
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                                state <= EXECUTE;
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                        end
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                end
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        end

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