URL
https://opencores.org/ocsvn/klc32/klc32/trunk
[/] [klc32/] [trunk/] [rtl/] [verilog/] [RESET.v] - Blame information for rev 12
Go to most recent revision |
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
2 |
robfinch |
// ============================================================================
|
2 |
|
|
// (C) 2011 Robert Finch
|
3 |
|
|
// All Rights Reserved.
|
4 |
|
|
// robfinch<remove>@opencores.org
|
5 |
|
|
//
|
6 |
|
|
// KLC32 - 32 bit CPU
|
7 |
|
|
// RESET.v
|
8 |
|
|
//
|
9 |
|
|
// This source file is free software: you can redistribute it and/or modify
|
10 |
|
|
// it under the terms of the GNU Lesser General Public License as published
|
11 |
|
|
// by the Free Software Foundation, either version 3 of the License, or
|
12 |
|
|
// (at your option) any later version.
|
13 |
|
|
//
|
14 |
|
|
// This source file is distributed in the hope that it will be useful,
|
15 |
|
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
16 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
17 |
|
|
// GNU General Public License for more details.
|
18 |
|
|
//
|
19 |
|
|
// You should have received a copy of the GNU General Public License
|
20 |
|
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
21 |
|
|
//
|
22 |
|
|
// ============================================================================
|
23 |
|
|
//
|
24 |
|
|
RESET:
|
25 |
|
|
begin
|
26 |
|
|
im <= 3'b111;
|
27 |
|
|
sf <= 1'b1;
|
28 |
|
|
tf <= 1'b0;
|
29 |
|
|
vector <= `STACK_VECTOR;
|
30 |
|
|
state <= LOAD_SP;
|
31 |
|
|
end
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.