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[/] [klc32/] [trunk/] [rtl/] [verilog/] [RTS.v] - Blame information for rev 5

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Line No. Rev Author Line
1 2 robfinch
// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// KLC32 - 32 bit CPU
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// RTS.v - return from subroutine
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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RTS:
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        if (!cyc_o) begin
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                fc_o <= {sf,2'b01};
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                sel_o <= 4'b1111;
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                adr_o <= sf ? ssp : usp;
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        end
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        else if (ack_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'b0000;
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                if (sf)
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                        ssp <= ssp + 32'd4 + ir[21:6];
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                else
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                        usp <= usp + 32'd4 + ir[21:6];
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                pc <= {dat_i[31:2],2'b00}+{ir[25:22],2'b00};
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                state <= IFETCH;
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        end
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        else if (err_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'b0000;
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                vector <= `BUS_ERR_VECTOR;
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                state <= TRAP;
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        end
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