OpenCores
URL https://opencores.org/ocsvn/klc32/klc32/trunk

Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [TRAP.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 robfinch 
// ============================================================================
2 
// (C) 2011 Robert Finch
3 
// All Rights Reserved.
4 
// robfinch<remove>@opencores.org
5 
//
6 
// KLC32 - 32 bit CPU
7 
// TRAP.v
8 
//
9 
// This source file is free software: you can redistribute it and/or modify
10 
// it under the terms of the GNU Lesser General Public License as published
11 
// by the Free Software Foundation, either version 3 of the License, or
12 
// (at your option) any later version.
13 
//
14 
// This source file is distributed in the hope that it will be useful,
15 
// but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
// GNU General Public License for more details.
18 
//
19 
// You should have received a copy of the GNU General Public License
20 
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
21 
//
22 
// ============================================================================
23 
//
24 
TRAP1:
25 
        if (!cyc_o) begin
26 
                fc_o <= {3'b101};
27 
                cyc_o <= 1'b1;
28 
                stb_o <= 1'b1;
29 
                we_o <= 1'b1;
30 
                sel_o <= 4'b1111;
31 
                adr_o <= ssp - 32'd4;
32 
                dat_o <= pc;
33 
        end
34 
        else if (ack_i) begin
35 
                stb_o <= 1'b0;
36 
                we_o <= 1'b0;
37 
                sel_o <= 4'b0000;
38 
                sr1 <= sr;
39 
                sf <= 1'b1;
40 
                tf <= 1'b0;
41 
                ssp <= ssp - 32'd4;
42 
                state <= TRAP2;
43 
        end
44 
        else if (err_i) begin
45 
                cyc_o <= 1'b0;
46 
                stb_o <= 1'b0;
47 
                sel_o <= 4'b0000;
48 
                vector <= `BUS_ERR_VECTOR;
49 
                state <= TRAP;
50 
        end
51 
TRAP2:
52 
        if (!stb_o) begin
53 
                fc_o <= {3'b101};
54 
                stb_o <= 1'b1;
55 
                we_o <= 1'b1;
56 
                sel_o <= 4'b1111;
57 
                adr_o <= ssp - 32'd4;
58 
                dat_o <= cr;
59 
        end
60 
        else if (ack_i) begin
61 
                stb_o <= 1'b0;
62 
                we_o <= 1'b0;
63 
                sel_o <= 4'b0000;
64 
                ssp <= ssp - 32'd4;
65 
                state <= TRAP3;
66 
        end
67 
        else if (err_i) begin
68 
                cyc_o <= 1'b0;
69 
                stb_o <= 1'b0;
70 
                sel_o <= 4'b0000;
71 
                vector <= `BUS_ERR_VECTOR;
72 
                state <= TRAP;
73 
        end
74 
TRAP3:
75 
        if (!stb_o) begin
76 
                fc_o <= {3'b101};
77 
                stb_o <= 1'b1;
78 
                we_o <= 1'b1;
79 
                sel_o <= 4'b1111;
80 
                adr_o <= ssp - 32'd4;
81 
                dat_o <= sr1;
82 
        end
83 
        else if (ack_i) begin
84 
                cyc_o <= 1'b0;
85 
                stb_o <= 1'b0;
86 
                we_o <= 1'b0;
87 
                sel_o <= 4'b0000;
88 
                ssp <= ssp - 32'd4;
89 
                state <= VECTOR;
90 
        end
91 
        else if (err_i) begin
92 
                cyc_o <= 1'b0;
93 
                stb_o <= 1'b0;
94 
                sel_o <= 4'b0000;
95 
                vector <= `BUS_ERR_VECTOR;
96 
                state <= TRAP;
97 
        end
98 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.