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[/] [klc32/] [trunk/] [rtl/] [verilog/] [WRITEBACK.v] - Blame information for rev 12

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// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// WRITEBACK.v - update register file / generate flags
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
WRITEBACK:
        begin
                state <= WRITE_FLAGS;
                if (opcode!=`CMPI && !(opcode==`RR && func==`CMP)) begin
                        regfile[Rn] <= res;
                        if (Rn==5'd31) begin
                                if (sf) ssp <= res;
                                else usp <= res;
                        end
                end
                case(opcode)
                `R:
                        case(func)
                        `ABS:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                vf <= res[31];
                                cf <= 1'b0;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `SGN,`NOT,`EXTB,`EXTH:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                vf <= 1'b0;
                                cf <= 1'b0;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `NEG:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                vf <= v_rr;
                                cf <= c_rr;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        endcase
                `RR:
                        case(func)
                        `ADD,`SUB:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                vf <= v_rr;
                                cf <= c_rr;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `CMP:
                                begin
                                state <= WRITE_FLAGS;
                                vf <= 1'b0;
                                cf <= c_rr;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `AND,`OR,`EOR,`NAND,`NOR,`ENOR,`MIN,`MAX,
                        `LWX,`LHX,`LBX,`LHUX,`LBUX:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                vf <= 1'b0;
                                cf <= 1'b0;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `SHL,`ROL:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                vf <= 1'b0;
                                cf <= shlo[32];
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `SHR,`ROR:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                vf <= 1'b0;
                                cf <= shro[31];
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `BCDADD:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                vf <= 1'b0;
                                cf <= bcdaddc;
                                nf <= res[7];
                                zf <= res[7:0]==8'd0;
                                end
                        `BCDSUB:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                vf <= 1'b0;
                                cf <= bcdsubc;
                                nf <= res[7];
                                zf <= res[7:0]==8'd0;
                                end
                        `DIVU,`DIVS,`MODU,`MODS:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                vf <= divByZero;
                                cf <= divByZero;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `MULU,`MULS,`MULUH,`MULSH:
                                begin
                                if (!Rcbit) state <= IFETCH;
                                cf <= vf;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        endcase
                `ADDI,`SUBI:
                        begin
                        vf <= v_ri;
                        cf <= c_ri;
                        nf <= res[31];
                        zf <= res==32'd0;
                        end
                `CMPI:
                        begin
                        vf <= 1'b0;
                        cf <= c_ri;
                        nf <= res[31];
                        zf <= res==32'd0;
                        end
                `ANDI,`ORI,`EORI,`LW,`LH,`LB,`LHU,`LBU,`POP,`TAS:
                        begin
                        vf <= 1'b0;
                        cf <= 1'b0;
                        nf <= res[31];
                        zf <= res==32'd0;
                        end
                `DIVSI,`DIVUI:
                        begin
                        vf <= divByZero;
                        cf <= divByZero;
                        nf <= res[31];
                        zf <= res==32'd0;
                        end
                `MULSI,`MULUI:
                        begin
                        cf <= vf;
                        nf <= res[31];
                        zf <= res==32'd0;
                        end
                `POP:   state <= POP1;
                `LINK:
                        begin
                                state <= IFETCH;
                                if (sf)
                                        ssp <= ssp - imm;
                                else
                                        usp <= usp - imm;
                        end
                endcase
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// WRITEBACK.v - update register file / generate flags`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`// ============================================================================`
23			`//`
24			`WRITEBACK:`
25			`begin`
26	10	robfinch	`state <= WRITE_FLAGS;`
27	2	robfinch	if (opcode!=`CMPI && !(opcode==`RR && func==`CMP)) begin
28			`regfile[Rn] <= res;`
29			`if (Rn==5'd31) begin`
30			`if (sf) ssp <= res;`
31			`else usp <= res;`
32			`end`
33			`end`
34			`case(opcode)`
35			`R:
36			`case(func)`
37			`ABS:
38			`begin`
39	10	robfinch	`if (!Rcbit) state <= IFETCH;`
40	2	robfinch	`vf <= res[31];`
41			`cf <= 1'b0;`
42			`nf <= res[31];`
43			`zf <= res==32'd0;`
44			`end`
45			`SGN,`NOT,`EXTB,`EXTH:
46			`begin`
47	10	robfinch	`if (!Rcbit) state <= IFETCH;`
48	2	robfinch	`vf <= 1'b0;`
49			`cf <= 1'b0;`
50			`nf <= res[31];`
51			`zf <= res==32'd0;`
52			`end`
53			`NEG:
54			`begin`
55	10	robfinch	`if (!Rcbit) state <= IFETCH;`
56	2	robfinch	`vf <= v_rr;`
57			`cf <= c_rr;`
58			`nf <= res[31];`
59			`zf <= res==32'd0;`
60			`end`
61			`endcase`
62			`RR:
63			`case(func)`
64			`ADD,`SUB:
65			`begin`
66	10	robfinch	`if (!Rcbit) state <= IFETCH;`
67	2	robfinch	`vf <= v_rr;`
68			`cf <= c_rr;`
69			`nf <= res[31];`
70			`zf <= res==32'd0;`
71			`end`
72			`CMP:
73			`begin`
74	10	robfinch	`state <= WRITE_FLAGS;`
75	2	robfinch	`vf <= 1'b0;`
76			`cf <= c_rr;`
77			`nf <= res[31];`
78			`zf <= res==32'd0;`
79			`end`
80			`AND,`OR,`EOR,`NAND,`NOR,`ENOR,`MIN,`MAX,
81			`LWX,`LHX,`LBX,`LHUX,`LBUX:
82			`begin`
83	10	robfinch	`if (!Rcbit) state <= IFETCH;`
84	2	robfinch	`vf <= 1'b0;`
85			`cf <= 1'b0;`
86			`nf <= res[31];`
87			`zf <= res==32'd0;`
88			`end`
89			`SHL,`ROL:
90			`begin`
91	10	robfinch	`if (!Rcbit) state <= IFETCH;`
92	2	robfinch	`vf <= 1'b0;`
93			`cf <= shlo[32];`
94			`nf <= res[31];`
95			`zf <= res==32'd0;`
96			`end`
97			`SHR,`ROR:
98			`begin`
99	10	robfinch	`if (!Rcbit) state <= IFETCH;`
100	2	robfinch	`vf <= 1'b0;`
101			`cf <= shro[31];`
102			`nf <= res[31];`
103			`zf <= res==32'd0;`
104			`end`
105			`BCDADD:
106			`begin`
107	10	robfinch	`if (!Rcbit) state <= IFETCH;`
108	2	robfinch	`vf <= 1'b0;`
109			`cf <= bcdaddc;`
110			`nf <= res[7];`
111			`zf <= res[7:0]==8'd0;`
112			`end`
113			`BCDSUB:
114			`begin`
115	10	robfinch	`if (!Rcbit) state <= IFETCH;`
116	2	robfinch	`vf <= 1'b0;`
117			`cf <= bcdsubc;`
118			`nf <= res[7];`
119			`zf <= res[7:0]==8'd0;`
120			`end`
121	10	robfinch	`DIVU,`DIVS,`MODU,`MODS:
122			`begin`
123			`if (!Rcbit) state <= IFETCH;`
124			`vf <= divByZero;`
125			`cf <= divByZero;`
126			`nf <= res[31];`
127			`zf <= res==32'd0;`
128			`end`
129			`MULU,`MULS,`MULUH,`MULSH:
130			`begin`
131			`if (!Rcbit) state <= IFETCH;`
132			`cf <= vf;`
133			`nf <= res[31];`
134			`zf <= res==32'd0;`
135			`end`
136	2	robfinch	`endcase`
137			`ADDI,`SUBI:
138			`begin`
139			`vf <= v_ri;`
140			`cf <= c_ri;`
141			`nf <= res[31];`
142			`zf <= res==32'd0;`
143			`end`
144			`CMPI:
145			`begin`
146			`vf <= 1'b0;`
147			`cf <= c_ri;`
148			`nf <= res[31];`
149			`zf <= res==32'd0;`
150			`end`
151			`ANDI,`ORI,`EORI,`LW,`LH,`LB,`LHU,`LBU,`POP,`TAS:
152			`begin`
153			`vf <= 1'b0;`
154			`cf <= 1'b0;`
155			`nf <= res[31];`
156			`zf <= res==32'd0;`
157			`end`
158	10	robfinch	`DIVSI,`DIVUI:
159			`begin`
160			`vf <= divByZero;`
161			`cf <= divByZero;`
162			`nf <= res[31];`
163			`zf <= res==32'd0;`
164			`end`
165			`MULSI,`MULUI:
166			`begin`
167			`cf <= vf;`
168			`nf <= res[31];`
169			`zf <= res==32'd0;`
170			`end`
171			`POP: state <= POP1;
172	2	robfinch	`LINK:
173			`begin`
174			`state <= IFETCH;`
175			`if (sf)`
176	10	robfinch	`ssp <= ssp - imm;`
177	2	robfinch	`else`
178	10	robfinch	`usp <= usp - imm;`
179	2	robfinch	`end`
180			`endcase`
181			`end`
182

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[/] [klc32/] [trunk/] [rtl/] [verilog/] [WRITEBACK.v] - Blame information for rev 12