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[/] [klc32/] [trunk/] [rtl/] [verilog/] [WRITEBACK.v] - Blame information for rev 12

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// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// KLC32 - 32 bit CPU
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// WRITEBACK.v - update register file / generate flags
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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WRITEBACK:
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        begin
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                state <= WRITE_FLAGS;
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                if (opcode!=`CMPI && !(opcode==`RR && func==`CMP)) begin
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                        regfile[Rn] <= res;
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                        if (Rn==5'd31) begin
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                                if (sf) ssp <= res;
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                                else usp <= res;
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                        end
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                end
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                case(opcode)
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                `R:
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                        case(func)
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                        `ABS:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                vf <= res[31];
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                                cf <= 1'b0;
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                                nf <= res[31];
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                                zf <= res==32'd0;
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                                end
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                        `SGN,`NOT,`EXTB,`EXTH:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                vf <= 1'b0;
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                                cf <= 1'b0;
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                                nf <= res[31];
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                                zf <= res==32'd0;
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                                end
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                        `NEG:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                vf <= v_rr;
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                                cf <= c_rr;
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                                nf <= res[31];
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                                zf <= res==32'd0;
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                                end
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                        endcase
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                `RR:
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                        case(func)
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                        `ADD,`SUB:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                vf <= v_rr;
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                                cf <= c_rr;
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                                nf <= res[31];
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                                zf <= res==32'd0;
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                                end
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                        `CMP:
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                                begin
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                                state <= WRITE_FLAGS;
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                                vf <= 1'b0;
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                                cf <= c_rr;
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                                nf <= res[31];
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                                zf <= res==32'd0;
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                                end
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                        `AND,`OR,`EOR,`NAND,`NOR,`ENOR,`MIN,`MAX,
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                        `LWX,`LHX,`LBX,`LHUX,`LBUX:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                vf <= 1'b0;
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                                cf <= 1'b0;
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                                nf <= res[31];
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                                zf <= res==32'd0;
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                                end
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                        `SHL,`ROL:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                vf <= 1'b0;
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                                cf <= shlo[32];
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                                nf <= res[31];
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                                zf <= res==32'd0;
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                                end
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                        `SHR,`ROR:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                vf <= 1'b0;
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                                cf <= shro[31];
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                                nf <= res[31];
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                                zf <= res==32'd0;
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                                end
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                        `BCDADD:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                vf <= 1'b0;
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                                cf <= bcdaddc;
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                                nf <= res[7];
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                                zf <= res[7:0]==8'd0;
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                                end
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                        `BCDSUB:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                vf <= 1'b0;
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                                cf <= bcdsubc;
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                                nf <= res[7];
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                                zf <= res[7:0]==8'd0;
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                                end
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                        `DIVU,`DIVS,`MODU,`MODS:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                vf <= divByZero;
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                                cf <= divByZero;
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                                nf <= res[31];
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                                zf <= res==32'd0;
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                                end
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                        `MULU,`MULS,`MULUH,`MULSH:
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                                begin
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                                if (!Rcbit) state <= IFETCH;
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                                cf <= vf;
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                                nf <= res[31];
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                                zf <= res==32'd0;
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                                end
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                        endcase
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                `ADDI,`SUBI:
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                        begin
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                        vf <= v_ri;
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                        cf <= c_ri;
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                        nf <= res[31];
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                        zf <= res==32'd0;
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                        end
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                `CMPI:
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                        begin
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                        vf <= 1'b0;
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                        cf <= c_ri;
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                        nf <= res[31];
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                        zf <= res==32'd0;
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                        end
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                `ANDI,`ORI,`EORI,`LW,`LH,`LB,`LHU,`LBU,`POP,`TAS:
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                        begin
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                        vf <= 1'b0;
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                        cf <= 1'b0;
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                        nf <= res[31];
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                        zf <= res==32'd0;
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                        end
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                `DIVSI,`DIVUI:
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                        begin
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                        vf <= divByZero;
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                        cf <= divByZero;
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                        nf <= res[31];
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                        zf <= res==32'd0;
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                        end
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                `MULSI,`MULUI:
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                        begin
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                        cf <= vf;
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                        nf <= res[31];
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                        zf <= res==32'd0;
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                        end
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                `POP:   state <= POP1;
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                `LINK:
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                        begin
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                                state <= IFETCH;
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                                if (sf)
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                                        ssp <= ssp - imm;
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                                else
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                                        usp <= usp - imm;
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                        end
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                endcase
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        end
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