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[/] [klc32/] [trunk/] [rtl/] [verilog/] [WRITEBACK.v] - Blame information for rev 5

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// ============================================================================
// (C) 2011 Robert Finch
// All Rights Reserved.
// robfinch<remove>@opencores.org
//
// KLC32 - 32 bit CPU
// WRITEBACK.v - update register file / generate flags
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
WRITEBACK:
        begin
                if (opcode==`POP)
                        state <= POP1;
                else
                        state <= WRITE_FLAGS;
                if (opcode!=`CMPI && !(opcode==`RR && func==`CMP)) begin
                        regfile[Rn] <= res;
                        if (Rn==5'd31) begin
                                if (sf) ssp <= res;
                                else usp <= res;
                        end
                end
                case(opcode)
                `R:
                        case(func)
                        `ABS:
                                begin
                                vf <= res[31];
                                cf <= 1'b0;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `SGN,`NOT,`EXTB,`EXTH:
                                begin
                                vf <= 1'b0;
                                cf <= 1'b0;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `NEG:
                                begin
                                vf <= v_rr;
                                cf <= c_rr;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        endcase
                `RR:
                        case(func)
                        `ADD,`SUB:
                                begin
                                vf <= v_rr;
                                cf <= c_rr;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `CMP:
                                begin
                                vf <= 1'b0;
                                cf <= c_rr;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `AND,`OR,`EOR,`NAND,`NOR,`ENOR,`MIN,`MAX,
                        `LWX,`LHX,`LBX,`LHUX,`LBUX:
                                begin
                                vf <= 1'b0;
                                cf <= 1'b0;
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `SHL,`ROL:
                                begin
                                vf <= 1'b0;
                                cf <= shlo[32];
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `SHR,`ROR:
                                begin
                                vf <= 1'b0;
                                cf <= shro[31];
                                nf <= res[31];
                                zf <= res==32'd0;
                                end
                        `BCDADD:
                                begin
                                vf <= 1'b0;
                                cf <= bcdaddc;
                                nf <= res[7];
                                zf <= res[7:0]==8'd0;
                                end
                        `BCDSUB:
                                begin
                                vf <= 1'b0;
                                cf <= bcdsubc;
                                nf <= res[7];
                                zf <= res[7:0]==8'd0;
                                end
                        endcase
                `ADDI,`SUBI:
                        begin
                        vf <= v_ri;
                        cf <= c_ri;
                        nf <= res[31];
                        zf <= res==32'd0;
                        end
                `CMPI:
                        begin
                        vf <= 1'b0;
                        cf <= c_ri;
                        nf <= res[31];
                        zf <= res==32'd0;
                        end
                `ANDI,`ORI,`EORI,`LW,`LH,`LB,`LHU,`LBU,`POP,`TAS:
                        begin
                        vf <= 1'b0;
                        cf <= 1'b0;
                        nf <= res[31];
                        zf <= res==32'd0;
                        end
                `LINK:
                        begin
                                state <= IFETCH;
                                if (sf)
                                        ssp <= ssp + imm;
                                else
                                        usp <= usp + imm;
                        end
                endcase
        end
 

Line No.	Rev	Author	Line
1	2	robfinch	`// ============================================================================`
2			`// (C) 2011 Robert Finch`
3			`// All Rights Reserved.`
4			`// robfinch<remove>@opencores.org`
5			`//`
6			`// KLC32 - 32 bit CPU`
7			`// WRITEBACK.v - update register file / generate flags`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`// ============================================================================`
23			`//`
24			`WRITEBACK:`
25			`begin`
26			if (opcode==`POP)
27			`state <= POP1;`
28			`else`
29			`state <= WRITE_FLAGS;`
30			if (opcode!=`CMPI && !(opcode==`RR && func==`CMP)) begin
31			`regfile[Rn] <= res;`
32			`if (Rn==5'd31) begin`
33			`if (sf) ssp <= res;`
34			`else usp <= res;`
35			`end`
36			`end`
37			`case(opcode)`
38			`R:
39			`case(func)`
40			`ABS:
41			`begin`
42			`vf <= res[31];`
43			`cf <= 1'b0;`
44			`nf <= res[31];`
45			`zf <= res==32'd0;`
46			`end`
47			`SGN,`NOT,`EXTB,`EXTH:
48			`begin`
49			`vf <= 1'b0;`
50			`cf <= 1'b0;`
51			`nf <= res[31];`
52			`zf <= res==32'd0;`
53			`end`
54			`NEG:
55			`begin`
56			`vf <= v_rr;`
57			`cf <= c_rr;`
58			`nf <= res[31];`
59			`zf <= res==32'd0;`
60			`end`
61			`endcase`
62			`RR:
63			`case(func)`
64			`ADD,`SUB:
65			`begin`
66			`vf <= v_rr;`
67			`cf <= c_rr;`
68			`nf <= res[31];`
69			`zf <= res==32'd0;`
70			`end`
71			`CMP:
72			`begin`
73			`vf <= 1'b0;`
74			`cf <= c_rr;`
75			`nf <= res[31];`
76			`zf <= res==32'd0;`
77			`end`
78			`AND,`OR,`EOR,`NAND,`NOR,`ENOR,`MIN,`MAX,
79			`LWX,`LHX,`LBX,`LHUX,`LBUX:
80			`begin`
81			`vf <= 1'b0;`
82			`cf <= 1'b0;`
83			`nf <= res[31];`
84			`zf <= res==32'd0;`
85			`end`
86			`SHL,`ROL:
87			`begin`
88			`vf <= 1'b0;`
89			`cf <= shlo[32];`
90			`nf <= res[31];`
91			`zf <= res==32'd0;`
92			`end`
93			`SHR,`ROR:
94			`begin`
95			`vf <= 1'b0;`
96			`cf <= shro[31];`
97			`nf <= res[31];`
98			`zf <= res==32'd0;`
99			`end`
100			`BCDADD:
101			`begin`
102			`vf <= 1'b0;`
103			`cf <= bcdaddc;`
104			`nf <= res[7];`
105			`zf <= res[7:0]==8'd0;`
106			`end`
107			`BCDSUB:
108			`begin`
109			`vf <= 1'b0;`
110			`cf <= bcdsubc;`
111			`nf <= res[7];`
112			`zf <= res[7:0]==8'd0;`
113			`end`
114			`endcase`
115			`ADDI,`SUBI:
116			`begin`
117			`vf <= v_ri;`
118			`cf <= c_ri;`
119			`nf <= res[31];`
120			`zf <= res==32'd0;`
121			`end`
122			`CMPI:
123			`begin`
124			`vf <= 1'b0;`
125			`cf <= c_ri;`
126			`nf <= res[31];`
127			`zf <= res==32'd0;`
128			`end`
129			`ANDI,`ORI,`EORI,`LW,`LH,`LB,`LHU,`LBU,`POP,`TAS:
130			`begin`
131			`vf <= 1'b0;`
132			`cf <= 1'b0;`
133			`nf <= res[31];`
134			`zf <= res==32'd0;`
135			`end`
136			`LINK:
137			`begin`
138			`state <= IFETCH;`
139			`if (sf)`
140			`ssp <= ssp + imm;`
141			`else`
142			`usp <= usp + imm;`
143			`end`
144			`endcase`
145			`end`
146

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[/] [klc32/] [trunk/] [rtl/] [verilog/] [WRITEBACK.v] - Blame information for rev 5