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[/] [klc32/] [trunk/] [rtl/] [verilog/] [WRITE_FLAGS.v] - Blame information for rev 4

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1 2 robfinch 
// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// KLC32 - 32 bit CPU
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// WRITE_FLAGS.v - update the CR registers
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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WRITE_FLAGS:
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        begin
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                state <= IFETCH;
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                if (opcode==`CMPI || (opcode==`RR && func==`CMP)) begin
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                        case(Rn[2:0])
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                        3'd0:   cr0 <= {nf,zf,vf,cf};
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                        3'd1:   cr1 <= {nf,zf,vf,cf};
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                        3'd2:   cr2 <= {nf,zf,vf,cf};
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                        3'd3:   cr3 <= {nf,zf,vf,cf};
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                        3'd4:   cr4 <= {nf,zf,vf,cf};
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                        3'd5:   cr5 <= {nf,zf,vf,cf};
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                        3'd6:   cr6 <= {nf,zf,vf,cf};
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                        3'd7:   cr7 <= {nf,zf,vf,cf};
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                        endcase
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                end
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                else begin
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                        case(opcode)
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                        `R:
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                                case(func)
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                                `ABS,`SGN,`NEG,`NOT,`EXTB,`EXTH:
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                                        cr0 <= {nf,zf,vf,cf};
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                                default:        ;
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                                endcase
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                        `RR:
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                                case(func)
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                                `ADD,`SUB,`AND,`OR,`EOR,`NAND,`NOR,`ENOR,
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                                `MIN,`MAX,
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                                `BCDADD,`BCDSUB,
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                                `SHL,`SHR,`ROL,`ROR,
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                                `LWX,`LHX,`LBX,`LHUX,`LBUX:
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                                        cr0 <= {nf,zf,vf,cf};
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                                default:        ;
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                                endcase
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                        `ADDI,`SUBI,`ANDI,`ORI,`EORI,`LW,`LH,`LB,`LHU,`LBU,`TAS:
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                                cr0 <= {nf,zf,vf,cf};
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                        default:        ;
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                        endcase
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                end
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        end
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