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[/] [klc32/] [trunk/] [rtl/] [verilog/] [carry.v] - Blame information for rev 6

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1 5 robfinch
/* ============================================================================
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        (C) 2005-2007  Robert T Finch
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        All rights reserved.
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        rob@birdcomputer.ca
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        carry.v
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        Verilog 1995
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        You may use this source code for non-commercial or evaluation purposes,
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        provided this copyright statement and disclaimer remains present in the
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        file.
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        NO WARRANTY.
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        THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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        EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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        Work.
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        IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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        INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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        THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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        IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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        IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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        REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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        LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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        AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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        LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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        This module computes carry for add/subtract given two operands and the
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        result. Assuming we don't know what the carry input is and there may
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        have been one.
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============================================================================ */
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module carry(op, a, b, s, c);
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        input op;       // 0=add,1=sub
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        input a;
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        input b;
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        input s;        // sum
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        output c;
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        assign c = op? (~a&b)|(s&~a)|(s&b) : (a&b)|(a&~s)|(b&~s);
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endmodule
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