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kavi |
-- File automatically generated by "cdfg2hdl".
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-- Filename: cordic_tb.vhd
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-- Date: 08 November 2010 11:05:42 AM
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-- Author: Nikolaos Kavvadias (C) 2009, 2010
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library IEEE, STD;
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use STD.textio.all;
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use WORK.std_logic_textio.all;
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use IEEE.numeric_std.all;
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use WORK.cordic_cdt_pkg.all;
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use IEEE.std_logic_1164.all;
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entity cordic_tb is
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end cordic_tb;
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architecture tb_arch of cordic_tb is
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component cordic
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port (
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clk : in std_logic;
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reset : in std_logic;
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start : in std_logic;
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direction : in std_logic_vector(15 downto 0);
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mode : in std_logic_vector(15 downto 0);
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xin : in std_logic_vector(15 downto 0);
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yin : in std_logic_vector(15 downto 0);
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zin : in std_logic_vector(15 downto 0);
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xout : out std_logic_vector(15 downto 0);
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yout : out std_logic_vector(15 downto 0);
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zout : out std_logic_vector(15 downto 0);
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done : out std_logic;
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ready : out std_logic
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);
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end component;
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signal clk : std_logic;
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signal reset : std_logic;
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signal start : std_logic;
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signal direction : std_logic_vector(15 downto 0);
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signal mode : std_logic_vector(15 downto 0);
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signal xin : std_logic_vector(15 downto 0);
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signal yin : std_logic_vector(15 downto 0);
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signal zin : std_logic_vector(15 downto 0);
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signal xout : std_logic_vector(15 downto 0);
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signal yout : std_logic_vector(15 downto 0);
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signal zout : std_logic_vector(15 downto 0);
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signal done : std_logic;
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signal ready : std_logic;
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-- Profiling signals
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signal ncycles : integer;
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-- Constant declarations
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constant CLK_PERIOD : time := 10 ns;
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-- Declare test data file and results file
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file TestDataFile: text open read_mode is "cordic_test_data.txt";
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file ResultsFile: text open write_mode is "cordic_alg_test_results.txt";
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begin
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uut : cordic
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port map (
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clk => clk,
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reset => reset,
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start => start,
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direction => direction,
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mode => mode,
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xin => xin,
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yin => yin,
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zin => zin,
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xout => xout,
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yout => yout,
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zout => zout,
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ready => ready,
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done => done
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);
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CLK_GEN_PROC: process(clk)
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begin
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if (clk = 'U') then
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clk <= '1';
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else
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clk <= not clk after CLK_PERIOD/2;
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end if;
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end process CLK_GEN_PROC;
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RESET_START_STIM: process
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begin
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reset <= '1';
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start <= '0';
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wait for CLK_PERIOD;
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reset <= '0';
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start <= '1';
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wait for 536870911*CLK_PERIOD;
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end process RESET_START_STIM;
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PROFILING: process(clk, reset, done)
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begin
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if (reset = '1' or done = '1') then
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ncycles <= 0;
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elsif (clk = '1' and clk'EVENT) then
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ncycles <= ncycles + 1;
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end if;
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end process PROFILING;
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CORDIC_BENCH: process
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variable direction_v : signed(15 downto 0);
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variable direction_v_vec : std_logic_vector(15 downto 0);
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variable mode_v : signed(15 downto 0);
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variable mode_v_vec : std_logic_vector(15 downto 0);
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variable xin_v : signed(15 downto 0);
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variable xin_v_vec : std_logic_vector(15 downto 0);
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variable yin_v : signed(15 downto 0);
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variable yin_v_vec : std_logic_vector(15 downto 0);
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variable zin_v : signed(15 downto 0);
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variable zin_v_vec : std_logic_vector(15 downto 0);
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variable xout_v, xout_ref : signed(15 downto 0);
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variable xout_v_vec, xout_ref_vec : std_logic_vector(15 downto 0);
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variable yout_v, yout_ref : signed(15 downto 0);
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variable yout_v_vec, yout_ref_vec : std_logic_vector(15 downto 0);
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variable zout_v, zout_ref : signed(15 downto 0);
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variable zout_v_vec, zout_ref_vec : std_logic_vector(15 downto 0);
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variable ncycles_v: integer;
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variable TestData, BufLine: line;
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variable Passed: std_logic := '1';
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begin
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while not endfile(TestDataFile) loop
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-- Read test data from file
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readline(TestDataFile, TestData);
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hread(TestData, direction_v_vec);
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direction <= direction_v_vec;
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hread(TestData, mode_v_vec);
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mode <= mode_v_vec;
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hread(TestData, xin_v_vec);
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xin <= xin_v_vec;
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hread(TestData, yin_v_vec);
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yin <= yin_v_vec;
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hread(TestData, zin_v_vec);
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zin <= zin_v_vec;
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hread(TestData, xout_ref_vec);
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xout_ref := SIGNED(xout_ref_vec);
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hread(TestData, yout_ref_vec);
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yout_ref := SIGNED(yout_ref_vec);
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hread(TestData, zout_ref_vec);
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zout_ref := SIGNED(zout_ref_vec);
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wait until done = '1';
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xout_v := signed(xout);
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yout_v := signed(yout);
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zout_v := signed(zout);
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-- Test CORDIC algorithm
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if (
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(xout_v /= xout_ref) or
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(yout_v /= yout_ref) or
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(zout_v /= zout_ref)
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) then
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Passed := '0';
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write(Bufline, string'("CORDIC error: direction="));
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hwrite(Bufline, STD_LOGIC_VECTOR(direction));
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write(Bufline, string'("CORDIC error: mode="));
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hwrite(Bufline, STD_LOGIC_VECTOR(mode));
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write(Bufline, string'("CORDIC error: xin="));
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hwrite(Bufline, STD_LOGIC_VECTOR(xin));
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write(Bufline, string'("CORDIC error: yin="));
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hwrite(Bufline, STD_LOGIC_VECTOR(yin));
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write(Bufline, string'("CORDIC error: zin="));
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hwrite(Bufline, STD_LOGIC_VECTOR(zin));
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write(Bufline, string'(" xout="));
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hwrite(Bufline, STD_LOGIC_VECTOR(xout_v));
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write(Bufline, string'(" xout_ref="));
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hwrite(Bufline, STD_LOGIC_VECTOR(xout_ref));
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write(Bufline, string'(" yout="));
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hwrite(Bufline, STD_LOGIC_VECTOR(yout_v));
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write(Bufline, string'(" yout_ref="));
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hwrite(Bufline, STD_LOGIC_VECTOR(yout_ref));
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write(Bufline, string'(" zout="));
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hwrite(Bufline, STD_LOGIC_VECTOR(zout_v));
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write(Bufline, string'(" zout_ref="));
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hwrite(Bufline, STD_LOGIC_VECTOR(zout_ref));
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writeline(ResultsFile, Bufline);
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else
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write(Bufline, string'(" direction="));
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hwrite(Bufline, STD_LOGIC_VECTOR(direction));
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write(Bufline, string'(" mode="));
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hwrite(Bufline, STD_LOGIC_VECTOR(mode));
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write(Bufline, string'(" xin="));
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hwrite(Bufline, STD_LOGIC_VECTOR(xin));
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write(Bufline, string'(" yin="));
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hwrite(Bufline, STD_LOGIC_VECTOR(yin));
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write(Bufline, string'(" zin="));
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hwrite(Bufline, STD_LOGIC_VECTOR(zin));
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write(Bufline, string'(" xout="));
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hwrite(Bufline, STD_LOGIC_VECTOR(xout));
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write(Bufline, string'(" xout_ref="));
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hwrite(Bufline, STD_LOGIC_VECTOR(xout_ref));
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write(Bufline, string'(" yout="));
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hwrite(Bufline, STD_LOGIC_VECTOR(yout));
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write(Bufline, string'(" yout_ref="));
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hwrite(Bufline, STD_LOGIC_VECTOR(yout_ref));
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write(Bufline, string'(" zout="));
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hwrite(Bufline, STD_LOGIC_VECTOR(zout));
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write(Bufline, string'(" zout_ref="));
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hwrite(Bufline, STD_LOGIC_VECTOR(zout_ref));
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writeline(ResultsFile, Bufline);
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ncycles_v := ncycles;
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write(Bufline, string'("CORDIC OK: Number of cycles="));
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write(Bufline, ncycles_v);
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writeline(ResultsFile, Bufline);
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end if;
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end loop;
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if (Passed = '1') then
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write(Bufline, string'("CORDIC algorithm test has passed"));
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writeline(ResultsFile, Bufline);
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-- Automatic end of the current simulation.
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assert false
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report "End simulation time reached"
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severity failure;
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end if;
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wait for CLK_PERIOD;
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end process CORDIC_BENCH;
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end tb_arch;
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