1 |
2 |
kavi |
====================
|
2 |
|
|
cordic user manual
|
3 |
|
|
====================
|
4 |
|
|
|
5 |
|
|
+-------------------+----------------------------------------------------------+
|
6 |
|
|
| **Title** | cordic (Multi-function, universal, fixed-point CORDIC) |
|
7 |
|
|
+-------------------+----------------------------------------------------------+
|
8 |
|
|
| **Author** | Nikolaos Kavvadias (C) 2010, 2011, 2012, 2013, 2014 |
|
9 |
|
|
+-------------------+----------------------------------------------------------+
|
10 |
|
|
| **Contact** | nikos@nkavvadias.com |
|
11 |
|
|
+-------------------+----------------------------------------------------------+
|
12 |
|
|
| **Website** | http://www.nkavvadias.com |
|
13 |
|
|
+-------------------+----------------------------------------------------------+
|
14 |
|
|
| **Release Date** | 22 February 2014 |
|
15 |
|
|
+-------------------+----------------------------------------------------------+
|
16 |
|
|
| **Version** | 1.0.0 |
|
17 |
|
|
+-------------------+----------------------------------------------------------+
|
18 |
|
|
| **Rev. history** | |
|
19 |
|
|
+-------------------+----------------------------------------------------------+
|
20 |
|
|
| **v1.0.0** | 2013-02-22 |
|
21 |
|
|
| | |
|
22 |
|
|
| | Updated architecture. A single cycle is now needed per |
|
23 |
|
|
| | iteration. Documentation updated to RestructuredText. |
|
24 |
|
|
| | Logic synthesis scripts updated for Xilinx ISE/XST 14.6. |
|
25 |
|
|
+-------------------+----------------------------------------------------------+
|
26 |
|
|
| **v0.0.2** | 2010-11-08 |
|
27 |
|
|
| | |
|
28 |
|
|
| | A universal CORDIC algorithm is now specified. The new |
|
29 |
|
|
| | version uses the full CORDIC interface (X,Y,Z) for input |
|
30 |
|
|
| | and output. Q2.14 (16-bit) signed fixed-point arithmetic |
|
31 |
|
|
| | is emulated through the use of integers. |
|
32 |
|
|
+-------------------+----------------------------------------------------------+
|
33 |
|
|
| **v0.0.1** | 2010-11-04 |
|
34 |
|
|
| | |
|
35 |
|
|
| | The CORDIC-EULA.txt has been added. |
|
36 |
|
|
+-------------------+----------------------------------------------------------+
|
37 |
|
|
| **v0.0.0** | 2010-11-01 |
|
38 |
|
|
| | |
|
39 |
|
|
| | Initial release. |
|
40 |
|
|
+-------------------+----------------------------------------------------------+
|
41 |
|
|
|
42 |
|
|
|
43 |
|
|
1. Introduction
|
44 |
|
|
===============
|
45 |
|
|
|
46 |
|
|
``cordic`` is a collection of files comprising an implementation of a universal
|
47 |
|
|
CORDIC algorithm (rotation/vectoring direction, circular/linear/hyperbolic mode)
|
48 |
|
|
high-level synthesis benchmark by Nikolaos Kavvadias. All design files except
|
49 |
|
|
``cordic.c``, ``cordic.nac``, and ``cordic_test_data.txt``
|
50 |
|
|
have been automatically generated. The original ``cordic.vhd`` has been
|
51 |
|
|
optimized via (manual) operation chaining. ``operpack.vhd``,
|
52 |
|
|
``std_logic_textio.vhd`` are simulation/synthesis library files, copyrighted by
|
53 |
|
|
their respective authors.
|
54 |
|
|
|
55 |
|
|
IMPORTANT: Please go through the license agreement (``CORDIC-EULA.txt``) to
|
56 |
|
|
ensure proper use of the CORDIC IP CORE.
|
57 |
|
|
|
58 |
|
|
|
59 |
|
|
2. File listing
|
60 |
|
|
===============
|
61 |
|
|
|
62 |
|
|
The CORDIC IP core distribution includes the following files:
|
63 |
|
|
|
64 |
|
|
+-----------------------+------------------------------------------------------+
|
65 |
|
|
| /cordic | Top-level directory |
|
66 |
|
|
+-----------------------+------------------------------------------------------+
|
67 |
|
|
| /bench/vhdl | Benchmarks VHDL directory |
|
68 |
|
|
+-----------------------+------------------------------------------------------+
|
69 |
|
|
| cordic_tb.vhd | Automatically-generated VHDL testbench file. |
|
70 |
|
|
+-----------------------+------------------------------------------------------+
|
71 |
|
|
| /doc | Documentation directory |
|
72 |
|
|
+-----------------------+------------------------------------------------------+
|
73 |
|
|
| AUTHORS | List of authors. |
|
74 |
|
|
+-----------------------+------------------------------------------------------+
|
75 |
|
|
| CORDIC-EULA.txt | End-user license agreement for using ``cordic``. |
|
76 |
|
|
+-----------------------+------------------------------------------------------+
|
77 |
|
|
| README | This file. |
|
78 |
|
|
+-----------------------+------------------------------------------------------+
|
79 |
|
|
| README.html | HTML version of README. |
|
80 |
|
|
+-----------------------+------------------------------------------------------+
|
81 |
|
|
| README.pdf | PDF version of README. |
|
82 |
|
|
+-----------------------+------------------------------------------------------+
|
83 |
|
|
| rst2docs.sh | Bash script for generating the HTML and PDF versions.|
|
84 |
|
|
+-----------------------+------------------------------------------------------+
|
85 |
|
|
| VERSION | Current version of the CORDIC IP cores. |
|
86 |
|
|
+-----------------------+------------------------------------------------------+
|
87 |
|
|
| /rtl/vhdl | RTL source code directory for the IP core |
|
88 |
|
|
+-----------------------+------------------------------------------------------+
|
89 |
|
|
| cordic.vhd | Automatically-generated VHDL design file |
|
90 |
|
|
| | (hand-optimized for operation chaining). |
|
91 |
|
|
+-----------------------+------------------------------------------------------+
|
92 |
|
|
| cordic_cdt_pkg.vhd | Package containing declarations. |
|
93 |
|
|
+-----------------------+------------------------------------------------------+
|
94 |
|
|
| /sim/rtl_sim | RTL simulation files directory |
|
95 |
|
|
+-----------------------+------------------------------------------------------+
|
96 |
|
|
| /sim/rtl_sim/bin | RTL simulation scripts directory |
|
97 |
|
|
+-----------------------+------------------------------------------------------+
|
98 |
|
|
| cordic.mk | Unix/Cygwin makefile for running a GHDL simulation. |
|
99 |
|
|
+-----------------------+------------------------------------------------------+
|
100 |
|
|
| /sim/rtl_sim/out | Dumps and other useful output from RTL simulation |
|
101 |
|
|
+-----------------------+------------------------------------------------------+
|
102 |
|
|
| cordic_alg_test_res- | Check this file for output. |
|
103 |
|
|
| ults.txt | |
|
104 |
|
|
+-----------------------+------------------------------------------------------+
|
105 |
|
|
| /sim/rtl_sim/run | Files for running RTL simulations |
|
106 |
|
|
+-----------------------+------------------------------------------------------+
|
107 |
|
|
| cordic.sh | Unix/Cygwin bash shell script for running a GHDL |
|
108 |
|
|
| | simulation. |
|
109 |
|
|
+-----------------------+------------------------------------------------------+
|
110 |
|
|
| cordic_test_data.txt | Reference vectors. |
|
111 |
|
|
+-----------------------+------------------------------------------------------+
|
112 |
|
|
| /sim/rtl_sim/vhdl | VHDL source files used for running RTL simulations |
|
113 |
|
|
+-----------------------+------------------------------------------------------+
|
114 |
|
|
| operpack.vhd | Reduced version of Nikolaos Kavvadias' operator |
|
115 |
|
|
| | library. |
|
116 |
|
|
+-----------------------+------------------------------------------------------+
|
117 |
|
|
| std_logic_textio.vhd | Modified version of a testbench-related package. |
|
118 |
|
|
+-----------------------+------------------------------------------------------+
|
119 |
|
|
| /sw | Software utilities |
|
120 |
|
|
+-----------------------+------------------------------------------------------+
|
121 |
|
|
| cordic.c | Reference C implementation for test vector |
|
122 |
|
|
| | generation. |
|
123 |
|
|
+-----------------------+------------------------------------------------------+
|
124 |
|
|
| cordic.dot | CDFG of the cordic procedure as a Graphviz file. |
|
125 |
|
|
+-----------------------+------------------------------------------------------+
|
126 |
|
|
| cordic.dot.png | PNG image for the above. |
|
127 |
|
|
+-----------------------+------------------------------------------------------+
|
128 |
|
|
| cordic.nac | The NAC description of the CORDIC application. |
|
129 |
|
|
+-----------------------+------------------------------------------------------+
|
130 |
|
|
| cordic-flp.txt | Comparison of fixed-point to floating-point CORDIC |
|
131 |
|
|
| | (using calls to the ``math`` C library) results. |
|
132 |
|
|
+-----------------------+------------------------------------------------------+
|
133 |
|
|
| /syn/xise | Synthesis files for use with Xilinx ISE |
|
134 |
|
|
+-----------------------+------------------------------------------------------+
|
135 |
|
|
| /syn/xise/bin | Synthesis scripts directory |
|
136 |
|
|
+-----------------------+------------------------------------------------------+
|
137 |
|
|
| xst.mk | Standard Makefile for command-line usage of ISE. |
|
138 |
|
|
+-----------------------+------------------------------------------------------+
|
139 |
|
|
| /syn/xise/log | Generated log files from the synthesis process |
|
140 |
|
|
+-----------------------+------------------------------------------------------+
|
141 |
|
|
| cordic-xst14.6.txt | Synthesis report from Xilinx ISE (XST) 14.6. |
|
142 |
|
|
+-----------------------+------------------------------------------------------+
|
143 |
|
|
| /syn/xise/run | Files for running synthesis |
|
144 |
|
|
+-----------------------+------------------------------------------------------+
|
145 |
|
|
| syn.sh | Bash shell script for synthesizing ``cordic`` |
|
146 |
|
|
| | architectures with ISE. |
|
147 |
|
|
+-----------------------+------------------------------------------------------+
|
148 |
|
|
|
149 |
|
|
|
150 |
|
|
3. Usage
|
151 |
|
|
========
|
152 |
|
|
|
153 |
|
|
1. Run the shell script from a Unix/Linux/Cygwin command line.
|
154 |
|
|
|
155 |
|
|
| ``$ ./cordic.sh``
|
156 |
|
|
|
157 |
|
|
After this process, the ``cordic_alg_test_results.txt`` file is generated
|
158 |
|
|
containing simulation results. The GHDL simulation will also generate
|
159 |
|
|
a VCD (waveform) file that can be opened with GTKwave:
|
160 |
|
|
|
161 |
|
|
| ``$gtkwave cordic_fsmd.vcd``
|
162 |
|
|
|
163 |
|
|
2. Create, build and run a Modelsim project with the following files (in
|
164 |
|
|
this order):
|
165 |
|
|
|
166 |
|
|
::
|
167 |
|
|
|
168 |
|
|
operpack.vhd
|
169 |
|
|
std_logic_textio.vhd
|
170 |
|
|
cordic_cdt_pkg.vhd
|
171 |
|
|
ram.vhd
|
172 |
|
|
cordic.vhd
|
173 |
|
|
cordic_tb.vhd
|
174 |
|
|
|
175 |
|
|
|
176 |
|
|
4. Synthesis
|
177 |
|
|
============
|
178 |
|
|
|
179 |
|
|
The CORDIC IP cores distribution includes scripts for logic synthesis automation
|
180 |
|
|
supporting Xilinx ISE. The corresponding synthesis script can be edited in order
|
181 |
|
|
to specify the following for adapting to the user's setup:
|
182 |
|
|
|
183 |
|
|
- ``XDIR``: the path to the ``/bin`` subdirectory of the Xilinx ISE/XST
|
184 |
|
|
installation where the ``xst.exe`` executable is placed
|
185 |
|
|
- ``arch``: specific FPGA architecture (device family) to be used for synthesis
|
186 |
|
|
- ``part``: specific FPGA part (device) to be used for synthesis
|
187 |
|
|
|
188 |
|
|
4.1. Running the synthesis script
|
189 |
|
|
---------------------------------
|
190 |
|
|
|
191 |
|
|
For running the Xilinx ISE synthesis tool, change directory to the
|
192 |
|
|
``/syn/xise/run`` subdirectory from the top-level directory of CORDIC:
|
193 |
|
|
|
194 |
|
|
| ``$ ./syn/xise/run``
|
195 |
|
|
|
196 |
|
|
and execute the corresponding script (for synthesizing ``hwlu``):
|
197 |
|
|
|
198 |
|
|
| ``$ ./syn.sh``
|
199 |
|
|
|
200 |
|
|
The synthesis procedure invokes several Xilinx ISE command-line tools for logic
|
201 |
|
|
synthesis as described in the corresponding Makefile, found in the
|
202 |
|
|
the ``/syn/xise/bin`` subdirectory.
|
203 |
|
|
|
204 |
|
|
Typically, this process includes the following:
|
205 |
|
|
|
206 |
|
|
- Generation of the ``*.xst`` synthesis script file.
|
207 |
|
|
- Generation of the ``*.ngc`` gate-level netlist file in NGC format.
|
208 |
|
|
- Building the corresponding ``*.ngd`` file.
|
209 |
|
|
- Performing mapping using ``map`` which generates the corresponding ``*.ncd``
|
210 |
|
|
file.
|
211 |
|
|
- Place-and-routing using ``par`` which updates the corresponding ``*.ncd``
|
212 |
|
|
file.
|
213 |
|
|
- Tracing critical paths using ``trce`` for reoptimizing the ``*.ncd`` file.
|
214 |
|
|
- Bitstream generation (``*.bit``) using ``bitgen``, however with unused pins.
|
215 |
|
|
|
216 |
|
|
Finally, the ``cordic.bit`` bitstream file is produced.
|
217 |
|
|
|
218 |
|
|
|
219 |
|
|
5. Prerequisities
|
220 |
|
|
=================
|
221 |
|
|
|
222 |
|
|
- Standard UNIX-based tools (tested with gcc-4.6.2 on MinGW/x86) [optional if
|
223 |
|
|
you use Modelsim].
|
224 |
|
|
|
225 |
|
|
* make
|
226 |
|
|
* bash (shell)
|
227 |
|
|
|
228 |
|
|
For this reason, MinGW (http://www.mingw.org) or Cygwin
|
229 |
|
|
(http://sources.redhat.com/cygwin) are suggested, since POSIX emulation
|
230 |
|
|
environments of sufficient completeness.
|
231 |
|
|
|
232 |
|
|
- GHDL simulator (http://ghdl.free.fr) [optional if you use Modelsim].
|
233 |
|
|
Provides the ``ghdl`` executable (has several Windows versions, with
|
234 |
|
|
0.29.1 and 0.31 being the latest). It also installs GTKwave on Windows.
|
235 |
|
|
Note that the latest version (0.31) from
|
236 |
|
|
http://sourceforge.net/project/ghdl-updates/ does not include GTKwave.
|
237 |
|
|
|
238 |
|
|
- Xilinx ISE (free ISE webpack is available from the Xilinx website):
|
239 |
|
|
http://www.xilinx.com)
|
240 |
|
|
The 14.6 version on Windows 7/64-bit is known to work.
|