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-------------------------------------------------------------------------------

-- Title      : Data selector

-- Project    : 

-------------------------------------------------------------------------------

-- File       : max_finder.vhd

-- Author     : Wojciech M. Zabolotny ( wzab01<at>gmail.com )

-- Company    :

-- License    : BSD

-- Created    : 2013-11-01

-- Last update: 2015-09-24

-- Platform   : 

-- Standard   : VHDL'93/02

-------------------------------------------------------------------------------

-- Description: This block selects from all available channels those

--              which are surrounding channel number "sel"

-------------------------------------------------------------------------------

-- Copyright (c) 2014 

-------------------------------------------------------------------------------

-- Revisions  :

-- Date        Version  Author  Description

-- 2013-11-01  1.0      WZab    Created

-------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.NUMERIC_STD.all;

library work;

use work.lateq_pkg.all;

use work.ex1_pkg.all;

entity data_sel is

  generic (

    N_SIDE_CHANS : integer);

  port (

    dins  : in  T_INPUT_DATA_MRK;

    dout  : out T_SEL_DATA;

    sel   : in  integer range 0 to C_N_CHANNELS-1;

    clk   : in  std_logic;

    rst_p : in  std_logic

    );

end data_sel;

architecture beh of data_sel is

begin

  ds1 : process (clk) is

    variable j : integer;

  begin  -- process ds1

    if clk'event and clk = '1' then     -- rising clock edge

      if rst_p = '1' then               -- synchronous reset (active high)

        dout <= C_SEL_DATA_INIT;

      else

        -- We select data surrounding the maximum.

        -- There is a problem if the maximum occures on edges of the detector.

        -- However in this example we simply add empty data

        for i in -N_SIDE_CHANS to N_SIDE_CHANS loop

          j := sel + i;

          if j < 0 then

            dout.data_vec(i+N_SIDE_CHANS) <= C_SINGLE_DATA_INIT;

          elsif j > C_N_CHANNELS-1 then

            dout.data_vec(i+N_SIDE_CHANS) <= C_SINGLE_DATA_INIT;

          else

            dout.data_vec(i+N_SIDE_CHANS) <= dins.data_vec(j);

          end if;

        end loop;

        -- pragma translate_off

        dout.lateq_mrk <= dins.lateq_mrk;

      -- pragma translate_on

      end if;

    end if;

  end process ds1;

end beh;