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wzab |
-------------------------------------------------------------------------------
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-- Title : ex1_pkg package
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-- Project :
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-------------------------------------------------------------------------------
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-- File : ex1_pkg.vhd
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-- Author : Wojciech M. Zabolotny ( wzab01<at>gmail.com )
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-- Company :
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-- License : BSD
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-- Created : 2013-11-01
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-- Last update: 2015-09-24
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: Package with definitions for the simple system
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-- demonstrating a method of latency balancing
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-------------------------------------------------------------------------------
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-- Copyright (c) 2015
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2013-11-01 1.0 WZab Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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use IEEE.math_real.all;
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library work;
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use work.lateq_pkg.all;
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package ex1_pkg is
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-- Constants describing the processor
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constant C_N_CHANNELS : integer := 64;
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constant C_DATA_WIDTH : integer := 9;
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constant C_N_SIDE_CHANS : integer := 3; -- number of neighbouring channels
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-- Type describing the position of the maximum of the signal
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subtype T_POS_INT is integer range 0 to C_N_CHANNELS-1;
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constant C_POS_INT_INIT : T_POS_INT := 0;
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-- Position of the maximum with time marker
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type T_POS_INT_MRK is record
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position : T_POS_INT;
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-- pragma translate_off
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lateq_mrk : T_LATEQ_MRK;
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-- pragma translate_on
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end record T_POS_INT_MRK;
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constant C_POS_INT_MRK_INIT : T_POS_INT_MRK := (
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-- pragma translate_off
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lateq_mrk => C_LATEQ_MRK_INIT,
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-- pragma translate_on
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position => C_POS_INT_INIT
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);
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-- Data from a single channel
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subtype T_SINGLE_DATA is signed(C_DATA_WIDTH-1 downto 0);
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constant C_SINGLE_DATA_INIT : T_SINGLE_DATA := (others => '0');
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-- Data from a single channel with time marker,position marker and validity marker
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type T_SINGLE_DATA_WITH_POS is record
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-- pragma translate_off
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lateq_mrk : T_LATEQ_MRK;
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-- pragma translate_on
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position : T_POS_INT;
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valid : boolean;
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data : T_SINGLE_DATA;
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end record T_SINGLE_DATA_WITH_POS;
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constant C_SINGLE_DATA_WITH_POS_INIT : T_SINGLE_DATA_WITH_POS := (
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-- pragma translate_off
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lateq_mrk => C_LATEQ_MRK_INIT,
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-- pragma translate_on
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position => C_POS_INT_INIT,
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valid => false,
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data => C_SINGLE_DATA_INIT
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);
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-- Function comparing two data with markers
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function ex1_cmp_data (
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constant v1, v2 : T_SINGLE_DATA_WITH_POS)
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return integer; -- range -1 to 1;
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-- Vector with all input data
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type T_INPUT_DATA is array (0 to C_N_CHANNELS-1) of T_SINGLE_DATA;
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constant C_INPUT_DATA_INIT : T_INPUT_DATA := (others => C_SINGLE_DATA_INIT);
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-- Record with all input data and time marker - internal form
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type T_INPUT_DATA_MRK is record
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-- pragma translate_off
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lateq_mrk : T_LATEQ_MRK;
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-- pragma translate_on
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data_vec : T_INPUT_DATA;
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end record T_INPUT_DATA_MRK;
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constant C_INPUT_DATA_MRK_INIT : T_INPUT_DATA_MRK := (
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-- pragma translate_off
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lateq_mrk => C_LATEQ_MRK_INIT,
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-- pragma translate_on
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data_vec => (others => C_SINGLE_DATA_INIT)
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);
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-- Here we calculate widths of words needed to store intermadiate calculation
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-- results. We may assign too many bits. During the synthesis unused bits
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-- will be optimized out.
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constant C_CALC_SUM_WIDTH : integer := 2*integer(ceil(log2(real(1+2*C_N_SIDE_CHANS))))+C_DATA_WIDTH;
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subtype T_CALC_DATA is signed(C_CALC_SUM_WIDTH-1 downto 0);
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constant C_CALC_DATA_INIT : T_CALC_DATA := (others => '0');
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-- Type storing the calculation results with time merker
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type T_CALC_DATA_MRK is record
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-- pragma translate_off
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lateq_mrk : T_LATEQ_MRK;
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-- pragma translate_on
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valid : boolean;
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sum : T_CALC_DATA;
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end record T_CALC_DATA_MRK;
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constant C_CALC_DATA_MRK_INIT : T_CALC_DATA_MRK := (
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-- pragma translate_off
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lateq_mrk => C_LATEQ_MRK_INIT,
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-- pragma translate_on
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valid => false,
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sum => C_CALC_DATA_INIT
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);
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-- It would be nice to define the vectors with selected data as follows:
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-- type T_SEL_DATA_VEC is array (-C_N_SIDE_CHANS to C_N_SIDE_CHANS) of T_SINGLE_DATA;
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-- Unfortunately it creates problems with other blocks.
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-- Therefore I must define them with indices starting from 0
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-- Vector with selected data
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type T_SEL_DATA_VEC is array (0 to 2*C_N_SIDE_CHANS) of T_SINGLE_DATA;
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-- Vector with selected data after calculations
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type T_CALC_DATA_VEC is array (0 to 2*C_N_SIDE_CHANS) of T_CALC_DATA;
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-- Vector with selected data and time marker
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type T_SEL_DATA is record
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-- pragma translate_off
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lateq_mrk : T_LATEQ_MRK;
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-- pragma translate_on
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data_vec : T_SEL_DATA_VEC;
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end record T_SEL_DATA;
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constant C_SEL_DATA_INIT : T_SEL_DATA := (
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-- pragma translate_off
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lateq_mrk => C_LATEQ_MRK_INIT,
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-- pragma translate_on
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data_vec => (others => C_SINGLE_DATA_INIT)
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);
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-- Vector with calculation results and time marker
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type T_CALC_SEL_DATA is record
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-- pragma translate_off
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lateq_mrk : T_LATEQ_MRK;
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-- pragma translate_on
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data_vec : T_CALC_DATA_VEC;
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end record T_CALC_SEL_DATA;
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constant C_CALC_SEL_DATA_INIT : T_CALC_SEL_DATA := (
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-- pragma translate_off
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lateq_mrk => C_LATEQ_MRK_INIT,
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-- pragma translate_on
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data_vec => (others => C_CALC_DATA_INIT)
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);
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end package ex1_pkg;
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package body ex1_pkg is
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function ex1_cmp_data (
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constant v1, v2 : T_SINGLE_DATA_WITH_POS)
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return integer is
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begin -- function ex1_cmp_data
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if v1.data > v2.data then
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return 1;
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elsif v2.data > v1.data then
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return -1;
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else
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return 0;
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end if;
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end function ex1_cmp_data;
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end package body ex1_pkg;
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