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-- Title      : Testbench for design "ex1_proc"

-- Project    : 

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-- File       : ex1_proc_tb.vhd

-- Author     : Wojciech M. Zabolotny  <wzab@wzdell.nasz.dom>

-- Company    : 

-- License    : BSD

-- Created    : 2015-09-09

-- Last update: 2015-09-23

-- Platform   : 

-- Standard   : VHDL'93/02

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-- Description: 

-------------------------------------------------------------------------------

-- Copyright (c) 2015 

-------------------------------------------------------------------------------

-- Revisions  :

-- Date        Version  Author  Description

-- 2015-09-09  1.0      wzab    Created

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use IEEE.NUMERIC_STD.all;

use ieee.math_real.all;

library work;

use work.lateq_pkg.all;

use work.ex1_pkg.all;

use work.ex1_trees_pkg.all;

-------------------------------------------------------------------------------

entity ex1_proc_tb is

end entity ex1_proc_tb;

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architecture test of ex1_proc_tb is

  -- component ports

  signal din        : T_INPUT_DATA := C_INPUT_DATA_INIT;

  signal position   : T_POS_INT;

  signal wgt_charge : T_CALC_DATA;

  signal charge     : T_CALC_DATA;

  signal rst_p      : std_logic    := '1';

  -- clock

  signal clk : std_logic := '1';

begin  -- architecture test

  -- component instantiation

  DUT : entity work.ex1_proc

    port map (

      din        => din,

      position   => position,

      wgt_charge => wgt_charge,

      charge     => charge,

      clk        => clk,

      rst_p      => rst_p);

  -- clock generation

  Clk <= not Clk after 10 ns;

  -- waveform generation

  WaveGen_Proc : process

    procedure clean_ins is

    begin  -- procedure clean_ins

      din <= C_INPUT_DATA_INIT;

    end procedure clean_ins;

  begin

    -- insert signal assignments here

    wait until Clk = '1';

    rst_p   <= '0';

    wait until rising_edge(Clk);

    wait until rising_edge(Clk);

    wait until rising_edge(Clk);

    din(13) <= to_signed(20, C_DATA_WIDTH);

    din(14) <= to_signed(80, C_DATA_WIDTH);

    din(15) <= to_signed(100, C_DATA_WIDTH);

    din(16) <= to_signed(40, C_DATA_WIDTH);

    din(17) <= to_signed(10, C_DATA_WIDTH);

    wait until rising_edge(Clk);

    clean_ins;

    wait until rising_edge(Clk);

    wait until rising_edge(Clk);

    wait until rising_edge(Clk);

    din(23) <= to_signed(5, C_DATA_WIDTH);

    din(24) <= to_signed(30, C_DATA_WIDTH);

    din(25) <= to_signed(100, C_DATA_WIDTH);

    din(26) <= to_signed(90, C_DATA_WIDTH);

    din(27) <= to_signed(40, C_DATA_WIDTH);

    wait until rising_edge(Clk);

    clean_ins;

    wait until rising_edge(Clk);

    wait until rising_edge(Clk);

    wait until rising_edge(Clk);

    din     <= C_INPUT_DATA_INIT;

    wait until rising_edge(Clk);

    wait until rising_edge(Clk);

    wait;

  end process WaveGen_Proc;

  -- printing of the results

  r1 : process (clk) is

    variable f_charge     : real := 0.0;

    variable f_wgt_charge : real := 0.0;

    variable f_position   : real := 0.0;

  begin  -- process r1

    if clk'event and clk = '1' then     -- rising clock edge

      if rst_p = '1' then               -- synchronous reset (active high)

        null;

      else

        if charge > 10 then

          f_charge     := real(to_integer(charge));

          f_wgt_charge := real(to_integer(wgt_charge));

          f_position   := real(position);

          f_position   := f_position + f_wgt_charge/f_charge;

          report "Hit with charge: " & real'image(f_charge) & " at " & real'image(f_position) severity note;

        end if;

      end if;

    end if;

  end process r1;

end architecture test;

-------------------------------------------------------------------------------

configuration ex1_proc_tb_test_cfg of ex1_proc_tb is

  for test

  end for;

end ex1_proc_tb_test_cfg;

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