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wzab |
#!/usr/bin/python3
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# This file was written by Wojciech M. Zabolotny (wzab@ise.pw.edu.pl)
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# And is published under BSD license
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import os
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import sys
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import string
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""" Below we define the entity template, which will be later filled with generated data
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"""
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EntTemp="""
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-------------------------------------------------------------------------------
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-- Title : Latency checker/equalizer for pipelined designs
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-- Project :
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-------------------------------------------------------------------------------
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-- This file is autmatically generated, please don't
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-- edit it manually.
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-- This file is generated by the tool written by Wojciech M. Zabolotny
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-- ( wzab01<at>gmail.com )
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-- This file is licensed under the BSD license
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-- Libraries used
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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${packages}
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entity ${entity_name} is
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generic (
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LEQ_ID : string := "X"
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);
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port (
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-- groups of inputs and outputs automatically generated
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${ports}
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-- system ports
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clk : in std_logic;
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rst_p : in std_logic
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);
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end ${entity_name};
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architecture beh of ${entity_name} is
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-- declarations
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-- definition of types and signals used in delay lines
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${types_and_dels}
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begin
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-- signal assignment and processes for delay lines
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${delay_lines}
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${delay_check}
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${delay_equalize}
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end beh;
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"""
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def type2init(tname):
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""" This function converts the type name into the name of its initialization
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constant. Of course it is the user responsibility to define the appropriate
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types and constants
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"""
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tname = tname.upper()
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if tname[0:2] != "T_":
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raise(Exception("Wrong type name, should start with T_"))
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tname="C"+tname[1:]+"_INIT"
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return tname
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if len(sys.argv)<4:
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appname=sys.argv[0]
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print(string.Template("""
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Correct calling syntax:
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${appname} entity_name output_file type_0 type_1 type_2
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""").substitute(locals()))
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sys.exit(0)
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fout=open(sys.argv[2], "w")
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ndef={}
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ndef['entity_name']=sys.argv[1]
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types = sys.argv[3:]
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ndef['packages']="""
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use work.lateq_pkg.all;
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use work.ex1_pkg.all;
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use work.lateq_read_pkg.all;
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"""
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# Generate ports definition
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tdef=""
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for i in range(0, len(types)):
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tdef += " in"+str(i)+" : in "+types[i]+";\n"
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tdef += " out"+str(i)+" : out "+types[i]+";\n"
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ndef['ports'] = tdef
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# Generate types and signals for delay lines
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tdef=""
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for i in range(0, len(types)):
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tdef += " type TDEL"+str(i)+" is array (integer range <>) of "+types[i]+";\n"
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tdef += " constant DLEN"+str(i)+" : integer := lateq_read_delays(LEQ_ID,"+str(i)+ ");\n"
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tdef += " signal s_out"+str(i)+" : "+types[i]+";\n"
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tdef += " signal del"+str(i)+" : TDEL"+str(i)+"(0 to DLEN"+str(i)+ ") := (others => "+type2init(types[i])+");\n"
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ndef['types_and_dels'] = tdef
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# Generate delay lines together with their processes
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tdef=""
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for i in range(0, len(types)):
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# Assign appropriate positions in the delay lines to input and output
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tdef += " s_out"+str(i)+ "<= del"+str(i)+"(0);\n"
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# If necessary, generate the process, servicing the delay line
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tdef += " gp"+str(i)+": if DLEN"+str(i)+" > 0 generate\n"
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tdef += " pd"+str(i)+" : process(clk,rst_p) is\n"
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tdef += " begin\n"
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tdef += " if clk'event and clk='1' then\n"
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tdef += " if rst_p='1' then\n"
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tdef += " for i in 0 to DLEN"+str(i)+"-1 loop \n"
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tdef += " del"+str(i)+"(i) <= "+type2init(types[i])+";\n"
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tdef += " end loop;\n"
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tdef += " else\n"
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tdef += " del"+str(i)+"(DLEN"+str(i)+"-1) <= in"+str(i)+";\n"
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tdef += " for i in 1 to DLEN"+str(i)+"-1 loop \n"
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tdef += " del"+str(i)+"(i-1) <= del"+str(i)+"(i);\n"
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tdef += " end loop;\n"
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tdef += " end if;\n"
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tdef += " end if;\n"
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tdef += " end process pd"+str(i)+";\n"
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tdef += " end generate gp"+str(i)+";\n"
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# Generate signal path for case when delay is 0
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tdef += " gn"+str(i)+": if DLEN"+str(i)+" = 0 generate\n"
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tdef += " del"+str(i)+"(0) <= in"+str(i)+";\n"
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tdef += " end generate gn"+str(i)+";\n"
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tdef += "\n"
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ndef['delay_lines'] = tdef
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# Generate the delay checking and reporting part (only in simulation)
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tdef=""
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tdef += " --pragma translate off\n"
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tdef += " pc : process(clk,rst_p) is\n"
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tdef += " begin\n"
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tdef += " if clk'event and clk='1' then\n"
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tdef += " if rst_p='1' then\n"
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tdef += " null;\n"
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tdef += " else\n"
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tdef += " if C_LATEQ_MODE=0 then\n"
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tdef += " -- Analyzis mode, report delays\n"
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for i in range(0,len(types)):
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tdef += " lateq_report_delay(LEQ_ID,"+str(i)+",in"+str(i)+".lateq_mrk);\n"
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tdef += " lateq_report_end(LEQ_ID);\n"
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tdef += " elsif C_LATEQ_MODE=1 then\n"
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tdef += " -- Final verification mode, assert output latency equality\n"
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for i in range(1,len(types)):
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tdef += " if s_out0.lateq_mrk /= s_out"+str(i)+".lateq_mrk then\n"
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tdef += " report LEQ_ID & \" inequal latencies: out0=\" & \n"
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tdef += " lateq_mrk_to_str(s_out0.lateq_mrk) & \", out"+str(i)+"=\" &\n"
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tdef += " lateq_mrk_to_str(s_out"+str(i)+".lateq_mrk) severity FAILURE;\n"
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tdef += " end if;\n"
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tdef += " end if;\n"
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tdef += " end if;\n"
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tdef += " end if;\n"
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tdef += " end process pc;\n"
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tdef += " --pragma translate on\n"
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ndef['delay_check'] = tdef
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# Generate the delay adjusting part
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# Idea is to find the smallest time marker and to propagate it to all outputs.
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tdef = ""
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tdef += " pu : process("
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for i in range(0, len(types)):
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if i>0:
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tdef += ", "
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tdef += "s_out"+str(i)
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tdef += ") is\n"
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tdef += "--pragma translate off\n"
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tdef += " variable dmin : T_LATEQ_MRK;\n"
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tdef += "--pragma translate on\n"
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tdef += " begin\n"
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for i in range(0, len(types)):
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tdef += " out"+str(i)+" <= s_out"+str(i)+";\n"
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tdef += "--pragma translate off\n"
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# Next part should be performed only for LATEQ_MODE=0
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tdef += " if C_LATEQ_MODE=0 then\n"
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tdef += " dmin := s_out0.lateq_mrk;\n"
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for i in range(0, len(types)):
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tdef += " if lateq_mrk_cmp(dmin,s_out"+str(i)+".lateq_mrk) > 0 then\n"
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tdef += " dmin := s_out"+str(i)+".lateq_mrk;\n"
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tdef += " end if;\n"
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tdef += "-- now we have found the dmin, so set it in all outputs\n"
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for i in range(0, len(types)):
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tdef += " out"+str(i)+".lateq_mrk <= dmin;\n"
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tdef += " end if;\n"
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tdef += "--pragma translate on\n"
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tdef += " end process pu;\n"
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ndef['delay_equalize'] = tdef
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tout=string.Template(EntTemp).substitute(ndef)
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fout.write(tout)
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fout.close()
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